ECE 545 Lecture 7. VHDL Description of Basic Combinational & Sequential Circuit Building Blocks. Required reading. Fixed Shifters & Rotators

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1 EE 55 Lecture 7 VHL escription o Basic ombinational & Sequential ircuit Building Blocks Required reading P. hu, RTL Hardare esign using VHL hapter 7, ombinational ircuit esign: Practice hapter 5., VHL Process hapter 8, Sequential ircuit esign: Principle (ecept subchapter 8.6) Slides or hapter 8, available at George Mason University 2 Fied Logical Shit Right in VHL SIGNL : ST_LOGI_VETOR(3 OWNTO ); SIGNL : ST_LOGI_VETOR(3 OWNTO ); Fied Shiters & Rotators (3) (2) () () >> L (3) (2) () EE 8 FPG and SI esign ith VHL 3 Fied Logical Shit Right in VHL SIGNL : ST_LOGI_VETOR(3 OWNTO ); SIGNL : ST_LOGI_VETOR(3 OWNTO ); Fied rithmetic Shit Right in VHL SIGNL : ST_LOGI_VETOR(3 OWNTO ); SIGNL : ST_LOGI_VETOR(3 OWNTO ); (3) (2) () () (3) (2) () () >> L >> (3) (2) () (3) (3) (2) () <= '' & (3 donto ); 5 6

2 Fied rithmetic Shit Right in VHL SIGNL : ST_LOGI_VETOR(3 OWNTO ); SIGNL : ST_LOGI_VETOR(3 OWNTO ); Fied Logical Shit Let in VHL SIGNL : ST_LOGI_VETOR(3 OWNTO ); SIGNL : ST_LOGI_VETOR(3 OWNTO ); (3) (2) () () (3) (2) () () >> (3) (3) (2) () << L (2) () () <= (3) & (3 donto ); 7 8 Fied Logical Shit Let in VHL SIGNL : ST_LOGI_VETOR(3 OWNTO ); SIGNL : ST_LOGI_VETOR(3 OWNTO ); Fied Rotation Let in VHL SIGNL : ST_LOGI_VETOR(3 OWNTO ); SIGNL : ST_LOGI_VETOR(3 OWNTO ); (3) (2) () () (3) (2) () () << L (2) () () <<< (2) () () (3) <= (2 donto ) & ''; 9 Fied Rotation Let in VHL SIGNL : ST_LOGI_VETOR(3 OWNTO ); SIGNL : ST_LOGI_VETOR(3 OWNTO ); (3) (2) () () Variable Rotators <<< (2) () () (3) <= (2 donto ) & (3); EE 8 FPG and SI esign ith VHL 2 2

3 8bit Variable Rotator Let 8 3 B <<< B Multipleers 8 To be covered during the net class 3 EE 8 FPG and SI esign ith VHL 2to Multipleer 2to Multipleer s s s s (a) Graphical symbol (b) Truth table (a) Graphical symbol (b) Truth table VHL: VHL: <= WHEN s = '' ELSE ; or <= WHEN s = '' ELSE ; 5 6 ascade o to multipleers ascade o to multipleers 3 2 y 3 2 y VHL: s2 s VHL: s2 s <= WHEN s = '' ELSE 2 WHEN s2 = '' ELSE 3 ; 7 8 3

4 to Multipleer to Multipleer (a) Graphic symbol (b) Truth table (a) Graphic symbol (b) Truth table s s s s s s s s s s WITH s SELET <= WHEN "", WHEN "", 2 WHEN "", 3 WHEN OTHERS ; 9 2 2to ecoder (a) Truth table (b) Graphical symbol y 3 ecoders En y y y y 3 2 y 2 y En y y EE 8 FPG and SI esign ith VHL to ecoder 2to ecoder (a) Truth table (b) Graphical symbol y 3 (a) Truth table (b) Graphical symbol y 3 En y y y y 3 2 y 2 y y En y y y y 3 2 y 2 y y En y En y En <= En & ; WITH En SELET y <= "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN OTHERS ; 23 2

5 VHL code or a 2to ecoder entity USE ieee.std_logic_6.all ; ENTITY dec2to IS PORT ( : IN ST_LOGI_VETOR( OWNTO ) ; En : IN ST_LOGI ; y : OUT ST_LOGI_VETOR(3 OWNTO ) ) ; EN dec2to ; RHITETURE datalo OF dec2to IS SIGNL En : ST_LOGI_VETOR(2 OWNTO ) ; En <= En & ; WITH En SELET y <= "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN OTHERS ; EN datalo ; Encoders 25 EE 8 FPG and SI esign ith VHL 26 Priority Encoder Priority Encoder 2 3 y y z y 2 3 y y z y 3 2 y y z 3 2 y y d d z Priority Encoder VHL code or a Priority Encoder entity USE ieee.std_logic_6.all ; 3 y y 3 2 y y 2 z d d z y y <= "" WHEN (3) = '' ELSE "" WHEN (2) = '' ELSE "" WHEN () = '' ELSE "" ; z <= '' WHEN = "" ELSE '' ; ENTITY priority IS PORT ( : IN ST_LOGI_VETOR(3 OWNTO ) ; y : OUT ST_LOGI_VETOR( OWNTO ) ; z : OUT ST_LOGI ) ; EN priority ; RHITETURE datalo OF priority IS y <= "" WHEN (3) = '' ELSE "" WHEN (2) = '' ELSE "" WHEN () = '' ELSE "" ; z <= '' WHEN = "" ELSE '' ; EN datalo ;

6 dder mod dders X S Y 6 EE 8 FPG and SI esign ith VHL 3 32 VHL code or an dder mod 2 6 Signed and Unsigned Types USE ieee.std_logic_6.all ; USE ieee.numeric_std.all ; ENTITY adder6 IS PORT ( X : IN ST_LOGI_VETOR(5 OWNTO ) ; Y : IN ST_LOGI_VETOR(5 OWNTO ) ; S : OUT ST_LOGI_VETOR(5 OWNTO ) ) ; EN adder6 ; RHITETURE datalo OF adder6 IS S <= std_logic_vector(unsigned(x) + unsigned(y)); EN datalo ; Behave eactly like ST_LOGI_VETOR plus, they determine hether a given vector should be treated as a signed or unsigned number. Require USE ieee.numeric_std.all; bit Unsigned dder ddition o Unsigned Numbers () 6 6 USE ieee.std_logic_6.all ; USE ieee.numeric_std.all ; out X 6 + S Y in ENTITY adder6 IS PORT ( in : IN ST_LOGI ; X : IN ST_LOGI_VETOR(5 OWNTO ) ; Y : IN ST_LOGI_VETOR(5 OWNTO ) ; S : OUT ST_LOGI_VETOR(5 OWNTO ) ; out : OUT ST_LOGI ) ; EN adder6 ;

7 ddition o Unsigned Numbers (3) RHITETURE datalo OF adder6 IS signal Sum: unsigned(6 OWNTO ) ; Sum <= unsigned('' & X) + unsigned(y) + unsigned('' & in) ) ; S <= std_logic_vector(sum(5 donto )); out <= Sum(6) ; EN datalo ; Multipliers 37 EE 8 FPG and SI esign ith VHL 38 Unsigned vs. Signed Multiplication 88bit Unsigned Multiplier Unsigned Signed a * c b U bit Signed Multiplier 88bit Unsigned and Signed Multiplier a * c b S a cu b cs

8 Multiplication o signed and unsigned numbers LIBRRY ieee; USE ieee.std_logic_6.all; USE ieee.numeric_std.all ; entity multiply is port( a : in ST_LOGI_VETOR(7 donto ); b : in ST_LOGI_VETOR(7 donto ); cu : out ST_LOGI_VETOR(5 donto ); cs : out ST_LOGI_VETOR(5 donto ) ); end multiply; ROM architecture datalo o multiply is begin signed multiplication cs <= ST_LOGI_VETOR(SIGNE(a)*SIGNE(b)); unsigned multiplication cu <= ST_LOGI_VETOR(UNSIGNE(a)*UNSIGNE(b)); end datalo; 3 EE 8 FPG and SI esign ith VHL ROM 86 eample () ROM 86 eample (2) ddr 3 86 ROM out 6 LIBRRY ieee; USE ieee.std_logic_6.all; USE ieee.numeric_std.all; ENTITY rom IS EN rom; PORT ( ); ddr : IN ST_LOGI_VETOR(2 OWNTO ); out : OUT ST_LOGI_VETOR(5 OWNTO ) 5 6 ROM 86 eample (3) RHITETURE datalo OF rom IS SIGNL temp: INTEGER RNGE TO 7; TYPE vector_array IS RRY ( to 7) OF ST_LOGI_VETOR(5 OWNTO ); ONSTNT memory : vector_array := ( X"8", X"59", X"87", X"7853", X"65", X"62F", X"F72", X"F58"); temp <= to_integer(unsigned(ddr)); out <= memory(temp); ROM 86 eample () RHITETURE datalo OF rom IS TYPE vector_array IS RRY ( to 7) OF ST_LOGI_VETOR(5 OWNTO ); ONSTNT memory : vector_array := ( X"8", X"59", X"87", X"7853", X"65", X"62F", X"F72", X"F58"); out <= memory(to_integer(unsigned(ddr))); EN datalo; EN datalo; 7 8 8

9 Tristate Buer e e = Buers (a) tristate buer e e = (b) Equivalent circuit (c) Truth table EE 8 FPG and SI esign ith VHL 9 5 Tristate Buer Four types o Tristate Buers e e e (a) tristate buer e = <= WHEN (e(a) = '') ELSE 'Z'; <= not WHEN (b) (e = '') ELSE 'Z'; e Z Z e = (b) Equivalent circuit e e (c) Truth table <= WHEN (e(c) = '') ELSE 'Z'; <= not WHEN (d) (e = '') ELSE 'Z'; 5 52 Tristate Buer entity () Tristate Buer entity (2) LIBRRY ieee; USE ieee.std_logic_6.all; ENTITY tri_state IS PORT ( e: IN ST_LOGI; : IN ST_LOGI; : OUT ST_LOGI ); EN tri_state; RHITETURE datalo OF tri_state IS <= WHEN (e = ) ELSE Z ; EN datalo;

10 MLU Block iagram MUX_ MUX MLU Eample NEG_ MUX_ MUX_2 IN IN IN2 OUTPUT IN3 SEL SEL Y Y B B L L NEG_Y NEG_B MUX_ MLU: Entity eclaration MLU: rchitecture eclarative Section LIBRRY ieee; USE ieee.std_logic_6.all; ENTITY mlu IS PORT( NEG_ : IN ST_LOGI; NEG_B : IN ST_LOGI; NEG_Y : IN ST_LOGI; : IN ST_LOGI; B : IN ST_LOGI; L : IN ST_LOGI; L : IN ST_LOGI; Y : OUT ST_LOGI ); EN mlu; RHITETURE mlu_datalo OF mlu IS SIGNL : ST_LOGI; SIGNL B : ST_LOGI; SIGNL Y : ST_LOGI; SIGNL MUX_ : ST_LOGI; SIGNL MUX_ : ST_LOGI; SIGNL MUX_2 : ST_LOGI; SIGNL MUX_3 : ST_LOGI; SIGNL L: ST_LOGI_VETOR( OWNTO ); MLU rchitecture Body <= NOT WHEN (NEG_='') ELSE ; B<= NOT B WHEN (NEG_B='') ELSE B; Y <= NOT Y WHEN (NEG_Y='') ELSE Y; MUX_ <= N B; MUX_ <= OR B; MUX_2 <= XOR B; MUX_3 <= XNOR B; L <= L & L; ith (L) select Y <= MUX_ WHEN "", MUX_ WHEN "", MUX_2 WHEN "", MUX_3 WHEN OTHERS; ombinational Logic Synthesis or Beginners EN mlu_datalo; 59 EE 8 FPG and SI esign ith VHL 6

11 Simple rules or beginners Simple rules or beginners For combinational logic, use only concurrent statements concurrent signal assignment (Ü) conditional concurrent signal assignment (henelse) selected concurrent signal assignment (ithselecthen) For circuits composed o simple logic operations (logic gates) simple arithmetic operations (addition, subtraction, multiplication) shits/rotations by a constant use concurrent signal assignment (Ü) 6 62 Simple rules or beginners For circuits composed o multipleers decoders, encoders tristate buers use conditional concurrent signal assignment (henelse) (ending ith ELSE) selected concurrent signal assignment (ithselecthen) (ending ith WHEN OTHERS;) Eample: VHL code or a to MUX USE ieee.std_logic_6.all ; ENTITY muto IS PORT (,, 2, 3 : IN ST_LOGI ; s : IN ST_LOGI_VETOR( OWNTO ) ; : OUT ST_LOGI ) ; EN muto ; RHITETURE datalo OF muto IS WITH s SELET <= WHEN "", WHEN "", 2 WHEN "", 3 WHEN OTHERS ; EN datalo ; 63 6 henelse vs. ithselecthen () henelse vs. ithselecthen (2) "henelse" should be used hen: ) there is only one condition (and thus, only one else), as in the 2to MUX 2) conditions are independent o each other (e.g., they test values o dierent signals) 3) conditions relect priority (as in priority encoder); one ith the highest priority need to be tested irst. "ithselecthen" should be used hen there is ) more than one condition 2) conditions are closely related to each other (e.g., represent dierent ranges o values o the same signal) 3) all conditions have the same priority (as in the to MUX)

12 Let vs. right side o the assignment Let side Internal signals (deined in a given architecture) Ports o the mode out inout <= <= henelse ithselect <= Right side Epressions including: Internal signals (deined in a given architecture) Ports o the mode in inout Behavioral esign Style: Registers & ounters 67 EE 8 FPG and SI esign ith VHL 68 VHL escription Styles datalo oncurrent statements VHL escription Styles synthesizable structural behavioral omponents and Sequential statements interconnects Registers Shit registers ounters State machines and more i you are careul 69 Processes in VHL Processes escribe Sequential Behavior Processes in VHL re Very Poerul Statements llo to deine an arbitrary behavior that may be diicult to represent by a real circuit Not every process can be synthesized Use Processes ith aution in the ode to Be Synthesized Use Processes Freely in Testbenches 7 natomy o a Process PROESS ith a SENSITIVITY LIST OPTIONL [label:] PROESS [(sensitivity list)] [declaration part] statement part EN PROESS [label]; List o signals to hich the process is sensitive. Whenever there is an event on any o the signals in the sensitivity list, the process ires. Every time the process ires, it ill run in its entirety. WIT statements are NOT LLOWE in a processes ith SENSITIVITY LIST. label: process (sensitivity list) declaration part begin statement part end process;

13 omponent Equivalent o a Process priority: PROESS (clk) IF (3) = '' THEN y <= "" ; ELSIF (2) = '' THEN y <= "" ; ELSIF () = c THEN y <= a and b; ELSE z <= "" ; EN PROESS ; clk a b c priority ll signals hich appear on the let o signal assignment statement (<=) are outputs e.g. y, z ll signals hich appear on the sensitivity list are inputs e.g. clk ll signals hich appear on the right o signal assignment statement (<=) or in logic epressions are inputs e.g., a, b, c Note that not all inputs need to be included on the sensitivity list y z Registers 73 EE 8 FPG and SI esign ith VHL 7 latch liplop Graphical symbol Truth table Timing diagram (t+) (t) Graphical symbol Truth table (t+) (t) (t) Timing diagram t t 2 t 3 t t t 2 t 3 t Time Time latch liplop USE ieee.std_logic_6.all ; ENTITY latch IS PORT (, : IN ST_LOGI ; : OUT ST_LOGI) ; EN latch ; USE ieee.std_logic_6.all ; ENTITY liplop IS PORT (, : IN ST_LOGI ; : OUT ST_LOGI) ; EN liplop ; RHITETURE behavioral OF latch IS PROESS (, ) IF = '' THEN <= ; EN PROESS ; EN behavioral; RHITETURE behavioral2 OF liplop IS PROESS ( ) IF rising_edge() THEN <= ; EN PROESS ; EN behavioral2;

14 liplop liplop ith asynchronous reset USE ieee.std_logic_6.all ; USE ieee.std_logic_6.all ; ENTITY liplop IS PORT (, : IN ST_LOGI ; : OUT ST_LOGI) ; EN liplop ; ENTITY liplop_ar IS PORT (, Reset, : IN ST_LOGI ; : OUT ST_LOGI) ; EN liplop_ar ; Reset RHITETURE behavioral OF liplop IS PROESS ( ) IF 'EVENT N = '' THEN <= ; EN PROESS ; EN behavioral ; RHITETURE behavioral OF liplop_ar IS PROESS ( Reset, ) IF Reset = '' THEN <= '' ; ELSIF rising_edge() THEN <= ; EN PROESS ; EN behavioral ; 79 8 liplop ith synchronous reset USE ieee.std_logic_6.all ; ENTITY liplop_sr IS PORT (, Reset, : IN ST_LOGI ; : OUT ST_LOGI) ; EN liplop_sr ; RHITETURE behavioral OF liplop_sr IS PROESS() IF rising_edge() THEN IF Reset = '' THEN <= '' ; ELSE <= ; EN IF; EN PROESS ; EN behavioral ; Reset sychronous vs. Synchronous In the IF loop, asynchronous items are Beore the rising_edge() statement In the IF loop, synchronous items are ter the rising_edge() statement bit register ith asynchronous reset USE ieee.std_logic_6.all ; ENTITY reg8 IS PORT ( : IN ST_LOGI_VETOR(7 OWNTO ) ; Reset, : IN ST_LOGI ; : OUT ST_LOGI_VETOR(7 OWNTO ) ) ; EN reg8 ; RHITETURE behavioral OF reg8 IS PROESS ( Reset, ) IF Reset = '' THEN <= "" ; ELSIF rising_edge() THEN <= ; EN PROESS ; EN behavioral ;` EE 8 FPG and SI esign ith VHL 8 Reset 8 reg8 83 Nbit register ith asynchronous reset USE ieee.std_logic_6.all ; ENTITY regn IS GENERI ( N : INTEGER := 6 ) ; PORT ( : IN ST_LOGI_VETOR(N OWNTO ) ; Reset, : IN ST_LOGI ; : OUT ST_LOGI_VETOR(N OWNTO ) ) ; EN regn ; RHITETURE behavioral OF regn IS PROESS ( Reset, ) IF Reset = '' THEN <= (OTHERS => '') ; ELSIF rising_edge() THEN <= ; EN PROESS ; EN behavioral ; EE 8 FPG and SI esign ith VHL N Reset regn N 8

15 ord on generics Generics are typically integer values In this class, the entity inputs and outputs should be std_logic or std_logic_vector But the generics can be integer Generics are given a deault value GENERI ( N : INTEGER := 6 ) ; This value can be overritten hen entity is instantiated as a component Generics are very useul hen instantiating an otenused component Need a 6bit register in one place, and 6bit register in another an use the same generic code, just conigure them dierently Use o OTHERS OTHERS stand or any inde value that has not been previously mentioned. <= can be ritten as <= ( =>, OTHERS => ) <= can be ritten as <= (7 =>, =>, OTHERS => ) or <= (7 =>, OTHERS => ) <= can be ritten as <= ( donto =>, OTHERS => ) omponent Instantiation in VHL93 omponent Instantiation in VHL87 U: ENTITY ork.regn(behavioral) GENERI MP (N => ) PORT MP ( => z, Resetn => reset, => clk, => t ); U: regn GENERI MP (N => ) PORT MP ( => z, Resetn => reset, => clk, => t ); Nbit register ith enable Implementing to registers in a single process USE ieee.std_logic_6.all ; ENTITY regne IS GENERI ( N : INTEGER := 8 ) ; PORT ( : IN ST_LOGI_VETOR(N OWNTO ) ; Enable, : IN ST_LOGI ; : OUT ST_LOGI_VETOR(N OWNTO ) ) ; EN regne ; out_tmp En En out V_tmp En En V RHITETURE behavioral OF regne IS PROESS () IF rising_edge() THEN IF Enable = '' THEN <= ; EN IF; EN PROESS ; EN behavioral ; N Enable regn N lk Reset lk Reset

16 Implementing to registers in a single process Implementing to registers in a single process PROESS (lk, Reset) IF Reset= '' THEN out <= ''; V <= ''; ELSIF rising_edge(lk) THEN IF En = '' THEN out <= out_tmp ; V <= V_tmp; EN IF; EN PROESS ; out_tmp lk En En Reset out V_tmp lk EnV En Reset V 9 EE 8 FPG and SI esign ith VHL 92 Implementing to registers in a single process PROESS (lk, Reset) IF Reset = '' THEN out <= ; V <= ''; ELSIF rising_edge(lk) THEN IF En = '' THEN out <= out_tmp ; IF EnV = '' THEN V <= V_tmp; EN IF; EN PROESS ; ounters 93 EE 8 FPG and SI esign ith VHL 9 2bit upcounter ith synchronous reset bit upcounter ith asynchronous reset () USE ieee.std_logic_6.all ; USE ieee.numeric_std.all ; ENTITY upcount IS PORT ( lear, : IN ST_LOGI ; : OUT ST_LOGI_VETOR( OWNTO ) ) ; EN upcount ; RHITETURE behavioral OF upcount IS SIGNL ount : unsigned( OWNTO ); upcount: PROESS ( ) IF rising_edge() THEN IF lear = '' THEN ount <= "" ; ELSE ount <= ount + ; EN IF; EN PROESS; <= std_logic_vector(ount); EN behavioral; lear upcount 2 USE ieee.std_logic_6.all ; USE ieee.numeric_std.all ; ENTITY upcount_ar IS PORT (, Resetn, Enable : IN ST_LOGI ; : OUT ST_LOGI_VETOR (3 OWNTO )) ; EN upcount_ar ; Enable Resetn upcount

17 bit upcounter ith asynchronous reset (2) RHITETURE behavioral OF upcount _ar IS SIGNL ount : UNSIGNE (3 OWNTO ) ; PROESS (, Resetn ) IF Resetn = '' THEN ount <= "" ; ELSIF rising_edge() THEN IF Enable = '' THEN ount <= ount + ; EN PROESS ; <= std_logic_vector(ount) ; EN behavioral ; Enable Resetn upcount Shit Registers 97 EE 8 FPG and SI esign ith VHL 98 Shit register internal structure Shit Register With Parallel Load Load (3) (2) () () (3) Sin (2) () () Sin Enable Enable (3) (2) () () 99 bit shit register ith parallel load () USE ieee.std_logic_6.all ; ENTITY shit IS PORT ( : IN ST_LOGI_VETOR(3 OWNTO ) ; Enable : IN ST_LOGI ; Load : IN ST_LOGI ; Sin : IN ST_LOGI ; : IN ST_LOGI ; : OUT ST_LOGI_VETOR(3 OWNTO ) ) ; EN shit ; Enable Load Sin shit bit shit register ith parallel load (2) RHITETURE behavioral OF shit IS SIGNL t : ST_LOGI_VETOR(3 OWNTO ); PROESS () IF rising_edge() THEN IF Enable = THEN IF Load = '' THEN t <= ; ELSE EN IF; EN PROESS ; <= t; EN behavioral ; Enable Load Sin t <= Sin & t(3 donto ); shit 2 7

18 Nbit shit register ith parallel load () USE ieee.std_logic_6.all ; ENTITY shitn IS GENERI ( N : INTEGER := 8 ) ; PORT ( : IN ST_LOGI_VETOR(N OWNTO ) ; Enable : IN ST_LOGI ; Load : IN ST_LOGI ; Sin : IN ST_LOGI ; : IN ST_LOGI ; : OUT ST_LOGI_VETOR(N OWNTO ) ) ; EN shitn ; N Enable Load Sin N shitn Nbit shit register ith parallel load (2) RHITETURE behavioral OF shitn IS SIGNL t: ST_LOGI_VETOR(N OWNTO ); N PROESS () IF rising_edge() THEN IF Enable = THEN IF Load = '' THEN t <= ; ELSE EN IF; EN PROESS ; <= t; EN behavior al; Enable Load Sin t <= Sin & t(n donto ); N shitn 3 Nbit register ith enable USE ieee.std_logic_6.all ; Generic omponent Instantiation ENTITY regn IS GENERI ( N : INTEGER := 8 ) ; PORT ( : IN ST_LOGI_VETOR(N OWNTO ) ; Enable, : IN ST_LOGI ; : OUT ST_LOGI_VETOR(N OWNTO ) ) ; EN regn ; RHITETURE Behavior OF regn IS PROESS () IF ( rising_edge() ) THEN IF Enable = '' THEN <= ; EN IF; EN PROESS ; EN Behavior ; N Enable regn N EE 8 FPG and SI esign ith VHL 5 6 ircuit built o medium scale components s() Structural description eample () VHL93 USE ieee.std_logic_6.all ; r() r() r(2) r(3) r() r(5) s() p() p() p(2) p(3) 2 3 priority y y z q() q() ena En y Enable 3 z(3) t(3) y 2 z(2) t(2) y z() t() En y z() t() dec2to regne lk ENTITY priority_resolver IS PORT (r : IN ST_LOGI_VETOR(5 OWNTO ) ; s : IN ST_LOGI_VETOR( OWNTO ) ; clk : IN ST_LOGI; en : IN ST_LOGI; t : OUT ST_LOGI_VETOR(3 OWNTO ) ) ; EN priority_resolver; RHITETURE structural OF priority_resolver IS SIGNL p : ST_LOGI_VETOR (3 OWNTO ) ; SIGNL q : ST_LOGI_VETOR ( OWNTO ) ; SIGNL z : ST_LOGI_VETOR (3 OWNTO ) ; SIGNL ena : ST_LOGI ; 7 8 8

19 Structural description eample (2) VHL93 u: ENTITY ork.mu2to(datalo) PORT MP ( => r(), => r(), s => s(), => p()); p() <= r(2); p(2) <= r(3); u2: ENTITY ork.mu2to(datalo) PORT MP ( => r(), => r(5), s => s(), => p(3)); u3: ENTITY ork.priority(datalo) PORT MP ( => p, y => q, z => ena); Structural description eample (3) VHL93 u: ENTITY ork.dec2to (datalo) PORT MP ( => q, En => ena, y => z); u5: ENTITY ork.regne(behavioral) EN structural; GENERI MP (N => ) PORT MP ( => z, Enable => En, => lk, => t ); 9 Structural description eample () VHL87 USE ieee.std_logic_6.all ; ENTITY priority_resolver IS PORT (r : IN ST_LOGI_VETOR(5 OWNTO ) ; s : IN ST_LOGI_VETOR( OWNTO ) ; clk : IN ST_LOGI; en : IN ST_LOGI; t : OUT ST_LOGI_VETOR(3 OWNTO ) ) ; EN priority_resolver; RHITETURE structural OF priority_resolver IS SIGNL p : ST_LOGI_VETOR (3 OWNTO ) ; SIGNL q : ST_LOGI_VETOR ( OWNTO ) ; SIGNL z : ST_LOGI_VETOR (3 OWNTO ) ; SIGNL ena : ST_LOGI ; Structural description eample (2) VHL87 OMPONENT mu2to PORT (,, s : IN ST_LOGI ; : OUT ST_LOGI ) ; EN OMPONENT ; OMPONENT priority PORT ( : IN ST_LOGI_VETOR(3 OWNTO ) ; y : OUT ST_LOGI_VETOR( OWNTO ) ; z : OUT ST_LOGI ) ; EN OMPONENT ; OMPONENT dec2to PORT ( : IN ST_LOGI_VETOR( OWNTO ) ; En : IN ST_LOGI ; y : OUT ST_LOGI_VETOR(3 OWNTO ) ) ; EN OMPONENT ; 2 Structural description eample (3) VHL87 OMPONENT regn GENERI ( N : INTEGER := 8 ) ; PORT ( : IN ST_LOGI_VETOR(N OWNTO ) ; Enable, : IN ST_LOGI ; : OUT ST_LOGI_VETOR(N OWNTO ) ) ; EN OMPONENT ; Structural description eample () VHL87 u: mu2to PORT MP ( => r(), => r(), s => s(), => p()); p() <= r(2); p(2) <= r(3); u2: mu2to PORT MP ( => r(), => r(5), s => s(), => p(3)); u3: priority PORT MP ( => p, y => q, z => ena); u: dec2to PORT MP ( => q, En => ena, y => z); 3 9

20 Structural description eample (5) VHL87 u5: regne GENERI MP (N => ) EN structural; PORT MP ( => z, Enable => En, => lk, => t ); onstants 5 EE 8 FPG and SI esign ith VHL 6 onstants Synta: ONSTNT name : type := value; Eamples: ONSTNT init_value : ST_LOGI_VETOR(3 donto ) := ""; ONSTNT N_EXT : ST_LOGI_VETOR(7 donto ) := X"B"; ONSTNT counter_idth : INTEGER := 6; ONSTNT buer_address : INTEGER := 6#FFFE#; ONSTNT clk_period : TIME := 2 ns; ONSTNT strobe_period : TIME := ms; onstants eatures onstants can be declared in a PKGE, RHITETURE, ENTITY When declared in a PKGE, the constant is truly global, or the package can be used in several entities. When declared in an RHITETURE, the constant is local, i.e., it is visible only ithin this architecture. When declared in an ENTITY declaration, the constant can be used in all architectures associated ith this entity. EE 8 FPG and SI esign ith VHL 7 8 Eample o package library ieee; use ieee.std_logic_6.all; package alu_pkg is constant OPOE_NOR : std_logic_vector(2 donto ) := ""; constant OPOE_NN : std_logic_vector(2 donto ) := ""; constant OPOE_XOR : std_logic_vector(2 donto ) := ""; constant OPOE_U : std_logic_vector(2 donto ) := ""; constant OPOE_S : std_logic_vector(2 donto ) := ""; constant OPOE_SSUB : std_logic_vector(2 donto ) := ""; constant OPOE_UMUL : std_logic_vector(2 donto ) := ""; constant OPOE_SMUL : std_logic_vector(2 donto ) := ""; Using objects rom a package library ieee; use ieee.std_logic_6.all; library ork; use ork.alu_pkg.all; entity alu_comb is.. end alu_pkg; 9 2 2

21 VHL escription Styles VHL escription Styles Miing escription Styles Inside o an rchitecture datalo oncurrent statements synthesizable structural behavioral omponents and Sequential statements interconnects Registers Shit registers ounters State machines EE 8 FPG and SI esign ith VHL 2 22 Mied Style Modeling architecture RHITETURE_NME o ENTITY_NME is Here you can declare signals, constants, unctions, procedures omponent declarations begin oncurrent statements: oncurrent simple signal assignment onditional signal assignment Selected signal assignment Generate statement omponent instantiation statement Process statement inside process you can use only sequential statements end RHITETURE_NME; oncurrent Statements PRNG Eample () library IEEE; use IEEE.ST_LOGI_6.all; use ork.prng_pkg.all; ENTITY PRNG IS PORT( oe : in std_logic_vector( donto ); Load_oe : in std_logic; Seed : in std_logic_vector( donto ); Init_Run : in std_logic; lk : in std_logic; urrent_state : out std_logic_vector( donto )); EN PRNG; RHITETURE mied OF PRNG is signal nds : std_logic_vector( donto ); signal Sin : std_logic; signal oe_ : std_logic_vector( donto ); signal Shit5_ : std_logic_vector( donto ); 23 2 PRNG Eample (2) ata Flo Sin <= nds() XOR nds() XOR nds(2) XOR nds(3) XOR nds(); urrent_state <= Shit5_; nds <= oe_ N Shit5_; Behavioral oe_reg: PROESS(lk) IF rising_edge(lk) THEN IF Load_oe = '' THEN oe_ <= oe; EN IF; EN IF; EN PROESS; Structural Shit5_Reg : ENTITY ork.shit5(behavioral) PORT MP ( => Seed, Load => Init_Run, Sin => Sin, => lk, => Shit5_); EN mied; Sequential Logic Synthesis or Beginners 25 EE 8 FPG and SI esign ith VHL 26 2

22 For Beginners Use processes ith very simple structure only to describe registers shit registers counters state machines. Use eamples discussed in class as a template. reate generic entities or registers, shit registers, and counters, and instantiate the corresponding components in a higher level circuit using GENERI MP PORT MP. Supplement sequential components ith combinational logic described using concurrent statements. Sequential Logic Synthesis or Intermediates 27 EE 8 FPG and SI esign ith VHL 28 For Intermmediates For Intermmediates (2). Use Processes ith IF and SE statements only. o not use LOOPS or VRIBLES. 2. Sensitivity list o the PROESS should include only signals that can by themsleves change the outputs o the sequential circuit (typically, clock and asynchronous set or reset) 3. o not use PROESSes ithout sensitivity list (they can be synthesizable, but make simulation ineicient) Given a single signal, the assignments to this signal should only be made ithin a single process block in order to avoid possible conlicts in assigning values to this signal. Process : PROESS (a, b) y <= a N b; EN PROESS; Process 2: PROESS (a, b) y <= a OR b; EN PROESS;