PU : General View. From FEB S2P DSP FIFO SLINK

Transcription

1 1. FIFO simulation In this document you will find a simple and elegant solution concerning the data transfer between the DSP and the (Output Controller). This solution is a response to the permanent question specific to the DSP activity : how to minimize the software overhead. Prerequisites PU : General View From FEB S2P DSP FIFO From FEB S2P DSP FIFO SLINK To ROB This figure shows a general diagram of the PU (Processing Unit). The incoming events sent by the FEB are reformatted in a convenient way to optimize the physics processing done by the DSP. In this context, the FIFO plays the role of an external buffer for the. This is necessary because the has to combine the events coming from two different DSPs in a specific way according to ROB event format requirements. Obviously, the two-combined events must have the same signature (e.g. the same: BCID bunch crossing ID, EvID event ID and Ttype trigger type). Strong requirements The maximum incoming event frequency is 100 KHz. After processing, the event size is roughly halved. Because an processes two DSPs, it must keep the input bandwidth. FIFO simulation DSP 1

2 The DSP should be able to manage situations when the event size is larger than the external FIFO size. In this case, several fragments should be sent sequentially when the FIFO has enough available space. When an event is sent out on the SLINK by the, it should be seen as a contiguous data bloc. Consequently, when the begins to send an event, it cannot stop until the end of the event is detected. It is the role of the DSP / FIFO data exchange protocol to keep this data flow continuous. Useful features FIFO size MAX event size Typical event size Event processing time FIFO signals 8 Kbytes 25 K 1 K max. 10 µs FF (FIFO Full), AF (FIFO Almost Full), HF (FIFO Half Full), AE (FIFO Almost Empty) and FE (FIFO Empty) FIFO controls RdClk (Read Clock), RdEn (Read Enable) Proposed solution To keep track of the FIFO status we propose to simulate it inside the DSP. For that, the DSP must be able to manage two similar situations: 1) two or several small events are ready to be transferred to the FIFO or 2) events of big size (i.e. larger than the external FIFO size) should be fragmented to fit successively inside the output FIFO. A convenient way to do that is to use an internal accumulator that keeps track of the current available space in the FIFO. Roughly, when an event fragment is sent by the DSP its size is subtracted from the accumulator; at the initiative of the external electronic (e.g. or Output FPGA), a corresponding value will be added to the accumulator (later we will see how it will happen). FIFO simulation DSP 2

3 Solution 1a Solution 1a DSP FIFO Counter Output FPGA Counter Overflow Fragment Sent FIFO - Fragment Size FIFO + Counter Size This solution is a quantitative one because the DSP, at each moment, knows exactly the status of the FIFO. The above figure shows the responsibilities of each element to realize an optimized data flow between the DSP and the. For sake of simplification, this figure doesn t contain some hardware elements. Hardware requirements An internal counter will be provided inside the. Each time an element is read out from the DSP, the counter is incremented; when this counter touches a predefined value (e.g. CLk_TICK = 1K) it will be restarted and a Counter Overflow pulse will be generated; this pulse will generate an interrupt on the DSP. Software requirements (see the precedent figure) The CLK_TICK value depends on the FIFO size and the granularity (i.e. the frequency of the interrupts) we want. An internal variable availablefifo (i.e. current available space in the external FIFO) works as an accumulator. At the boot of the system, this value will be initialized to the maximum size of the external FIFO. FIFO simulation DSP 3

4 Software sequence Variables definition and initialization #define CLK_TICK 1024 #define EXTERNAL_FIFO_SIZE 8192 int availablefifo = EXTERNAL_FIFO_SIZE; Sending an event fragment (after the event slicing) : NB The introduced overhead is presented in italics in this code bloc. int crtfragmentsize; if(crtfragmentsize < availablefifo) { availablefifo -= crtfragmentsize; } SendTheFragment(); Associated Routine : ISR () { availablefifo += CLK_TICK; } Remarks The main advantages of this solution are: 1) the knows perfectly when it reads a value from the FIPO then the Counter incrementation is easy to realize; 2) the DSP code will be simplified a lot (e.g. no further overhead related to the DMA management will be necessary). The drawback of this solution : two extra lines will be needed on the connector between the PU and the (they are already foreseen : spare 1 & 2) FIFO simulation DSP 4

5 Solution 1b Solution 1b RdEN DSP FIFO RdCLK Output FPGA Counter Fragment Sent FIFO - Fragment Size FIFO + Counter Size This solution is a variation of the precedent one. Remarks The main advantage of this solution : the new needed hardware will be implemented in the Output FPGA of the PU.. The drawback of this solution : two signals (RdCLK and RdEN) should be used to implement the Counter Clock. Improvement It is obvious that a residual value will remain in the counter until the next Counter Overflow signal. This effect can be reduced if the FE (FIFO Empty) signal (not shown in the above figure) will be used to reset the counter and to generate another interrupt on the DSP. This interrupt doesn t represent a reel software overhead for the DSP because it is in idle mode when the FIFO is empty. FIFO simulation DSP 5

6 Solution 2 Solution 2 DSP FIFO 1 2 Output FPGA AF AE Fragment Sent FIFO - Fragment Size FIFO + Counter Size This solution is a qualitative one because the DSP knows only when the FIFO transgresses two predefined borders : FIFO Almost Empty and FIFO almost Full. Those two signals play the role of an hysterezis. If the hysterezis width is too big, the FIFO Almost Empty signal can be replaced by FIFO Half Full signal. FIFO simulation DSP 6