CHAPTER 5 DECODER BOARD SOFTWARE

Transcription

1 CHAPTER 5 DECODER BOARD SOFTWARE This chapter describes the Grayson Electronics boot program that came with the prototype decoder board, and the application program that was integrated with it. Before the programs are discussed, the DS80C320 architecture is described first. 5.1 DS80C320 Architecture The DS80C320 has three basic memory address spaces: 64 KB Program Memory, 64 KB External Data Memory, and 384 bytes Internal Data Memory. This differs from the Motorola 68HC11 microcontroller which does not distinguish between program memory space and data memory space. Figure 5.1 shows the DS80C320 memory map. The program memory space has an internal and an external memory portion. If the EA pin on the microcontroller is held high, the DS80C320 executes out of internal program memory unless the address exceeds 1FFFh. Locations FFFFh are fetched from external program memory. If the EA pin is held low, the DS80C320 fetches all instructions from external program memory. The EA pin is held low on the decoder board. The data memory space also has an internal and an external memory portion. The internal data memory is divided into three physically separate and distinct blocks: the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128 byte Special Function Register (SFR) area which contains the register locations for the accumulator, stack pointer, data pointer, port registers, timer control registers, interrupt control registers, serial port control registers, and others. As shown in Figure 5.1, upper RAM and the SFRs share the same address locations. These two areas are accessed through different addressing modes. Specifically, indirect addressing is used to access upper RAM, whereas direct addressing is used to access the SFRs. Both addressing modes can be used to access the lower RAM. The decoder board application software uses internal data RAM for all user defined variables. As mentioned before, the decoder board application program uses the entire external data memory as a buffer for IVDS messages. The 16-bit data pointer (DPTR) in conjunction with the MOV instruction are used to access the external data memory. 31

2 FFFF FFFF ETERAL ETERAL FFF OVERLAPPED SPACE ITERAL ETERAL FF 80 UPPER RAM SPECIAL FUCTIO REGISTERS F 00 LOWER RAM 0000 PROGRAM MEMOR ITERAL ETERAL DATA MEMOR DATA MEMOR Figure 5.1 DS80C320 Memory Map Also, unlike the Motorola 68HC11, the DS80C320 has an integrated bit processor. It has its own instruction set, accumulator (the carry flag), and bit-addressable RAM and I/O. The bit instructions allow a bit to be set, cleared, complemented, jump-if-set, jump-if-notset, and others. Addressable bits may be logically ADed and ORed with the contents of the carry flag, with the result returned to the carry register. Many SFR registers are bitaddressable, and internal RAM locations 20-2Fh are bit-addressable. The decoder board application program uses the bit-addressable RAM locations for user defined state bits. A complete description of the DS80C320 architecture features is provided in the Intel Microcontroller Handbook.[6] 32

3 5.2 Boot Program Grayson Electronics provided the decoder board boot program already burned into the PROM, its source code, and the assembler software. Per agreement with Grayson Electronics, no other software assistance would be provided to Virginia Tech. Before the decoder board application software was developed, the boot program was first analyzed Main Routine of Boot Program The boot program is the microcontroller kernel software. Upon power-up, the boot program initializes the microcontroller, sends diagnostic information to the WMI, and then waits for commands in the form of interrupts. The main routine of the boot program first initializes the SFRs so that the decoder board can serially communicate with the WMI. Timer 1 clocks the serial port at 57.6 KBaud. Also, the serial port is set for 10-bit asynchronous communications: one start bit, eight data bits, and one stop bit. ext, the stack pointer, user variables, and state bits are initialized. The serial interrupts are enabled last. The boot program uses portions of internal data RAM to establish memory for the stack, a serial input buffer, and a serial output buffer. Each serial buffer is implemented as a firstin, first-out (FIFO) cyclic buffer, each having an in-pointer and an out-pointer. Each time data is input to a buffer, the in-pointer is incremented, and each time data is output from a buffer, the out-pointer is incremented. Consequently, when a pointer is at the end of a buffer, the pointer is reset to the beginning of the buffer, and when the in-pointer equals the out-pointer, the buffer is empty. At power-up, the main routine initializes the pointers to the beginning of their buffers. After initialization, the main routine sends diagnostic information to the WMI to indicate its operational status. If the diagnostic information is incorrect, the WMI will ignore any further data from that decoder board. The diagnostic information contains two diagnostic byte codes, the board type, the ROM version, the RAM version, a two-byte ROM checksum, and a two-byte RAM checksum. The diagnostic byte codes, which are 7021h, tell the WMI that diagnostic information about a decoder board will follow. The board type is set to 11h which indicates an IVDS decoder board, and the ROM version is set to decimal. Though RAM does not contain program code, RAM version is set to the ROM version. The ROM and RAM checksums are self-explanatory. Lastly, the main routine begins an infinite loop waiting for a serial interrupt to cause the microcontroller to process one of three WMI commands: Restart ROM code, Write-to- RAM, and Run RAM code. The Restart ROM command simply restarts the ROM as if a power-up occurred. The Write-to-RAM command stores a byte to RAM. The Run RAM command causes the microcontroller to fetch instructions from RAM. 33

4 5.2.2 Condensed Address Packet Protocol The boot program has a serial interrupt service routine (ISR) to transmit data, and a serial ISR to receive data. Before a discussing these ISRs, the protocol that Grayson Electronics has implemented is described first. Communication between the WMI and decoder board uses the Condensed Address Packet Protocol (CAPP). CAPP uses control codes to indicate the start and end of packet transmission, and if a data byte happens to be a control code, then the ULL/ESC control code must be sent first, so that the next data byte will be taken literal. Table 5.1 shows the control codes. Table 5.1 Condensed Address Packet Protocol Byte $00 CAPP ame ULL Description Used as ESC. Take next byte literal. $01 O ICB HC05 to decoder C320: O = Software flow control off. $02 ST Start of packet transmission. $03 OFF ICB HC05 to decoder C320: OFF = Software flow control on. $04 $05 EOT OT USED End of packet transmission. The microcontroller will always end a start of transmission with at least one EOT (more than one EOT may follow). Data transmission must be completed to be executed. A packet has the following format: ST [ data bytes + ULL codes if needed] EOT. Also, when the microcontroller sends a packet, the ICB HC05 automatically overwrites the lower nibble of the first data byte with the decoder board number. For example, if the first data byte from decoder board 2 is 50h, then this data byte becomes 52h. Current ICB restrictions limit packet size to 32 bytes maximum, including the control codes. If every data byte is assumed to be control code and thus must be preceded by a ULL, then the largest safe packet size is reduced to 15 bytes ([32 - ST - EOT]/2). The software flow control between the microcontroller and HC05 is unidirectional. The HC05 can start and stop data transmission from the microcontroller, but the 34

5 microcontroller cannot stop the HC05 from sending data. For example, when the HC05 sends the OFF command, the microcontroller stops data transmission until it receives the O command Serial Interrupt Service Routines and Subroutines The function of the Receive ISR is to process data bytes sent by the WMI via the serial port. Thus, bytes sent to the microcontroller are characterized as receive bytes. As when the microcontroller sends data bytes to the WMI, the WMI must also send data bytes to the microcontroller in a packet that begins with an ST and ends with an EOT. There are four commands that the WMI can send to the microcontroller. The WMI can tell the microcontroller to start or stop data transmission. It can tell the microcontroller to store bytes to RAM. It can tell the microcontroller to execute instructions stored in RAM. And lastly, it can tell the microcontroller to execute instructions stored in ROM. The Receive ISR uses a state machine approach to process bytes received from the WMI. There are three states: IDLE, RU0, and RU1. In the IDLE state, the state machine is simply waiting for an ST byte. When the ST byte is received, the state machine enters the RU0 state. In the RU0 state, the state machine either stores the next byte into the Receive buffer or takes appropriate action based on the control code. If an ESC byte is received while in the RU0 state, the state machine enters the RU1 state. In the RU1 state, the state machine stores the next byte received. Also, the Receive ISR toggles LED 1 when a byte is received. Figure 5.2 shows the Receive ISR flow chart. Using internal data memory location 20h, bits 0-1 are used to represent the Idle and Run states, respectively. Bit 0 is set to put the state machine in the IDLE state. Once not in the IDLE state, bit 1 is cleared to put it in the RU0 state, or is set to put it in the RU1 state. The boot program uses three subroutines and the Transmit ISR to transmit a packet. First, the ST byte is put into the Transmit buffer using the send ST subroutine. Then, the data bytes are put into the buffer using the send serial subroutine for each data byte. Lastly, the EOT byte is put into the buffer using the send end subroutine. The Transmit ISR then sends the packet. Figures show flow charts for these routines. Using internal data memory location 20h, bits 2-3 are used to represent the Transmit and Flow Control states, respectively. If the microcontroller is transmitting a byte, then bit 2 is set to indicate that the Transmit state is active. Also, if the HC05 is accepting data, bit 3 is set to indicate that the microcontroller has permission to transmit data. Each time a subroutine puts a byte into the Transmit buffer, the Transmit state is set to active unless it is already active. Once the buffer is empty, then the Transmit ISR sets the Transmit state to non-active. Also, the Transmit ISR checks the flow control bit, which the Receive ISR sets or clears as appropriate. 35

6 IDLE RU1 Byte = ST? Set state = RU0 EIT Store byte EIT EIT RU0 Byte = ESC? Set state = RU1 EIT Byte = EOT? Packet complete Set state = IDLE EIT Byte = O/OFF? Operate as needed EIT Store byte EIT Figure 5.2 Flow Chart for Receive ISR in Decoder Board Boot Program 36

7 START Put ST/EOT byte into serial buffer Increment serial in-pointer In-pointer at end of serial buffer? Put in-pointer to start of serial buffer Transmission in progress? RETUR Set transmit state to active Force serial interrupt RETUR Figure 5.3 Flow Chart for Send ST/EOT Subroutine in Decoder Board Boot Program 37

8 START Data byte = control code? Put ESC byte into serial buffer Put data byte into serial buffer Increment serial in-pointer Increment serial in-pointer In-pointer at end of serial buffer? Put in-pointer to start of serial buffer In-pointer at end of serial buffer? Put in-pointer to start of serial buffer Transmission in progress? RETUR Set transmit state to active Force serial interrupt RETUR Figure 5.4 Flow Chart for Send Serial Subroutine in Decoder Board Boot Program 38

9 START Out-pointer = in-pointer? Serial Buffer Empty FLOW = OFF? RETI Set transmit state to non-active RETI Send data byte out Increment serial out-pointer Out-pointer at end of serial buffer? Put out-pointer to start of serial buffer RETI Figure 5.5 Flow Chart for Transmit ISR in Decoder Board Boot Program 39

10 5.3 Application Program With modifications and additions to the boot program, Virginia Tech developed the application program to initialize the microcontroller, the synthesizer, and the spread spectrum decoder so that the decoder board can receive IF messages from the receiver, packetize them, and then send them to the WMI. Figure 5.6 shows the flow chart for the application program main routine. After initialization, the microcontroller waits for an interrupt while continuously resetting/restarting the Watchdog timer. Initialize Microcontroller Enable Serial Interrupts Enable Timer 0 Interrupt Initialize/Enable Synthesizer (Call init_phiint) Send Diagnostics Reset/Start Watchdog Timer Initialize/Enable Spread Spectrum Decoder (Call init_stel) Initialize/Enable Watchdog Timer Wait for interrupt Initialize Interrupts Flush Serial Buffer Figure 5.6 Flow Chart for Main Routine in Decoder Board Application Program Interactive Video Data Service Message Format Before discussing the application program, the IVDS message format is discussed. An IVDS message has a fixed length of 184 data bits or 23 bytes. The first three bytes are Lock bytes, which allow time for the receiver s Automatic Gain Control (AGC) to stabilize. This stabilization time is not constant and causes message bits to be lost. Therefore, the Lock bytes protect message integrity and provide a method to find the byte 40

11 boundaries. The fourth byte is the Header byte which marks the beginning of a message. The next 17 bytes are the message data bytes, and the last two bytes are Cyclic Redundancy Check (CRC) bytes. The CRC bytes provide error detection to prevent corrupted messages from being accepted as valid messages. The CRC calculation is only computed for the 17 data bytes and so a loss of Lock bits will not prevent a valid message from reaching the Host subsystem. Figure 5.7 shows the hexadecimal values of these bytes. A detailed description of the message format is provided in the description and specification manual.[3] 0F 0F 0F data bytes CRC CRC Figure 5.7 Interactive Video Data Service Message Format Timer Initialization The application program initializes Timer 0 as an 8-bit counter with automatic reload. In the counter mode, the count register is incremented in response to 1-to-0 transitions at its corresponding external input pin T0. Overflow from the TL0 register not only sets the TF0 flag, but also reloads TL0 with the contents of TH0, which is preset by software. The reload leaves TH0 unchanged. The overflow condition occurs when the count register changes from FFh to 00h. Since the Timer 0 interrupt is enabled, an interrupt is generated when the TF0 flag is set. TH0 and TL0 are initialized to FFh. The Timer 0 counter is used to count the number of clock pulses received from the SSD. Once a specified number of clock pulses is counted, the Timer 0 ISR is executed. The application program initializes Timer 2 as a 16-bit timer. In the timer mode, the timer register is incremented once per machine cycle. Overflow from the TH2 and TL2 registers sets the TF2 flag which must be cleared by software. The overflow condition occurs when the register contents change from FFFFh to 0000h. Since the Timer 2 interrupt is enabled, an interrupt is generated when the TF2 flag is set. TH2 and TL2 are initialized to FFh and DBh, respectively. Timer 2 is used to determine if a timeout has occurred between the SSD and microcontroller. If the timeout period expires, then the Timer 2 ISR is executed Variable Initialization After the timers are initialized, the user variables and state bits are initialized. Using internal data RAM location 20h, bits 4-7 contain the lock_byte, header_byte, last_five, and buffer_full state bits, respectively. These state bits are initially cleared. Internal data RAM locations 21h and 26-2Ch contain the user variables byte_count, tx_outptr, tx_outptrhi, tx_inptr, tx_inptrhi, buffer_high, buffer_low, and rx_ptr, respectively. Internal data RAM locations B0 - DFh are reserved for the Receive serial buffer, which is 54 bytes long. Since the Transmit serial buffer is the 41

12 external data RAM (32 KB), two memory locations are required to store the in-pointer and out-pointer values. Consequently, tx_outptr, tx_outptrhi, tx_inptr, and tx_inptrhi are initialized to 0. Buffer_high and buffer_low are also initialized to 0. Byte_count gets initialized to 15h, and rx_ptr to B0h. Except for initializing the SSD and synthesizer, the remainder of the main routine is straightforward. The interrupt priority is initialized so that the Serial Transmit/Receive Interrupt has the highest priority so that if the WMI sends the command for the microcontroller to stop transmitting data, the microcontroller will respond promptly. The Timer 0 Interrupt is enabled last so that the decoder board will be completely initialized before responding to incoming messages. The main routine then waits for interrupts while continuously resetting/restarting the Watchdog timer. The Watchdog timer is set to its lowest timeout value of milliseconds. If a program fault occurs, the Watchdog timer will timeout causing the microcontroller to perform a hardware reset Synthesizer Initialization The subroutine, init_phiint, initializes and enables the synthesizer in the receiver. The synthesizer is configured so that the receiver is tuned to one of four carrier frequencies: 906 MHz, 912 MHz, 918 MHz, or 924 MHz. To program the synthesizer, data is entered with the MSB first. The leading bits are the data field while the last four bits are the address field. As shown in Figure 4.2, the signal lines from the microcontroller to the synthesizer are inverted. Therefore, software must complement the data bits before sending them to the synthesizer. Figure 5.8 shows the five registers with the appropriate bit values to program the synthesizer to 912 MHz. The OLP and OLA bits are set to select both principal and auxiliary in-lock detect output on the S#LOCK signal line. Software checks the synthesizer output to determine when the synthesizer is locked to the desired frequency. The CR1 and CR0 bits are set to select the appropriate fast and normal charge pumps current ratio. The PO and AO bits are set to power-up the principal and auxiliary synthesizers. A complete description on the register settings is provided in the product specification.[10] The divider coefficients values are based upon the receiver design and the synthesizer design. Block diagrams for the receiver and principal/auxiliary synthesizers are shown in Figures 5.9 and 5.10, respectively. The common reference frequency input to both synthesizers is 14.4 MHz. The RF group specified that f VCO should be tunable in 10 KHz steps. To achieve 10 KHz steps, f must equal 10 KHz (0.01 MHz). REF 42

13 FIRST I LAST I COTROL REGISTER ADDRESS OLP OLA CR1 CR0 PO AO PRICIPAL MAI DIVIDER COEFFICIET 1 1 (Frcv + 70)/.01: Value For Frcv=912 MHz Shown Below (98200 Decimal) ADDRESS PRICIPAL REFERECE DIVIDER COEFFICIET (1440 Decimal) ADDRESS AUILIAR MAI DIVIDER COEFFICIET (9000 Decimal) ADDRESS AUILIAR REFERECE DIVIDER COEFFICIET (1440 Decimal) ADDRESS D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1 A0 D = Data Bit = Don t Care A = Address Bit Figure 5.8 Synthesizer Control and Data Registers 43

14 912 MHz 70 MHz 20 MHz Output 982 MHz 90 MHz Principal Synthesizer Auxiliary Synthesizer Figure 5.9 Receiver Block Diagram Reference Divider PD Main Divider CLK M f VCO f REF f(s) Equation 5.1: f REF = CLK M Equation 5.2: f VCO = f = (CLK) = REF CLK M M Figure 5.10 Principal/Auxiliary Synthesizer Block Diagram 44

15 Using equation 5.1, M = 14.4 MHz / 10 KHz = 1440 decimal for the principal and auxiliary synthesizers. Using equation 5.2 for the principal synthesizer, = (f VCO + 70 MHz) / 0.01 MHz, and for the auxiliary synthesizer, = (f VCO + 20 MHz) / 0.01 MHz. Figure 5.11 shows the required calculations for the main divider coefficients (decimal) to tune the receiver to a desired carrier frequency. The auxiliary main divider coefficient will remain fixed at 9000 decimal while the principal main divider coefficient will have to be adjusted to achieve the desired carrier frequency. Principal Synthesizer 906 MHz: = (906 MHz + 70 MHz) / 0.01 MHz = MHz: = (912 MHz + 70 MHz) / 0.01 MHz = MHz: = (918 MHz + 70 MHz) / 0.01 MHz = MHz: = (924 MHz + 70 MHz) / 0.01 MHz = Auxiliary Synthesizer 70 MHz: = (70 MHz + 20 MHz) / 0.01 MHz = 9000 Figure 5.11 Main Divider Coefficient Calculations for Synthesizer Figure 5.12 shows the flow chart for programming the synthesizer registers. The registers are programmed in this order: Control Register, Auxiliary Reference Divider Coefficient (ARDC), Auxiliary Main Divider Coefficient (AMDC), Principal Reference Divider Coefficient (PRDC), and Principal Main Divider Coefficient (PMDC). The same basic steps are used to program each register. The first bit (D16) is sent to the synthesizer using the sen_syn_one subroutine. ext, eight bits (D15 - D8) are sent using the sen_syn subroutine with the MSB sent first. Then, another eight bits (D7 - D0) are sent. Lastly, four bits (A3 - A0) are sent using the sen_syn_four subroutine. When programming the Control Register, the AMDC register, and the ARDC register, the data to be sent to the synthesizer is put into the accumulator register before calling the appropriate synthesizer subroutine. Since the first bit of these registers is a Don t Care bit, software just calls the sen_syn_one subroutine to maintain the bit boundaries. For the sen_syn_four subroutine, only the upper nibble of the accumulator is sent. 45

16 init_phiint Shift A3-A0 into Control Register (Call sen_syn_four) Shift D7-D0 into ARDC Register (Call sen_syn) Drive CLK low Disable synthesizer Shift A3-A0 into Control Register (Call sen_syn_four) Enable synthesizer Delay Disable synthesizer Shift D16 into Control Register (Call sen_syn_one) Enable synthesizer Delay Shift D15-D8 into Control Register (Call sen_syn) Shift D16 into ARDC Register (Call sen_syn_one) Enable synthesizer Shift D7-D0 into Control Register (Call sen_syn) Shift D15-D8 into ARDC Register (Call sen_syn) Shift D16 into AMDC Register (Call sen_syn_one) A Figure 5.12 Flow Chart for Synthesizer Initialization Subroutine (1 of 2) 46

17 A Shift D15-D8 into AMDC Register (Call sen_syn) Disable synthesizer Set principal main divider coefficient (Call sen_syn_x) Shift D7-D0 into AMDC Register (Call sen_syn) Delay Synthesizers locked? Shift A3-A0 into AMDC Register Set principal reference divider coefficient RETUR (Call sen_syn_four) (Call sen_syn_x) Figure 5.12 Flow Chart for Synthesizer Initialization Subroutine (2 of 2) 47

18 sen_syn_one sen_syn_four sen_syn Complement data bit Shift bit into carry register Shift bit into carry register Send data bit to synthesizer Complement data bit Complement data bit Drive CLK high Send data bit to synthesizer Send data bit to synthesizer Drive CLK low Drive CLK high Drive CLK high RETUR Drive CLK low Drive CLK low 4 bits shifted? 8 bits shifted? RETUR RETUR Figure 5.13 Subroutine Flow Charts for Sending Synthesizer One/Four/Eight Data Bits 48

19 sen_syn_x Drive CLK low Enable synthesizer Shift D16 into PRDC Register (Call sen_syn_one) Set PRDC? Shift D16 into PMDC Register (Call sen_syn_one) Shift D15-D8 into PRDC Register (Call sen_syn) Shift D15-D8 into PMDC Register (Call sen_syn) Shift D7-D0 into PRDC Register Shift D7-D0 into PMDC Register Shift A3-A0 into PRDC Register (Call sen_syn_four) Shift A3-A0 into PMDC Register (Call sen_syn_four) Disable synthesizer RETUR Figure 5.14 Subroutine Flow Chart for Setting Principal Main/Reference Divider Coefficient 49

20 When programming the PRDC and PMDC registers, the data to be sent to the synthesizer is put into three user defined registers labeled syn_work, syn_work+1, and syn_work+2, which use internal data RAM locations 2D - 2Fh, respectively. To program the PRDC register, the D15 - D8 and D7 - D0 bits are put into the syn_work and syn_work+1 registers, respectively. Then, 2h is placed into Register 5, indicating that the PRDC register is to be programmed, before calling the sen_syn_x subroutine. To program the PMDC register, the D16 bit is placed into the syn_work register as the LSB, and D15 - D8 and D7 - D0 bits are put into the syn_work+1 and syn_work+2 registers, respectively. Then, 3h is placed into Register 5, indicating that the PMDC register is to be programmed, before calling the sen_syn_x subroutine Spread Spectrum Decoder Initialization The subroutine, init_stel, initializes and enables the SSD. As mentioned before, the SSD control registers are 8-bit registers which conveniently allows software to configure the SSD. The control register values are stored in external ROM, starting at address 7700h. As shown in Figure 5.15, software enables the SSD, reads a byte from ROM, and writes the byte to the SSD. The remaining 86 bytes are then read from ROM and written to the SSD. Once the 87 bytes are written, the umerically Controlled Oscillator (CO) must be reloaded with the frequency control information so that the CO will start. A complete description for controlling the CO is provided in the product specification.[14] Lastly, software disables the SSD as the write peripheral before exiting the subroutine. If the SSD remains enabled after its initialization, then the microcontroller will erroneously write data bytes to the SSD when the data bytes should be written to RAM. In other words, the RAM should always be enabled unless the programmer specifically wants to configure the control registers in the SSD. Since the SSD is a write-only device, there is no direct method for checking the contents of the control registers. However, an oscilloscope can be used to display RSPLPLS to at least determine if the CO has started. If the CO has started, then one is assured that all SSD internal timing signals are being generated. 50