CES 522: Laboratory Manual for Digital Integrated Circuit Design. Jack Ou, Ph.D.

Transcription

1 CES 522: Laboratory Manual for Digital Integrated Circuit Design Jack Ou, Ph.D. September 2011

2 2

3 Contents 1 Getting Started with ICStudio Create a Project Directory Start ICStudio Create a Project Verilog Create a Verilog Block Test a Verilog Block Command Line Mode Basic Steps A Half Adder Example A Sample Verilog Code Creating the Stimulus Monitoring the Response Command Line Operation Assignment MOS Characterization Technology Selection Generate the DC operating point Generate a I DS versus V DS Plot Assignment Transistor Level Design of a Half-Adder CMOS Static Inverter XOR Gate AND Gate Half-Adder Submission Checklist

4 4 CONTENTS 6 Verilog and Transistor Level Simulation 31 7 Layout 43 8 DRC 47 9 Running DRC from the Calibre Menu LVS xrc Post Layout Simulation 59

5 Chapter 1 Getting Started with ICStudio 1.1 Create a Project Directory 1. Log on to machines in Salazaar (a) Username: student 2. Open a terminal (Applications Accessories Terminal) 3. At the prompt, type cd /home/student/ 4. At the prompt, type mkdir YourUserName 5. At the prompt, type cd /home/student/yourusername 6. At the prompt, type mkdir mgc_project 1.2 Start ICStudio 1. At the prompt, type cd /usr/local/mentor/adk3_1 2. At the prompt, type tcsh 3. At the prompt, type pwd (a) You should find yourself in the following directory: /usr/local/mentor/adk3_1 4. At the prompt, type source source_me 5. At the prompt, type icstudio & 5

6 6 CHAPTER 1. GETTING STARTED WITH ICSTUDIO 1.3 Create a Project 1. Start a new project (File New Project) 2. Click Next at the Introduction window 3. Enter the followings at the Name and Location window (Figure 1.1) (a) Project Name: CES522_VLSI (b) New Project Location: /home/student/yourusername (c) Click on Next Figure 1.1: New Project Window 4. Click on Open Library Editor (a) Click on Edit Menu (b) Click on Add MGC Design Kit. Enter /usr/local/mentor/adk3_1 (c) Click on Edit Menu (d) Select Add Standard MGC Libraries (Figure 1.2) (e) Click on OK (f) Click on Next 5. Click on Open Settings Editor under Technology Settings (Figure 1.3)

7 1.3. CREATE A PROJECT 7 Figure 1.2: Library List Editor (a) Under the IC Layout tab, enter the followings under Technology Settings (b) Process: /usr/local/mentor/imported_kit/process/mgc_generic (c) DRC rules files: /usr/loca/mentor/imported_kit/rule_deck/drc (d) LVS rules files: /usr/loca/mentor/imported_kit/rule_deck/lvs (e) SDL rule files: /usr/local/mentor/imported_kit/processed/sdl_process_rules (f) PEX rules files: /usr/loca/mentor/imported_kit/rule_deck/pex (g) Select OK 6. Select Next 7. Select Finish 8. The library should not be populated with references to the design kit and the MGC_IC_LIB. (Figure 1.4)

8 8 CHAPTER 1. GETTING STARTED WITH ICSTUDIO Figure 1.3: Technology Settings Figure 1.4: Project Window

9 Chapter 2 Verilog 2.1 Create a Verilog Block We will create a half adder in IC Studio in this exercise. (Figure 2.1) Figure 2.1: Schematic and Verilog Code of a Half Adder 1. Create add_half.v in a text editor. (Figure ) 2. Start ICStudio. Create a library. Call it veriloglib. (File New Library). 3. Select the newly created libary. Go to File Import Verilog. (Figure 2.2) (a) Select Verilog/Symbol option for Views to be created. (b) View Name: add_half (c) Verilog netlist: browse for add_half.v (d) Language type: verilog (e) Click on Import 4. Use Box as shape. Click on Create Symbol. (Figure 2.3) 9

10 10 CHAPTER 2. VERILOG Figure 2.2: Import verilog file Figure 2.3: Create a Symbol 2.2 Test a Verilog Block 1. Create a new library called veriloglib_tb. 2. Right Click veriloglib_tb. Select New Cell Vew. (a) Cell Name: add_half_tb

11 2.2. TEST A VERILOG BLOCK 11 (b) View Type: Schematic (c) Press Finish 3. Add add_half to the schematic. (Add Instance, Figure 2.4) Figure 2.4: Add a Instance 4. Add portin and portout. (Figure 2.5) Figure 2.5: Add Ports 5. Add wires. (Figure 2.6)

12 12 CHAPTER 2. VERILOG Figure 2.6: Add Wires 6. Rename ports to a,b,sum and c_out. (Select each port, and press q, Figure 2.7) Figure 2.7: Rename Ports 7. Click on Check & Save button 8. Click Simulation (a) Choose New Configuration (b) Choose Digital_Simulation (c) Press OK (Figure 2.8)

13 2.2. TEST A VERILOG BLOCK 13 Figure 2.8: Simulation Configuration 9. Select session. Select Simulator/Viewer option. Click on Advanced Setup and select ns as time units. Unselect Use EZWave waveform viewer. Press OK. (Figure 2.9) 10. Select netlist and run. 11. Select a,b,sum and c_out. Add ports to wave. (Figure 2.10) 12. Force clocks on a and b. Select b, right click, select clock, choose a period of 200 for b and 100 for a. (Figure 2.11) 13. Select run length to 100 ns. Clock on run next to the run length. (Figure 2.12) 14. If you change either the period of a or b, please remember to restart the simulation. (Simulate Run restart)

14 14 CHAPTER 2. VERILOG Figure 2.9: Simulator Viewer Figure 2.10: Add Waves

15 2.2. TEST A VERILOG BLOCK 15 Figure 2.11: Define Clock Figure 2.12: Plot Wave

16 16 CHAPTER 2. VERILOG

17 Chapter 3 Command Line Mode 3.1 Basic Steps 1. Create a library. A library is a location on your file system where ModelSim stores data to be used for simulation. 2. Compile the design. 3. Load the design for simulation 4. Simulate the design 5. Debug the design 3.2 A Half Adder Example A Sample Verilog Code We will demonstrate how to run the verilog without the GUI in the next section using the following test bench for the half adder. module add_half_tb(); wire sum,c_out; reg a,b; add_half M1 (c_out,sum,a,b); initial begin #100 $finish; 17

18 18 CHAPTER 3. COMMAND LINE MODE end initial begin #10 a=0; b=0; #10 b=1; #10 a=1; #10 b=0; end initial begin $monitor($time, "a=%b, b=%b,sum=%b, c_out=%b",a,b,sum,c_out); end Creating the Stimulus The keyword initial declares a single-pass behavior that begins executing when the stimulator is activated at t sim = 0. The time at which the statement in begin...end block executes depends on its order in the list of statements, and on the delay time preceding the statement. The statement excecutes from top to botom. In this example, each line is preceded by a time delay (e.g., 10 simulator time units) that is prescribed with a delay control operator #. Figure 3.1 shows the delay implemented using the delay control operator. Figure 3.1: Delay of a and b. The keyword reg indicates that the variables (signals) a and b are getting their values from execution of procedural statements (i.e. between initial begin $10 a=0; b=0;...end. The type declaration reg ensures that the value of the variable will exist from the moment it is assigned by a procedural statement until execution of a later procedural statement changes

19 3.3. COMMAND LINE OPERATION 19 it. All variables that have type reg are given the value of x when the simulation begins and they hold that value until they are assigned a different value. The cross-hatched waveform fill pattern in Figure 3.1 denotes the value x. In this example, a and b contain states which can be used to test the functionality of the add_half.v Monitoring the Response $monitor is used to monitor specific variables and signals in a simulation. initial begin $monitor($time, "a=%b, b=%b,sum=%b, c_out=%b",a,b,sum,c_out); end 3.3 Command Line Operation 1. Source the source_me file as indicated in the previous chapter. 2. Create a logical library. In the following example, we will create a library named work using the following command: vlib work. 3. By default, ModelSim can find libraries in your current directory, but for it to find libraries located elsewhere, you need to map a logical library name to the pathname of the library. You can do it with a command called vamp. Type the following command at the linux prompt: vmap work./work Please note that./work represents a work directory you have created outside of adk3_1 directory. [calhost sandbox]$ vlib work [r2d2@localhost sandbox]$ vmap work./work Modifying modelsim.ini 4. Move your verilog files to the./work directory. 5. Compile the verilog files using the vlog command. [r2d2@localhost sandbox]$ pwd /home/r2d2/design/mentor/verilog/sandbox [r2d2@localhost sandbox]$ ls modelsim.ini work

20 20 CHAPTER 3. COMMAND LINE MODE sandbox]$ vlog./work/add_half.v QuestaSim vlog 6.4c Compiler Dec Compiling module add_half Top level modules: add_half [r2d2@localhost sandbox]$ vlog./work/add_half_tb.v QuestaSim vlog 6.4c Compiler Dec Compiling module add_half_tb Top level modules: add_half_tb [r2d2@localhost sandbox]$ 6. You can start Modelsim using the vsim command followed by the name of the toplevel modeul. In this instance, add_half_tb.v is the top-level module because it contains add_half.v. If you type vsim add_half_tb, Modelsim will start with the add_half_tb.v loaded. If you don t want to run Modelsim in the GUI mode, then you should type the following command: vsim -c add_half_tb 7. Type run at the prompt to execute the entire script. Notice that the $monitor$ command outputs the values of a, b, sum and c_out at critical time instants. Top level modules: add_half_tb [r2d2@localhost sandbox]$ vsim add_half_tb Reading /home/r2d2/mentor/ams_2008_2a/mgc_ams_home/questasim/v6.4c/tcl/vsim/ [r2d2@localhost sandbox]$ vsim -c add_half_tb Reading /home/r2d2/mentor/ams_2008_2a/mgc_ams_home/questasim/v6.4c/tcl/vsim/ # 6.4c # vsim -c add_half_tb # // QuestaSim 6.4c Dec Linux el5 # // # // Copyright Mentor Graphics Corporation # // All Rights Reserved. # //

21 3.4. ASSIGNMENT 21 # // THIS WORK CONTAINS TRADE SECRET AND # // PROPRIETARY INFORMATION WHICH IS THE PROPERTY # // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS # // AND IS SUBJECT TO LICENSE TERMS. # // # Loading work.add_half_tb # Loading work.add_half VSIM 1> run # 0a=x, b=x,sum=x, c_out=x # 10a=0, b=0,sum=0, c_out=0 # 20a=0, b=1,sum=1, c_out=0 # 30a=1, b=1,sum=0, c_out=1 # 40a=1, b=0,sum=1, c_out=0 # ** Note: $finish :./work/add_half_tb.v(8) # Time: 100 fs Iteration: 0 Instance: :add_half_tb [r2d2@localhost sandbox]$ 3.4 Assignment 1. Write the verilog code for a full adder. (Name the file add_full.v.) 2. Generate a verilog test bench for the full adder. (Name it add_full_tb.v) 3. Run the add_full_tb.v in the command mode. Submit a print of outputs and inputs at different time instants.

22 22 CHAPTER 3. COMMAND LINE MODE

23 Chapter 4 MOS Characterization 4.1 Technology Selection Use the 0.18 µm CMOS from TSMC in the following exercise. 1. cd /usr/local/mentor/adk3_1 2. cp source_me source_me.tsmc018 (If you do not have the linux privelege to edit source_me, please copy source_me to a directory where you have write and edit permission) 3. emacs source_me.tsmc018 & 4. Change the value of ADK_TECH from ami05 to tsmc Save, close and exit. 6. tcsh 7. source source_me.tsmc adk_daic & 9. The following lines should appear: [r2d2@localhost adk3_1]$ adk_daic & [1] [r2d2@localhost adk3_1]$ Technology is currently set to TSMC 0.18u // Design Architect-IC v2008.2_6.1 (2008.2e) Wed Oct 28 18:28:14 PDT 2009 // EDDM-IC v2008.2_6.1 (2008.2e) Wed Oct 28 18:27:43 PDT

24 24 CHAPTER 4. MOS CHARACTERIZATION // Core Libraries v2008.2_6.1 Wed Oct 28 18:45:19 PDT 2009 // // Copyright Mentor Graphics Corporation 1982 // // All Rights Reserved. // // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR // ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. // // Mentor Graphics software executing under x86 Linux. 4.2 Generate the DC operating point 1. Open a linux terminal. Create a tsmc018 under /home/student/yourusername. mkdir tsmc Click Open Schematic in the session_pallete. Enter /home/student/tsmc018/lab1/ in the Component field, and select OK. 3. Select ADK IC Library from the session_pallete to the right. 4. Select nmos under Transistors. 5. Select the transistor, press q to edit object properties. 6. Change the length to 0.18 and the width to Add Port Bi to each terminal of the transistor. (Figure 4.1) 8. Click on Simulation in the session_pallete to the right. 9. CLick on Lib/Temp/Inc under Setup in the session_pallete. 10. Select Include Files. 11. Select tsmc018.mod under /adk3_1/technology/ic/models 12. Open a terminal and use a text editor such as emacs to browse tsmc018.mod. 13. Close tsmc018.mod when you are done. 14. Select a net attached to a pin (e.g. the net attached to the source termina). Select Force Manager in the session_pallete.

25 4.2. GENERATE THE DC OPERATING POINT 25 Figure 4.1: An NMOS transistor 15. Select a pin (e.g. S), click on the add button under General Setup, select Independent, specify a DC value for the source terminal (e.g. 0 ). Add it to the list on the top. Repeat this step to set V G to 0.9 V, V D to 1.8 V, V B to 0 V and V S to 0V. (Figure 4.2) Figure 4.2: Apply forces to terminals

26 26 CHAPTER 4. MOS CHARACTERIZATION 16. Click on Analysis under session_pallete. Select DC and DCOP to generate DC conditions of the NMOS. 17. Press Shift + F9 in the schematic window, a window with the Choose Small Signal Param should pop up. Click on OK. 18. Read the Small Signal Parameter Report, and sumbit the following parameters: (a) VTH (Please ignore the negative sign) (b) Region (c) V G (d) V S (e) V D (f) V B 19. Change V B to 0.3 V and observe the change in the threshold voltage. 20. Change V D to 0.2 V and V S to 0.0 V. What is the operational region of the transistor? 4.3 Generate a I DS versus V DS Plot We will sweep VDS next to generate a I DS vs. V GS plot. 1. Click on Analysis in the session_pallete. Click on Setup next to DC. 2. Select Source. Select VOURCE_D from the pull down menu. Set the Start voltage to 0, stop voltage to 1.8V, and step to 0.05 V. (Figure 4.3) 3. Select Forces Manager Edit Waveforms. 4. Select Probe All currents and Probe All Voltages. 5. Click on Session simulator/viewer. Select Enalbe Marching waveforms with EZwave. 6. Click Run ELDO.

27 4.3. GENERATE A I DS VERSUS V DS PLOT 27 Figure 4.3: Sweep V DS Figure 4.4: Probe currents and voltages 7. Select the device by selecting first the data base, then DC. Click on I(D) to generate I DS versus V GS plot. Use the export function to

28 28 CHAPTER 4. MOS CHARACTERIZATION Figure 4.5: Current versus voltage plot export the waveform to a jpeg file. 8. Follow the same procedure to generate a I DS vs. V GS plot. (Please set V DS to 1.8 V) 4.4 Assignment 1. Submit answers to questions in the DC Operating Point Section. 2. Submit I DS vs. V GS plot. 3. Submit I DS vs. V DS plot. 4. Use the I DS vs. V GS plot to determine n in the threshold region. (See page 69 in the textbook)

29 Chapter 5 Transistor Level Design of a Half-Adder 5.1 CMOS Static Inverter 1. Design a CMOS inverter. Assume the following characteristics: (a) 50 ps propagation delay. (b) a load capacitance of 50 ff. (c) Use minimum length (0.2 µm). (d) Meet the propagation delay requirement by using the smallest W/L ratio. (e) Generate a symbol for the CMOS inverter so that it can be reused. (hint: Miscellaneous Generate Symbol. You can modify the shape of the symbol.) 5.2 XOR Gate 1. Design an XOR gate by resizing the W/L ratio of the inverter. You can reuse the inverter design in the previous section. 2. Generate a symbol for the XOR Gate. 5.3 AND Gate 1. Design an NAND gate by resizing the W/L ratio of the inverter. 29

30 30 CHAPTER 5. TRANSISTOR LEVEL DESIGN OF A HALF-ADDER 2. Design an AND gate next. 3. Generate a symbol for the AND Gate. 5.4 Half-Adder 1. Assemble the toplevel schematic of the half-adder cell using the XOR gate and the AND gate you have designed earlier.(use Add /rightarrowinstance /rightarrow Symbol by Path add a symbol.) 2. Demonstrate the functionality of the half-adder cell by driving its input with two non-overlapping clocks. 5.5 Submission Checklist 1. Discuss how you size up the CMOS inverter. Show calculations. 2. Submit the schematic of the XOR gate. 3. Submit the schematic of the NAND gate. 4. Submit the schematic of the AND gate. 5. Submit the toplevel schematic of the half-adder. 6. Submit the.cir and the.spi files under./tsmc018a directory. 7. Submit the waveforms of your input/output.

31 Chapter 6 Verilog and Transistor Level Simulation 1. Type icstudio & to start 2. Select Tools List Library List Editor. Set the location to../adk3_1/technology/ic/symbols (Figure 6.1) Figure 6.1: List Library 31

32 32 CHAPTER 6. VERILOG AND TRANSISTOR LEVEL SIMULATION 3. Link adk_daic design library (Figure 6.2) Figure 6.2: Add design library 4. Use File New Library to create the following libraries: (a) vlsi_tb for storing test benches (b) vlsi_trans for storing transistors schematics (c) vlsi_verilog for storing verilog scripts 5. You will use two verilog files in this tutorial:mux_2_1_tb to drive the simulation. Here is the verilog code for mux_2_1_tb. \ timescale 1 ns / 100 ps % this line is important! module mux_2_1_tb_a(output reg a1, reg b1, reg clk); //reg a1,b1,sel1; //reg clk; wire y1; initial begin

33 33 #100 $finish; end always begin clk=1; #5; clk=0; #5; end initial begin a1=1;b1=0; #10 a1=0; #5 b1=0; #5 a1=1; #5 b1=1; #5 a1=1; #5 a1=0; #5 b1=0; #5 a1=1; #5 a1=0; #5 b1=1; #5 a1=1; end endmodule 6. mux_2_1.v will be used in this tutorial to simulate the behavior of a two to one mux. Here is the code: timescale 1 ns /100 ps module mux_2_1 (output reg y1, input a1,b1,sel1); //reg y1; or b1 or sel1) begin if(sel1) y1=a1; else y1=b1; end

34 34 CHAPTER 6. VERILOG AND TRANSISTOR LEVEL SIMULATION endmodule 7. Import the verilog code into the library. (Figure 6.3) Figure 6.3: Import Verilog code 8. Create a symbol for each verilog code. (Figure 6.4) 9. Use Add Instance to generate a test bench. (Figure 6.5) The mux_2_1_tb generates the test signal and is implemented in Verilog. The mux_2_1 mimics the behavior of a mux and is implemented in Verilog. The inverter is implemented at the transistor level. 10. Enter the Simulation mode. Choose AMS_Simulation as the Configuration Type.(hint: select New Configuration) 11. Select Session simulator/viewer. Select ADMS for the simulator option. You can also select ADMS Interactive, but if you do that, you will have to type run -all to start the simulation once you are in the interactive mode. (Figure 6.6) 12. Since the mux cell is implemented in Verilog and the inverter is implemented at the transistor level. The simulator needs to learn how

35 35 Figure 6.4: Import Verilog code to convert a logicvalue(e.g. 1) to a voltage(e.g. 1.8V). You can define signal version rules by inserting interface element. (Simulation Interface Elements Insert, Figure fig:mixfig8) 13. Here is an example on how to specify the A2D conversion. (Figure 6.8) 14. Here is an example on how to specify the D2A conversion. (Figure 6.9) 15. You can check whether the a2d and d2a have been added to the files correctly by using View Command File. (Figure 6.10) 16. Sometimes the tool designates different nets for as the reference ground. It can use GROUND, GND or even VSS. You can have strange sim-

36 36 CHAPTER 6. VERILOG AND TRANSISTOR LEVEL SIMULATION Figure 6.5: A verilog/transistor level test bench Figure 6.6: AMDS ulation results when your ground is not tied to ground. When you see strange things (e.g. getting a 1.8 V at GND.) You need to tie the ground reference to 0. You can do this by choosing Option Additional and adding.connect statement as an optional arguement. (Figure 6.11) 17. Set up the simulator to display waveform after simulation. (Session Environment (Figure 6.12) 18. Make sure you add the 0.18 model file using Lib/Temp/Inc Include Files.

37 37 Figure 6.7: AMDS Figure 6.8: A2D 19. Set up parameters to run transcient simulation. 20. Click Run ADMS. (Figure 6.13)

38 38 CHAPTER 6. VERILOG AND TRANSISTOR LEVEL SIMULATION Figure 6.9: D2A Figure 6.10: Command File 21. View the waveforms using EZwave. (Figure 6.14)

39 Figure 6.11: Ground 39

40 40 CHAPTER 6. VERILOG AND TRANSISTOR LEVEL SIMULATION Figure 6.12: Display Waveform

41 41 Figure 6.13: RUN ADMS Figure 6.14: RUN ADMS

42 42 CHAPTER 6. VERILOG AND TRANSISTOR LEVEL SIMULATION

43 Chapter 7 Layout 1. Once you have created a schematic, you can prepare the design for layout by clicking Prep for Layout in the schematic_edit. This will create a *.src.net and an SDL viewpoint which will be used later (Figure 7.1). Figure 7.1: Prep for Layout 2. Close adk_daic. 3. Create a schematic driven layout (a) Click Create. Enter the following in the pop-up window: (b) For cell name, enter a name for the layout. (c) In the Process Name, enter the path to the adk3_1 design ticket, which may be different than the one shown in Figure 7.2. (d) For Rules File Name, enter the file tsmc018.rules in the design kit directory. 43

44 44 CHAPTER 7. LAYOUT Figure 7.2: Prep for Layout (e) Click on Existing Viewpoint. (f) Enter the path to the SDL(Figure 7.3). Figure 7.3: Enter the path to the SDL file (g) Scroll down options in IC palettes, and click on ADK_Edit. Transistors can be placed automatically using the AutoInst feature. The tool will not place instances automatically if the schematic is not ope. You can open a schematic in the layout window by clicking on the Open button next to the Logic under SDL in the ADK_Edit palette.

45 45 Figure 7.4: Place Instances Automatically (h) Complete the layout. Use the cells from the standard liblrary as your reference. (i) Please remember to place ports on your layout. You can do this by clicking port button next to the AutoInst button. Use the space bar to cycle through different layers. Place the ports on the correct metal layers. (j) Once all ports have been palced select Connectivity Port Add Text on Ports from the menu bar. Enter METAL# for the Shape layer and Metal#.PORT for the Text layer for each Metal# layer you have created port on, and then click OK. This will automatically add text too all the ports in your design. The port text is used by Calibre to identify the ports in your design. Without the text, the extracted netlist would be useless.

46 46 CHAPTER 7. LAYOUT

47 Chapter 8 DRC 1. Select Verification Load Rules in the ADK Edit. 2. Select Verification - DRC +Check+in the ADK Edit palette and click OK. This will perform DRC on your layout. Figure 8.1. Figure 8.1: Run DRC 3. To view the errors one at a time select Verification-DRC First to see the first DRC violation. Select Verification-DRC Next to step through the DRC errors currently in the results (errors) database. DRC errors are shown in the message area. (Figure 8.2.) Details about each DRC error can be found in the DRC rule deck. (e.g. Figure 8.3, /adk3_1/technology/ic/process/tsmc018.rules) 47

48 48 CHAPTER 8. DRC Figure 8.2: DRC error in the message area Figure 8.3: DRC rule deck

49 Chapter 9 Running DRC from the Calibre Menu 1. Select Run DRC from the Calibre pull-down menu (Figure 9.1). Figure 9.1: Start DRC 2. Enter the path to the DRC Rules File and Specify the DRC Run Directory (Figure 9.2). 3. Inputs tab and Outputs tab will be filled out automatically. Click on Run DRC tab to run the DRC. 4. DRC errors (if there is any in the layout) will be displayed in the DRC RVE window. Use the DRC RVE window to correct the DRC violation (Figure 9.3). 49

50 50 CHAPTER 9. RUNNING DRC FROM THE CALIBRE MENU Figure 9.2: Rules Figure 9.3: DRC RVE

51 Chapter 10 LVS 1. From the menu bar select Calibre Run LVS. This will launch Calibre Interactive-LVS. If this is the first time you have run Calibre LVS, click cancel. (Figure 10.1) Figure 10.1: LVS 2. Click the Rules on the left. 3. Set the rules file to: /adk3_1/technology/ic/process/tsmc018.calibre.rules 4. Set the LVS Run Directory to a directory of your choice. (Figure 10.2) 5. Next click the Inputs button. This panel controls the input files which Calibre will use. The layout tab should be set up correctly by default. (Figure 10.3) 6. Click the Netlist tab. This tab tells Calibre where to get the source(schematic) netlist for comparison. You can use either the Export from the schematic viewer option or specify the location of the assign1.src.net. (In Figure 10.4, assign1 is the name of the design cell.) 51

52 52 CHAPTER 10. LVS Figure 10.2: Rules Figure 10.3: Layout Netlist Figure 10.4: Schematic Netlist 7. Now select Setup LVS Options from the menu bar. For our purpose, we are only interested in the Supply tab. Set Power nets: VDD and Ground nets: GND. (V S is the ground net in assign1 in Figure 10.5)

53 53 Figure 10.5: Specify power and ground nets 8. Select File Save Runset As and save the runset you have created. 9. Click Run LVS.

54 54 CHAPTER 10. LVS

55 Chapter 11 xrc 1. Select Calibre Interactive-PEX from the menu bar. 2. Click cancel, if this is the first time you are running PEX. 3. Click the Rules. 4. The rule file should be of the form (Figure 11.1: /adk3_1/technology/ic/process/tsmc018.calibre.rules 5. Click the Inputs button. Figure 11.1: Rules 6. The Layout tab should be set correctly and you can ignore the H-Cells tab. (Figure 11.2 In the Netlist tab set the source file to the same one you used for performing LVS check. (Figure Select the Outputs button. At the top, the Extraction Type should be Transistor Level and you can choose one of the following types: RCC, RC, and C. (Figure 11.4) 55

56 56 CHAPTER 11. XRC Figure 11.2: Layout Tab Figure 11.3: Netlist Tab Figure 11.4: Extraction Type 8. In the Netlist tab, choose ELDO as the format and Use Names from Schematic. 9. Choose Setup PEX Options from the menu bar. In the Netlist tab, click the Ground node name: check box and enter the name of your reference ground. (Figure 11.5) In the LVS Options tab, set Recognize gates to the same settings you used for the LVS check.

57 57 Also enter the name for power nets and ground nets. (Figure 11.6) Figure 11.5: Reference Ground Figure 11.6: Power/Ground Nets 10. Select File Save Runset As. 11. Click on Run PEX.

58 58 CHAPTER 11. XRC

59 Chapter 12 Post Layout Simulation Reference: Mentor Graphics Schematic Driven Layout Using the ADK v Create a symbol (a) Type adk_daic & (b) Click Open-Symbol in the session palette. Enter a name for the new symbol(something different than the origianl design) and click OK. (c) In the symbol_draw palette, click Add-Rectangle, and then leftclick and drag to create a rectangle. (d) Add the pins to your symbol by clicking Add-Pin in the symbol_draw palette. In the window that pops up choose the Pin Type, then chose the Pin Placement. (Generally, V DD and GND are considered to have a Pin Type of IN. (e) Bring up the Add Multiple Properties window by first pressing F2 to unselect all, then right click and choose Properties (Logical). (f) Enter the following two properties: i. Property Name: ELEMENT ii. Property Value: X iii. Property Name: ASIM_MODEL iv. Property Value: <design> (assign2 in the previous example) v. Click OK. (g) Select a spot and left-click to place each property. 59

60 60 CHAPTER 12. POST LAYOUT SIMULATION (h) Check & Save the symbol. Once it passes all the checks you can close the symbol. 2. Build a test bench schematic so that it can use the extracted netlist created by Calibre. 3. Click Add-Instance in the schematic_edit palette. Browse and find the new symbol you just created and click OK, and then left-click in the schematic window to place the symbol. 4. Add pins to your schematic. 5. Click the Simulation button. 6. Click adk_schematic_sim and choose Setup Other-Include to bring up the Set Include paths window (Figure 12.1). Include the top level netlist(assign1.pex.netlist) created by Calibre and click OK(Figure 12.2). Figure 12.1: Include in the simulation 7. Remember to the transistor model in the simulation. Click on Default Sim Palette. 8. Click /Lib/Temp/Inc and add the model file. 9. Click on the adk_schematic_sim palette, create a netlist by clicking Netlist-Write. This will create a new netlist of your deisgn using the new symbol.

61 61 Figure 12.2: assign.pex.netlist 10. Open the netlist located at <design>/tsmc018a/*.spi and find a line which looks like: X1 <pin list> <design>. Pay attention to the order of the pin list. 11. Open the *.pex.netlist and identify the line which looks like:.subckt <design> <pin list>. 12. Change the *.pex.netlist file so that the pin list matches the one in the.spi file. (Figure 12.3) Figure 12.3: Change Pin List

62 62 CHAPTER 12. POST LAYOUT SIMULATION 13. Simulate your extracted circuit and examine the waveform. (e.g. adk_schematic_sim Results View (Figure 12.4)) Figure 12.4: Post Layout Simulation