PREPARED BY: S.SAKTHI, AP/IT

Transcription

1 CHETTINAD COLLEGE OF ENGINEERING & TECHNOLOGY DEPARTMENT OF EIE CS6303 COMPUTER ARCHITECTURE (5 th semester)-regulation MARKS QUESTION BANK WITH ANSWER KEY UNIT I OVERVIEW & INSTRUCTIONS 1. Explain Eight ideas invented for computer design (8marks) 1. Design for Moore s Law 2. Use Abstraction to Simplify Design 3. Make the Common Case Fast 4. Performance via Parallelism 5. Performance via Pipelining 6. Performance via Prediction 7. Hierarchy of Memories 8. Dependability via Redundancy 2. Explain Components of a computer system or hardware / software of computer system (16marks) APRIL/DEC-15, MAY 2016 Diagram for Components of a computer system Functional unit, Memory unit (primary and secondary memory),cpu, Input/Output devices,types of software (Application & System Software), OS Input devices -keyboard, mouse etc., Output devices- LCD, LED, Types of printer Printers definition and its types(impact &Non-impact printers) Impact printers: Line, Drum, Chain, Dot matrix (Definition and its advantages, disadvantages) Non impact printers : Inkjet & Laser Printers(Definition and its advantages, disadvantages) 3. Discuss Technology or generations of computer in brief(16marks) First generation computer Explanation,Advantages and Disadvantages Second generation computer Explanation,Advantages and Disadvantages Third generation computer Explanation,Advantages and Disadvantages Fourth generation computer and

2 Fifth generation computer Explanation,Advantages and Disadvantages 4. Discuss Performance of CPU & CPU performance equation (16marks) DEC-2014 Definition Formula Example problems 5. Write note on Power wall equation of CPU (8marks) Diagram and its explanation 6. Write note on Uniprocessors to multiprocessors (8marks) Definition Comparison, Advantages and disadvantages 7. Explain Instruction types in detail. (16 marks) APRIL ,1,2,3 address instruction types with examples 8. Explain Logical operations & control operations with examples (16 marks)

3 9. Explain Addressing and addressing modes types with examples or Explain immediate, register, Base/Displacement, PC relative & Pseudo direct addressing (Theory and problems )(16marks) APRIL/DEC-2015,MAY 2016 Register addressing mode Definition, Diagram, Example with description Register direct and indirect addressing mode Definition, Diagram, Example with description Immediate addressing mode Definition, Diagram, Example with description Base/Displacement/Index addressing mode Definition,Diagram, Example with description PC relative addressing mode Definition, Diagram, Example with description Pseudo direct addressing mode Definition, Diagram,Example with description Auto increment and decrement addressing mode Definition,Diagram,Example with description. 10. Suppose we have two implementations of the same instruction set architecture. Computer A has a clock cycle time of 250 ps and a CPI of 2.0 for some program, and computer B has a clock cycle time of 500 ps and a CPI of 1.2 for the same program. Which computer is faster for this program and by how much? (8marks) CPU performance =1.2(computer A is 1.2 times faster than computer B) 11. A compiler designer is trying to decide between two code sequences for a particular computer. The hardware designers have supplied the following facts: (8marks) class BC CPI for each instruction class A B C CPI Instruction counts for each instruction class Code Sequence A B C For a particular high-level language statement, the compiler writer is considering two code sequences that require the following instruction counts: a. Which code sequence executes the most instructions? Code sequence 2 b. Which will be faster? Code sequence 2 c. What is the CPI for each sequence? CPI1=2.0,CPI2=1.5 (Dec 2014)

4 12. A program runs in 12 seconds on computer A, which has a 3 GHz clock. We have to design a computer B such that it can run the same program within 9 seconds. Determine the clock rate for computer B. Assume that due to increase in clock rate, CPU design of computer B is affected ant it requires 1.2 times as many clock cycles as computer A for execution this program. (8marks) CPU clock cycle A=36*109 cycles, Clock rate B=4.8GHZ 13. Assume a two address format specified as source, destination. Examine the following sequence of instructions and explain the addressing modes used and the operation done in every instruction. (Dec 2014) (10 marks) 1)Move (R5)+, R0 2)Add (R5)+, R0 3)Move R0, (R5) 4)Move 16(R5),R3 5)Add #40,R5 (1) Move the content of R5 value into R0 register, after then R5 value is automatically incremented. (2) Add R5 with R0, result is stored in R0 and then R5 value is automatically incremented. (3)Move the R0 value into address of R5 (4)First 16 is added with R5, Move the resultant value to R3. (5)Add immediately 40 with R5, resultant is stored in R Consider three different processors p1,p2,p3 executing same instruction set.p1 has a 3Ghz clock rate and a CPI of 1.5. P2 has a 2.5 Ghz clock rate and a CPI of 1.0.P3 has a 4.0 Ghz clock rate and has a CPI of 2.2. (10 marks) (i) Which processors has the highest performance expressed in instruction per second? CPU time=instruction count* CPI / Clock rate CPU time P1=Instruction count* CPI / Clock rate =n*1.5/3*10 9 =n*0.5 *10-9 sec CPU time P2=Instruction count* CPI / Clock rate = n*0.4*10-9 sec CPU time P3=Instruction count* CPI / Clock rate = n*0.55 * 10-9 sec Therefore p2 produces highest performance than other processors. (ii) If the processor each execute a program in 10 seconds, find the number of cycles and the number of instructions. Number of clock cycles: CPU time for p1,p2,p3=10 sec CPU time= CPU clock cycles / clock rate CPU clock cycles = CPU time * clock rate CPU clock cycles P1 = 10 sec * 3 * 10 9 Hz =30*10 9 cycles

5 CPU clock cycles P2 = 10 sec * 2.5 * 10 9 Hz =25*10 9 cycles CPU clock cycles P3 = 10 sec * 4 * 10 9 Hz = 40*10 9 cycles Number of instructions count: CPU clock cycles = Instruction count* CPI Instruction count = CPU clock cycles / CPI Instruction count P1=CPU clock cycles / CPI = 30*10 9 cycles / 1.5 =20 *10 9 instructions Instruction count P2 = CPU clock cycles / CPI = 25*10 9 cycles / 1.0 =25 *10 9 instructions Instruction count P3= CPU clock cycles / CPI = 40*10 9 cycles / 2.2 =18.18 *10 9 instructions

6 UNIT II ARITHMETIC OPERATIONS 1. Write notes on ALU - Addition and subtraction (Theory or problem) (8/16 marks) (1 s complement, 2 s complement, addition and Subtraction problem, half and full adder, look ahead carry addition) 2. Explain look ahead carry addition. (8marks) Definition, Diagram with explanation 3. Explain half and full adder in detail. (8marks) Definition, Diagram with explanation 4. Explain Booths Multiplication algorithm in detail.(theory or problem) (16marks) MAY,DEC-2015, MAY 2016 (Recode multiplier & bit pair recoding multiplication problems, Booths multiplication problems) 5. Explain Division algorithm in detail (Theory or problem) (16marks) DEC-2014,2015 (Restoring and Non restoring division problems) (i) Perform the division of following numbers using restoring algorithm: Dividend = 1010, Divisor = 0011(8) Answer: Quotient=0011, Remainder=00001 (ii)perform the division of following numbers using non-restoring algorithm: Dividend = 1010, Divisor = 0011(8) Answer: Quotient=0011, Remainder= Explain Floating Point operations (floating point addition, floating point subtraction, floating point multiplication and floating point division-steps, flowchart with example problems) in detail. (Theory or problem) (16marks) MAY 2016, May 2015

7 7. Explain single and double precision in IEEE format. Example: Represent in Single and double precision format. Example: Represent in Single and double precision format 8. Explain floating point addition and subtraction in detail. (16marks) May 2015 OR Perform floating point addition using the numbers and use the floating point addition algorithm.

8 9. Perform floating point multiplication using the numbers and use the floating point addition algorithm. 10. Write notes on Subword parallelism. (4 marks) Definition

9 UNIT III PROCESSOR AND CONTROL UNIT 1. Explain Basic MIPS implementation. (16marks) DEC-2015 Definition Architecture diagram with explanation 2. Explain Building datapath in detail. (16marks) DEC 2014 Data path segment for ALU instructions Data path segment for load and store word instructions Data path segment for branch instruction 3. Explain Control Implementation scheme of MIPS. (16marks) R type, Load, Branch on equal and Jump instructions 4. Explain Pipelining and types of Pipeline hazards or (16marks) MAY/DEC 2015, MAY 2016 Pipeline definition Types of pipeline- Data, structural and control / instruction hazards (Definition, Diagram with explanation) Various ways to handling Data hazards, structural and control / instruction hazards 5. Explain Pipelined data path and control unit in detail.or Explain implementation of MIPS instruction pipeline and pipeline control in detail (16marks) DEC-2015,MAY 2016 Definition Architecture diagram with explanation 6. Explain various ways to handling Data hazards (8 marks) (MAY 2015, DEC 2014) NOP Definition,Example with explanation Bubble Definition,Example with explanation Operand forwarding Definition,Example with explanation 7. Explain various ways to Handling Control hazards (8 marks) (MAY 2015, DEC 2014) Branch prediction, Multiple streams, Prefetch branch target & loop buffer 8. Write notes on branch prediction techniques. (8 marks) Definition Prediction techniques:

10 Predict never taken, always taken, by opcode, taken/not taken switch and branch history table Branch prediction strategies: Static and Dynamic 9. Explain Exceptions and its ways to handle exception in MIPS. (16marks) Types of exception Ways of handling exception in MIPS architecture with neat sketch.

11 UNIT IV PARALLELISM 1. Explain Instruction-level-parallelism. (8/16marks) DEC 2014 Static & Dynamic multi-issue processors Limitations of ILP. 2. Explain Parallel processing challenges.(16marks) Amdahl s law Load balancing problem Speedup challenging problem 3. Explain Flynn's classification. (8/16marks) MAY/DEC 2015,MAY 2016 (SISD, SIMP, MISD, MIMD, SPMD(single program multiple data stream),mpmd, VECTOR and SCALAR systems) Single program, multiple data streams (SPMD) Multiple autonomous processors simultaneously executing the same program (but at independent points, rather than in the lockstep that SIMD imposes) on different data. Also termed single process, multiple data - the use of this terminology for SPMD is technically incorrect, as SPMD is a parallel execution model and assumes multiple cooperating processes executing a program. SPMD is the most common style of parallel programming. The SPMD model and the term was proposed by Frederica Darema. Gregory F. Pfister was a manager of the RP3 project, and Darema was part of the RP3 team. Multiple programs, multiple data streams (MPMD) Multiple autonomous processors simultaneously operating at least 2 independent programs. Typically such systems pick one node to be the "host" ("the explicit host/node programming model") or "manager" (the "Manager/Worker" strategy), which runs one program that farms out data to all the other nodes which all run a second program. Those other nodes then return their results directly to the manager. An example of this would be the Sony PlayStation 3 game console, with its SPU/PPU processor. 4. Explain Hardware multithreading and its types. (8/16marks) DEC-2015/2014, MAY 2015,2016 Fine/Interleaved Definition, Diagram with explanation, advantages & disadvantages

12 Coarse/Blocked Definition, Diagram with explanation, advantages & disadvantages & Simultaneous Multithreading (SMT) Definition, Diagram with explanation, advantages & disadvantages 5. Explain Multicore processors. (8/16marks) DEC-14,MAY 2016 Shared multicore processors (SMP) & Distributed / cluster-message passing multicore processors (Definition, Diagram with explanation, advantages & disadvantages)

13 UNIT V MEMORY AND I/O SYSTEMS 1. Explain Memory hierarchy (8 marks) MAY 2015 Memory hierarchy diagram and its explanation 2. Explain Memory technologies (16 marks) MAY 2015 RAM ROM,PROM, EPROM, EEPROM DRAM Flash memory SDRAM DDR SDRAM 3. Explain Cache memory in detail. (16 marks) DEC 2014,MAY 2016 Cache memory Definition with diagram Cache organization Cache read and write operations Program locality Locality of reference (temporal and spatial) Cache mapping techniques Direct, Associative mapping techniques Cache updating policies Write through, Buffered write through system, Write back system Page replacement algorithms Measuring and improving cache performance 4. Explain Virtual memory (16 marks) MAY,DEC-2015 Virtual memory concept Paging Page translation TLB Page size Page fault and demand paging Page replacement algorithms 5. Explain Input/output system(16 marks)

14 Requirements of I/O system I/O interfacing techniques Data transfer techniques 6. Explain Programmed I/O(16 marks) Definition Flowchart and its explanation Interrupts and its types 7. Explain DMA in detail (16 marks) DEC-2015, MAY 2016 Definition Flowchart DMA opeartions DMA block diagram with explanation Data transfer modes Bus arbitration -DEC 14&15 8. Write notes on interrupt. (8/16 marks) Definition Types of interrupts Recognition of interrupt and response to interrupt Interrupt priority schemes 9. Explain I/O processors. (8/16 marks) Definition Features and functions of IOP Block diagram of IOP CPU & IOP communication ***************************************************************************************

15 EXTRA QUESTION BANK FOR UNIT-II 1. Explain Multiplication algorithm in detail.(theory or problem) (16marks) Multiplication algorithm: Sequential Version of the Multiplication Algorithm and Hardware

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18 2. Explain Division algorithm in detail (Theory or problem) (16marks) A Division Algorithm and Hardware

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