CS/ECE/752 Chapter 2 Instruction Sets Instructor: Prof. Wood

Transcription

1 CS/ECE/752 Chapter 2 Instruction Sets Instructor: Prof. Wood Computer Sciences Department University of Wisconsin Slides developed by Profs. Falsafi,, Hill, Smith, Sohi,, and Vijaykumar of Carnegie Mellon University, Purdue University, and University of Wisconsin Classic paper: many observations are still true most historians credit Eckert and Mauchly for the ideas It is evident that the machine must be capable of storing in some manner not only the data but also the instructions which govern the actual machine. Conceptually we have discussed above two different forms of memory: storage of numbers and storage of orders. The memory organ can be used to store both numbers and orders. 1 2 Arithmetic: binary arithmetic two s complement iterative carry iterative multiply (carry-save adders) rounding vs jamming non-restoring division no floating-point. Why? Control: 40-bit data 20-bit instructions 8-bit opcodes 12-bit addresses basic instructions conditional and unconditional branches data transfer ALU and shift store into orders. Why? 3 4 1

2 Instruction set architecture (ISA) is the structure of a computer that a machine language programmer (or a compiler) must understand to write a correct (timing independent) program for that machine IBM introducing 360 in 1964 Instruction set aspects operands memory issues operations (mostly control) assumes you know what simple pipelines look like (CS 552) Why in the processor? faster access shorter address Accumulator less hardware high memory traffic likely bottleneck Stack code density bottleneck while pipelining (why?) e.g., JAVA VM 5 6 Registers (8 to 256 words) flexible register must be named code density separate name space Registers faster (no addressing modes, no tags) deterministic access time easier to add ports (usually smaller) short identifier smaller must save/restore on procedure calls can not take address of register fixed size (can not fit strings, structures/records) may have separate registers for Integers and FP compilers must manage (an advantage?) 7 8 2

3 !"# Can we increase number of registers? Hold operands longer (reducing memory traffic & runtime) longer register specfiers (except with register windows) slower registers more state slows context switches ALU instructions combine operands Number of explicit operands one, r i = op r j two, r i = r i op r j or r i = op r j three, r k = r i op r j Operands in registers or memory any combo, orthogonal, e.g., VAX at least one register, not orthogonal, e.g., IBM 360/370 all registers, orthogonal but loads/stores, e.g., Cray, RISCs 9 10!"# $ % Order of bytes in words Big endian MSB at address 0x...0 Little endian MSB at address 0x..3 Big endian IBM, Motorola, SPARC Little endian DEC, Intel Windows NT requires this (pathetic!) Mode selectable PowerPC, MIPS becoming more common

4 What is alignment? address mode size = 0 natural boundaries! e.g., aligned word (4 bytes) load from 0x.0 e.g., unaligned word (4 bytes) load from 0x.1 Placing no restrictions simpler software hardware must detect misalignment, make 2 memory accesses expensive logic, may slow down all references (why?) sometimes required for backward compatibility!! &' Restricted alignment software must guarantee alignment hardware only detects misalignment trap handler aligns Middle ground misaligned data ok but requires multiple instructions compiler must still know trap on misaligned access 13 14! ( Mode Semantics Register R i Immediate #n Displacement M[R i + #n] Register indirect M[R i ] Indexed M[R i + R j ] Absolute M[#n] Memory indirect M[M[R i ]] Auto-increment M[R i ]; R I += d Auto-decrement M[R i ]; R i -= d Scaled M[R i + #n + R j * d] Update M[R i = #n + R i ] Modes 1-4 account for 93% of all VAX operands [Clark & Emer] Type Arithmetic and logical Data transfer Control System Floating point Decimal String Example Instruction and, add move, load branch, jump, call, return trap, rett add, mul, div, sqrt addd, convert move, compare

5 ) ) Aspects: 1. Taken or not taken? 2. Where is the target? 3. Links return address? 4. Saves/restores state? Instructions that change the PC Instructions Aspects (Conditional) branches 1,2 (Unconditional) jumps 2 Function calls 2,3,4 Function returns 2,4 System calls 2,3,4 System returns 2,4 Compare and branch no extra compare no state passed between instructions no state to save (correctly) on traps and context switches requires ALU ops restricts code scheduling opportunities Implicitly set condition codes can be set for free restricts code scheduling extra state to save/restore ) ) &' Explicitly set condition codes can be set for free decouples branch/fetch from pipeline extra state to save/restore Condition registers compares and condition operations operate on separate regs. decouples complex condition evaluation from pipeline extra state to save/restore Condition in general-purpose registers no special state uses up a register branch condition separate from branch logic in pipeline ) ) &' Some data from MIPS > 80% branches use immediate data > 80% of these are zero immediates 50% branches compare equal, less than, or greater than zero Compromise in MIPS branch instructions with equal, less than or greater than zero compare instructions for all other compares

6 % ) * % ) *&' Arbitrary specifier orthogonal more bits to specify => more time to decode branch execution and target separated in pipeline PC-relative with immediate position independent, target computable in branch unit short immediate sufficient #bits < 4 (47%), < 8 (94%) target must be known statically => can t go far other techniques needed for returns, distant jumps Register short specifier can jump anywhere can have dynamic target branch and target are separated in the pipeline Vectored traps (for system calls) protection implementation headaches % ) *&' + * Common compromises Type (Conditional) branches (Unconditional) jumps Function calls Function returns System calls System returns Where is the target? PC-relative PC-relative and register PC-relative and register register trap register What state? function calls => registers system calls => registers, flags, PC, PSW, etc. Hardware need not save registers caller can save registers in use callee can save registers it will use Hardware register save IBM STM, VAX CALLS faster? Many recent ISA s do no register saving or do implicit saving with register windows

7 Generic assembly code SUB R1, R2, R3 Means R1 gets R2 - R3 Data sizes Byte = 8 bits Halfword = 16 bits Word = 32 bits Doubleword = 64 bits Quadword = 128 bits,!- DEC 1977 VAX 11/780 upward compatible from PDP bit words and addresses virtual memory 16 GPRs (R15 PC, R14 SP), CCs extremely orthogonal and memory-memory decode as byte stream, variable in length opcode, operation, #operands, operand types 25 26,!-.)/,!-!( 8, 16, 32, 64, 128 char string, 8 bits/char decimal, 4 bits/char numeric string, 8 bits/digit literal, 6 bits 8, 16, 32 bit immediates register, register deferred 8, 16, 32 bit displacements 8, 16, 32 bit displacements deferred indexed (scaled) autoincrement, autodecrement autoincrement deferred

8 ,!-,!-$0 data transfer including string move arithmetic and logical (2 and 3 operands) control (branch, jump, etc.) e.g., AOBLEQ function calls save state bit manipulation floating point: add, sub, mul, div, polyf system: exception, VM other: CRC, INSQUE addl3 R1, 737(R2), #456 byte 1: addl3 byte 2: mode, R1 byte 3: mode, R2 byte 4-5: 737 byte 6: mode byte 7-10:456 VAX has too many modes and formats However, few modes/formats => fast decoding in the pipeline Arugment for RISC? Intel in 1978 chosen for IBM PC 1980 remains most popular 16-bit architecture upward compatible with 8080 complex: difficult to explain and impossible to love special purpose registers 4 arithmetic, 4 address, 4 segment, 2 control addresses: 16-bit segments << $ + 16-bit offset 64K 16 KB-aligned 64KB segments many formats ( 4 32-bit byte addresses aligned load/store: only displacement addressing standard data types 3 fixed length formats bit GPRs (R0 = 0) bit or bit FPRs FP status register no CCs

9 ( 4&' Data transfer load/store word load/store byte/halfword signed? load/store FP signle/double moves between GPRs and FPRs ALU add/sub signed? Immediate? mul/div signed? and, or, xor, immediate? shifts: ll, rl, ra immediate? sets immediate? Control FP ( 4&' branches == 0, <> 0 conditional branch testing FP bit jump, jump register jump&link, jump&link register trap, return from trap add/sub/mul/div single/double fp converts, fp set ( I-type R-type J-type opcode opcode opcode rs1 rd immediate rs1 rs2 rd func offset added to PC Compiler goals: all correct programs execute correctly most compiled programs execute fast compile fast provide support for debugging I: ALU immediate, load/store, branches, jump register R: RRR ALU ops J: unconditional jumps

10 62 6 % % 7 4 Multiple phases to manage complexity Lexical analysis Parsing => Intermediate representation Optimization & code generation Procedure In-lining Loop optimizations Common sub-expression elimination Jump optimization Constant propagation Register allocation Strength reduction Pipeline scheduling Generation of assembly code What compiler writers want? regularity orthogonality composability Compilers perform a giant case analysis too many choices make it hard Orthogonal instruction sets operation, addressing mode, data type % % 7 4 One solution or all possible solutions 2 branch conditions, eq and lt or all six conditions, eq, ne, lt, gt, le, ge not 3 or 4 Primitives not solutions by giving too much semantic content to the instruction, the machine designer made it possible to use the instruction only in limited contexts. In many cases the complex instructions are synthesized from more primitive operations, which if the compiler had access to, could be recomposed to more closely model the feature actually needed VAX 8700 vs MIPS M/R2000 Combines 3 features: Architecture Implementation Compilers and OS Argues that implementation effects are second order compilers are similar RISCs are better than CISCs: fair comparison?

11 7 74 RISC factor: {CPI VAX * Instr VAX }/{CPI MIPS * Instr MIPS } 7 74 RISC vs CISC Benchmark Instruction ratio CPI MIPS CPI VAX CPI ratio RISC factor Li Eqntott Fpppp Tomcatv Compensating factors increase VAX CPI but decrease VAX instruction count increase MIPS instruction count e.g. 1: loads/stores vs operand specifiers Factors favoring VAX big immediate values not-taken branches incur no delay Factors favoring MIPS operands specifier decoding number of registers separate floating-point unit simple branches/jumps (lower latency) no complex instructions instruction scheduling translation buffer branch displacement size 7% 74 Two RISCs: Alpha and PowerPC At this point many RISC purists will undoubtedly claim that this is not a RISC design..this is a second generation RISC, representing a reasonable melding of RISC and CISC concepts likely to be the direction for many future RISC designs P. Hester, RS/6000 Hardware Background & Philosophies We re-applied the principles of RISC to processor design to get maximum clock speed R. Sites, RISC enters new generation. An insider s look at the development of DEC s Alpha

12 7% 74 Recall the Iron Law Time = Instr count x CPI x clock speed Alpha optimizes the last two (emphasis on the 3rd) PowerPC optimizes the first two 5 Feature PowerPC Alpha Basic Arch Ld/St Ld/St Instr Length 32 bits 32 bits Byte/Halfword/ ld/st Yes No Condition Codes Yes No Conditional Moves No Yes Integer Registers Integer Register Size 32/64 bits 32 bits Instruction formats similar PowerPC has slightly longer immediate field PowerPC provides 3 source FP regs Alpha has longer branch/jump displacements Loads and stores Alpha has only register+displacement PowerPC has register+register PowerPC has update addressing Floating point! PowerPC supports A*B+C and A*B-C instructions Data Alignment PowerPC allows any alignment Alpha faster if aligned Alpha uses multiple instruction sequence if unaligned

13 ! Byte operations PowerPC has byte ld/st Alpha has only ld/st 32 & 64 bits more instructions (insert/extract) for other lengths Branches PowerPC uses explicit condition codes and CTR Alpha uses general registers 49 13