CHAPTER 2: INSTRUCTION SET PRINCIPLES. Prepared by Mdm Rohaya binti Abu Hassan

Transcription

1 CHAPTER 2: INSTRUCTION SET PRINCIPLES Prepared by Mdm Rohaya binti Abu Hassan

2 Chapter 2: Instruction Set Principles Instruction Set Architecture Classification of ISA/Types of machine Primary advantages and disadvantages of each class of machine Classification of General Purpose Register Machines Addressing modes Aligning Addresses Interpreting Memory Addresses Addressing Modes for Desktops and Servers Addressing Mode Usage (VAX) DLX Instruction Set

3 Instruction Sets What is an instruction set? Set of all instructions understood by the CPU Each instruction directly executed in hardware

4 Instruction Set Architecture (ISA) Definition: The instruction set architecture is informally the set of programmer visible registers and address spaces and the set of instructions that can operate on them.

5 Instruction Set Architecture (ISA) Instruction set architecture of a machine fills the semantic gap between the user and the machine. The ISA specifies the size of main memory, number of registers, and number of bits per instruction. It also specifies exactly which instructions the machine is capable of performing and how each of the instruction bits is interpreted.

6 Instruction Set Architecture (ISA) It is all of the programmer-visible components and operations of the computer The ISA provides all the information needed for someone to write a program in machine language translate from a high-level language to machine language

7 Instruction Set Architecture (ISA) ISA serves as the starting point for the design of a new machine or modification of an existing one.

8 Instruction Set Architecture (ISA) software instruction set hardware

9 Instruction Set Architecture (ISA)

10 Classification of ISA The type of internal storage in the CPU is the most basic differentiation. The major choices are a stack the operands are implicitly on top of the stack an accumulator one operand is implicitly the accumulator a set of registers all operands are explicit either registers or memory locations

11 Classification of ISA Stack Architecture: Operands are implicit. They are on the top of the stack. For example, a binary operation pops the top two elements of the stack, applies the operation and pushes the result back on the stack.

12 Classification of ISA Accumulator Architecture: One of the operands is implicitly the accumulator. Usually one of the source operand and the destination operand is assumed to be the accumulator.

13 Classification of ISA General Purpose Register Architecture: Operands are explicit: either memory operands or register operands. Any instruction can access memory. Load/Store Architecture: Only load/store instructions can access memory. All other instructions use registers. Also referred to as register- register architecture.

14 Types of Machines

15 Code Sequence for C=A+B Stack Accumulator Register-memory Register-register Push A Load A Load R1, A Load R1, A Push B Add B Add R1, B Load R2, B Add Store C Store C Add R3, R1, R2 Pop C Store C, R3

16 Classification of ISA While most early machines used stack or accumulator-style architectures, all machines designed in the past ten years use a general purpose architecture. Stack architecture : Early machines Accumulator architecture : Early machines General purpose register (GPR) architecture : machines after 1980.

17 Classification of ISA Reasons for emergence of general-purpose register (GPR) machines17 1. Registers are faster than memory 2. Registers are easily used by a compiler and used more effectively. 1. Example: (A*B)-(C*D)-(E*F) for stack machine? for GPR machine? 3. Registers can be used to hold variables: Reduce memory traffic, improve code density, speed up program.

18 Classification of General Purpose Register Machines There are two major instruction set characteristics that divide GPR architectures. 1. Concerns whether an ALU instruction has two or three operands 2. how many of the operands may be memory addressed in ALU instruction

19 Types of GPR Machines Number of memory address Max # of operands allowed Examples 0 3 SPARC, MIPS, PA, PowerPC 1 2 Intel 80X86, Motorola VAX 3 3 VAX

20 Classification of General Purpose Register Machines 1. They concern whether an ALU instruction has two or three operands Example: ADD R3, R1, R2 R3 <-R1 + R2 or ADD R1, R2 R1 <- R1 + R2 3 operands, R1.R2 and R3 2 operands, R1 and R2

21 Classification of General Purpose Register Machines 2. how many of the operands may be memory addressed in ALU instruction Register- Register (Load/Store) ADD R3, R1, R2 (R3 <- R1 + R2) Register - Memory ADD R1, A (R1 <- R1 + A) Memory - Memory ADD C, A, B (C <- A + B)

22 Primary advantages and disadvantages of each class of machine Machine Type Stack Accumulator Register Advantages Simple model of expression evaluation. Good code density. Minimizes internal state of machine. Short instructions Most general model for code generation Disadvantages A stack can't be randomly accessed. It makes it difficult to generate efficient code. Since accumulator is only temporary storage, memory traffic is highest. All operands must be named, leading to longer instructions.

23 Addressing modes ISA design must define how memory addresses are interpreted and specified in the instructions. Addressing modes are the ways how architectures specify the address of an object they want to access. In GPR machines, an addressing mode can specify a constant, a register or a location in memory.

24 Addressing modes Addressing Modes Example Instruction Meaning When used Register Add R4,R3 R4 <- R4 + R3 When a value is in a register Immediate Add R4, #3 R4 <- R4 + 3 For constants Displacement Add R4, 100(R1) Accessing local R4 <- R4 + M[100+R1] variables Accessing using a Register deffered Add R4,(R1) R4 <- R4 + M[R1] pointer or a computed address Indexed Add R3, (R1 + R2) R3 <- R3 + M[R1+R2] Useful in array addressing: R1 - base of array R2 - index amount Direct Add R1, (1001) R1 <- R1 + M[1001] Useful in accessing static data

25 Addressing modes Addressing Modes Example Instruction Memory deferred Add Autoincrement Autodecrement Scaled Add R1, (R2)+ Add R1,-(R2) Add R1, 100(R2)[R3] Meaning R1 <- R1 + M[M[R3]] R1 <- R1 +M[R2] R2 <- R2 + d R2 <-R2-d R1 <- R1 + M[R2] R1<- R1+M[100+R2+R3*d ] When used If R3 is the address of a pointer p, then mode yields *p Useful for stepping through arrays in a loop. R2 - start of array d - size of an element Same as auto increment. Both can also be used to implement a stack as push and pop Used to index arrays. May be applied to any base addressing mode in some machines.

26 Addressing modes - Notation <- - assignment M - the name for memory: M[R1] refers to contents of memory location whose address is given by the contents of R1

27 Interpreting Memory Addresses How is a memory address interpreted? Byte addressed: Provide access for bytes (8 bits), half words (16 bits), words (32 bits), and double words (64 bits) Conventions for ordering the bytes within a word: Little Endian: put byte whose address xxxx00 at LSB position. followed by DEC and Intel Word address Data Big Endian: Put byte whose address xxxx00 at MSB position. followed by IBM, Motorola and others Word address Data

28 Example To store a word in byte-addressable memory (i.e. where each element of memory is one byte), you have to break up the 32 bit quantity into 4 bytes. Thus, if the word was 0x01ab23cd, it's broken up into 0x01, 0xab, 0x23, 0xcd.

29 Interpreting Memory Addresses When operating within one machine, the byte order is often unnoticeable - only programs that access the same locations as both words and bytes can notice the difference. However, byte order is a problem when exchanging data among machines with different ordering.

30 Aligning Addresses In some machines, accesses to objects larger than a byte must be aligned. An access to an object of size s bytes at byte address A is aligned if A mod s = 0. Object Addressed Aligned at Byte Offset byte 0,1,2,3,4,5,6,7 never halfword 0,2,4,6 1,3,5,7 Misaligned at Byte Offset word 0,4 1,2,3,5,6,7 doubleword 0 1,2,3,4,5,6,7

31 Aligning Addresses Quantity Address divisible by (Binary) address ends in Byte 1 anything Halfword (16 bits) 2 0 Word (32 bits) 4 00 Doubleword (64 bits) 8 000

32 Aligning Addresses

33 Aligning Addresses Misalignment causes hardware complications, since the memory is typically aligned on a word boundary. A misaligned memory access will, therefore, take multiple aligned memory references. Misalignment typically results in an alignment fault that must be handled by the OS

34 Addressing Mode How architectures specify the address of an object they will access? In a GPR, an addressing mode can specify a constant, a register, a location in memory (used to compute effective address). Immediate or literals are usually considered as memory addressing mode. Addressing modes that depend on the program counter is called PCrelative addressing. Addressing modes can significantly reduce instruction counts, but may add to the complexity of building a machine and increase the average CPI.

35 Addressing Modes for Desktops and Servers Register ADD R4, R3 Immediate ADD R4, #3 Displacement ADD R4, 100(R1) Register Indirect ADD R4, (R1) Indexed ADD R3, (R1+R2) Direct (Absolute) ADD R1, (1001) Memory Indirect ADD Autoincrement ADD R1, (R2)+ Autodecrement ADD R1, -(R2) Scaled ADD R1, 100(R2)[R3]

36 Addressing Mode Usage (VAX)

37 Operations in the Instruction Set Data transfer instructions. Arithmetic and logic instructions. Instructions for control flow: conditional and unconditional branches, jumps, procedure calls and procedure returns. System calls. Floating point instructions. Decimal instructions. String instructions. Graphics instructions

38 DLX The DLX(pronounced "Deluxe") is a RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal designers of the MIPS and the Berkeley RISC designs (respectively), the two benchmark examples of RISC design. The DLX is essentially a cleaned up and simplified MIPS, with a simple 32-bit load/store architecture. Intended primarily for teaching purposes, the DLX design is widely used in university-level computer architecture courses.

39 DLX Instruction Set The architecture of DLX was chosen based on observations about most frequently used primitives in programs. DLX provides a good architectural model for study, not only because of the recent popularity of this type of machine, but also because it is easy to understand. Like most recent load/store machines, DLX emphasizes A simple load/store instruction set Design for pipelining efficiency An easily decoded instruction set Efficiency as a compiler target

40 DLX s Operation 1. Load/Store Any of the GPRs or FPRs may be loaded and stored except that loading R0 has no effect. 2. ALU Operations All ALU instructions are register-register instructions. The operations are : - add, subtract, AND, OR, XOR,shifts Compare instructions compare two registers (=,!=,<,>,=<,=>). If the condition is true, these instructions place a 1 in the destination register, otherwise they place a 0.

41 DLX s Operation Branches/Jumps All branches are conditional.the branch condition is specified by the instruction, which may test the register source for zero or nonzero. Floating-Point Operations - add - subtract - multiply - divide

42 DLX s Operation There are four classes of instructions: 1. Load/Store 2. ALU Operations 3. Branches/Jumps 4. Floating-Point Operations

43 DLX Instruction Set opcode Data transfers Instruction meaning Move data between registers and memory, or between the integer and FP or special register; only memory address mode is 16-bit displacement + contents of a GPR LB, LBU, SB Load byte, load byte unsigned, store byte LH, LHU, SH Load halfword, load halfword unsigned, store halfword LW, SW LF, LD, SF, SD MOVI2S, MOVS2I MOVF, MOVD MOVFP2I, MOVI2FP Load word, store word (to/from integer registers) Load SP float, load DP float, store SP float, store DP float (SP - single precision, DP - double precision) Move from/to GPR to/from a special register Copy one floating-point register or a DP pair to another register or pair Move 32 bits from/to FP tegister to/from integer registers

44 DLX Instruction Set opcode Arithmetic / Logical ADD, ADDI, ADDU, ADDUI SUB, SUBI, SUBU, SUBUI Instruction meaning Operations on integer or logical data in GPRs; signed arithmetics trap on overflow Add, add immediate (all immediates are 16-bits); signed and unsigned Subtract, subtract immediate; signed and unsigned MULT, MULTU, DIV, DIVU Multiply and divide, signed and unsigned; operands must be floating-point registers; all operations take and yield 32-bit values AND, ANDI OR, ORI, XOP, XOPI LHI And, and immediate Or, or immediate, exclusive or, exclusive or immediate Load high immediate - loads upper half of register with immediate SLL, SRL, SRA, SLLI, SRLI, SRAI S, S I Shifts: both immediate(s I) and variable form(s ); shifts are shift left logical, right logical, right arithmetic Set conditional: " "may be LT, GT, LE, GE, EQ, NE

45 DLX Instruction Set opcode Control Instruction meaning Conditional branches and jumps; PC-relative or through register BEQZ, BNEZ Branch GPR equal/not equal to zero; 16-bit offset from PC BFPT, BFPF Test comparison bit in the FP status register and branch; 16-bit offset from PC J, JR Jumps: 26-bit offset from PC(J) or target in register(jr) JAL, JALR TRAP Jump and link: save PC+4 to R31, target is PC-relative(JAL) ot a register(jalr) Transfer to operating system at a vectored address RFE Return to user code from an exception; restore user code

46 DLX Instruction Set Floating point ADDD, ADDF SUBD, SUBF MULTD, MULTF DIVD, DIVF CVTF2D, CVTF2I, CVTD2F, CVTD2I, CVTI2F, CVTI2D D, F Floating-point operations on DP and SP formats Add DP, SP numbers Subtract DP, SP numbers Multiply DP, SP floating point Divide DP, SP floating point Convert instructions: CVTx2y converts from type x to type y, where x and y are one of I(Integer), D(Double precision), or F(Single precision). Both operands are in the FP registers. DP and SP compares: " " may be LT, GT, LE, GE, EQ, NE; set comparison bit in FP status register.

47 THANK YOU