Figure 1: Clocked I/O Transceiver

Transcription

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2 Figure 1: Clocked I/O Transceiver oe_dly2 oe_dly1 even_oe OE odd_oe dio1_oe (tristate_e) odd_oe D SET Q 126 dio1_out 126 CLR Q DIO1 dio1 Testbench Driver dio1_in D SET CLR Q Q dio2_in dio2_oe even_oe (tristate_e) dio2_out DIO2 dio2 Testbench Driver CLOCK OE odd odd_oe dio1_oe even_oe dio2_oe even turnaround time

3 Table 1: 768 FAST Channels mapped to 1148 pin DUT

4 DUT Card DAB Out RING ID # Con_Pin # DUT Sig Name Pin # Sig Name Pin # Sig # FPGA Pin # FPGA Sig Name 1 J1_1 DAB_P0_1 1 DAB_P0 4 0 AA28 IO_L1P_11 2 J1_3 DAB_N0_1 3 DAB_N0 4 0 AA29 IO_L1N_11 3 J1_2 DAB_P1_1 2 DAB_P1 3 1 W24 IO_L2P_11 4 J1_4 DAB_N1_1 4 DAB_N1 3 1 Y24 IO_L2N_11 5 J1_5 DAB_P2_1 5 DAB_P2 8 2 AB30 IO_L3P_11 6 J1_7 DAB_N2_1 7 DAB_N2 8 2 AA30 IO_L3N_11 7 J1_6 DAB_P3_1 6 DAB_P3 7 3 AE33 IO_L5P_11 8 J1_8 DAB_N3_1 8 DAB_N3 7 3 AE34 IO_L5N_11 9 J1_9 DAB_P4_1 9 DAB_P AC29 IO_L7P_11 10 J1_11 DAB_N4_1 11 DAB_N AC30 IO_L7N_11 11 J1_10 DAB_P5_1 10 DAB_P AD34 IO_L8P_CC_LC_11 12 J1_12 DAB_N5_1 12 DAB_N AC34 IO_L8N_CC_LC_11 13 J1_13 DAB_P6_1 13 DAB_P AE32 IO_L10P_11 14 J1_15 DAB_N6_1 15 DAB_N AD32 IO_L10N_11 15 J1_14 DAB_P7_1 14 DAB_P AC28 IO_L11P_11 16 J1_16 DAB_N7_1 16 DAB_N AB28 IO_L11N_11 17 J1_17 DAB_P8_1 17 DAB_P AF33 IO_L14P_11 18 J1_19 DAB_N8_1 19 DAB_N AF34 IO_L14N_11 19 J1_18 DAB_P9_1 18 DAB_P AE29 IO_L15P_11 20 J1_20 DAB_N9_1 20 DAB_N AD29 IO_L14N_11 21 J1_21 DAB_P10_1 21 DAB_P AA23 IO_L17P_11 22 J1_23 DAB_N10_1 23 DAB_N AA24 IO_L17N_11 23 J1_22 DAB_P11_1 22 DAB_P AD27 IO_L19P_11 24 J1_24 DAB_N11_1 24 DAB_N AC27 IO_L19N_11 25 J1_25 DAB_P12_1 25 DAB_P AG30 IO_L21P_11 26 J1_27 DAB_N12_1 27 DAB_N AG31 IO_L21N_11 27 J1_26 DAB_P13_1 26 DAB_P AF29 IO_L24P_CC_LC_11 28 J1_28 DAB_N13_1 28 DAB_N AF30 IO_L24N_CC_LC_11 29 J1_29 DAB_P14_1 29 DAB_P AK33 IO_L26P_11 30 J1_31 DAB_N14_1 31 DAB_N AK34 IO_L26N_11 31 J1_30 DAB_P15_1 30 DAB_P AM32 IO_L27P_11 32 J1_32 DAB_N15_1 32 DAB_N AM33 IO_L27N_11 33 J1_33 DAB_P16_1 33 DAB_P AB22 IO_L29P_11 34 J1_35 DAB_N16_1 35 DAB_N AB23 IO_L29N_11 35 J1_34 DAB_P17_1 34 DAB_P AL33 IO_L30P_11 36 J1_36 DAB_N17_1 36 DAB_N AL34 IO_L30N_11 37 J1_37 DAB_P18_1 37 DAB_P AJ30 IO_L32P_11 38 J1_39 DAB_N18_1 39 DAB_N AH30 IO_L32N_11 39 J1_38 DAB_P19_1 38 DAB_P AK29 IO_L1N_7 40 J1_40 DAB_N19_1 40 DAB_N AJ29 IO_L1P_7 41 J1_41 DAB_P20_1 41 DAB_P AF28 IO_L2N_7 42 J1_43 DAB_N20_1 43 DAB_N AE27 IO_L2P_7 43 J1_42 DAB_P21_1 42 DAB_P AF26 IO_L3N_7 44 J1_44 DAB_N21_1 44 DAB_N AE26 IO_L3P_7 45 J1_45 DAB_P22_1 45 DAB_P AG18 IO_L5P_GC_LC_4 46 J1_47 DAB_N22_1 47 DAB_N AG17 IO_L5N_GC_LC_4 47 J1_46 DAB_P23_1 46 DAB_P AP30 IO_L7N_7 48 J1_48 DAB_N23_1 48 DAB_N AN30 IO_L7P_7 49 J1_49 DAB_P24_1 49 DAB_P AG27 IO_L8N_CC_LC_7 50 J1_51 DAB_N24_1 51 DAB_N AG28 IO_L8P_CC_LC_7 51 J1_50 DAB_P25_1 50 DAB_P AM30 IO_L10N_7 52 J1_52 DAB_N25_1 52 DAB_N AL30 IO_L10P_7 53 J1_53 DAB_P26_1 53 DAB_P AP27 IO_L11N_7 54 J1_55 DAB_N26_1 55 DAB_N AN27 IO_L11P_7 55 J1_54 DAB_P27_1 54 DAB_P AL28 IO_L14N_7 56 J1_56 DAB_N27_1 56 DAB_N AL29 IO_L14P_7 57 J1_57 DAB_P28_1 57 DAB_P AP25 IO_L15N_7 58 J1_59 DAB_N28_1 59 DAB_N AP26 IO_L15P_7 59 J1_58 DAB_P29_1 58 DAB_P AP21 IO_L17N_7 60 J1_60 DAB_N29_1 60 DAB_N AP22 IO_L17P_7 61 J1_61 DAB_P30_1 61 DAB_P AK24 IO_L19N_7 62 J1_63 DAB_N30_1 63 DAB_N AJ24 IO_L19P_7 63 J1_62 DAB_P31_1 62 DAB_P AH19 IO_L3P_GC_LC_4 64 J1_64 DAB_N31_1 64 DAB_N AH18 IO_L3N_GC_LC_4 65 J1_65 DAB_P32_1 65 DAB_P AN28 IO_L24P_CC_LC_7 66 J1_67 DAB_N32_1 67 DAB_N AM28 IO_L24N_CC_LC_7 67 J1_66 DAB_P33_1 66 DAB_P AL26 IO_L26P_SM6_7 68 J1_68 DAB_N33_1 68 DAB_N AK26 IO_L26N_SM6_7 69 J1_69 DAB_P34_1 69 DAB_P AN22 IO_L27P_SM5_7 70 J1_71 DAB_N34_1 71 DAB_N AN23 IO_L27N_SM5_7 71 J1_70 DAB_P35_1 70 DAB_P AP24 IO_L29P_SM4_7 LMO PEG

5 Figure 2: Virtex 50 Pin Definition File

6 /* */ /* This is a pin definition file for the XCV TQ Transceiver device*/ /* */ /* */ /* Pin definitions and pin grouping. */ /* */ PIN b[46:0] BID 44,45,53,22,59,63,104,24,49,58,52,21,14, 60,133,4,32,29,48,23,20,13,76, 116,65,39,70,51,60,62,12,106,31,71,79,102,50, 61,47,69,11,56,80,67,105,5,81; PIN a[46:0] BID 137,139,121,138,101,119,113,7,88,89,131,97,141,124, 132,123,33,6,135,96,142,103,77,117, 66,27,85,130,98,122, 140,114,30,82,78,8,86,87,134,95,3,125,115,118,107, 127,28; PIN dir IN 139; PIN g_ IN 108; PIN CCLK IN 119; PIN M0 IN 40; PIN M2 IN 42; PIN M1 IN 38; PIN Done IN 80; PIN Prog IN 82; PIN TDO OUT 121; PINGROUP AllPins a[46:0],b[46:0];, dir,g_,cclk,m0,m1,m2,done,prog,tdo; PINGROUP APins PINGROUP BPins PINGROUP InPins PINGROUP VCCPins PINGROUP BndPins a[46:0]; b[46:0]; dir, g_; Prog,Done; a[46],a[45],a[44],a[43],a[42],a[41],a[40],a[39],a[38], a[37],a[36],a[35],a[34],a[33],a[32],a[31],a[30],a[29], a[28],a[27],a[26],a[25],a[24],a[23],a[22],a[21],a[20], a[19],a[17],a[16],a[15],a[14],a[13],a[12],a[11],a[10], a[9],a[8],a[7],a[6],a[5],a[4],a[2],a[1],a[0],b[47],b[46], b[45],b[44],b[43],b[42],b[41],b[40],b[39],b[38],b[37], b[36],b[33],b[32],b[31],b[30],b[29],b[28],b[27],b[26], b[25],b[24],b[23],b[22],b[21],b[20],b[19],b[18],b[17], b[16],b[15],b[14],b[13],b[12],b[11],b[10],b[9],b[8],b[7], b[6],b[5],b[4],b[3],b[2],b[1],b[0]; b[34] a[18] a[3] b[35] TDI TCK TMS Init Figure 3: FPGA Verilog Testbench Code

7 File: tb_generic.v Desc: Testbench for Xilinx LX60-ff1148 FPGA Date: Copyright (c) AtSpex Test ( ). All rights reserved `timescale 1ns/1ns module tb_generic (); Module Parameters For v4lx60ff1148_clocked_io.v DUT parameter FILENAME = "clocked_18x32.vec"; parameter COMB_MODE = 0; Set if outputs are combinatorial (not clocked) parameter NB = 18; number of busses parameter BW = 32; bus width, in bits parameter FBW = 32; first pair bus width, in bits For xc4vlx60ff1148_2x315.v DUT parameter FILENAME = "comb_2x47.vec"; parameter COMB_MODE = 1; Set if outputs are combinatorial (not clocked) parameter NB = 2; number of busses parameter BW = 315; bus width, in bits parameter FBW = 315; first pair bus width, in bits parameter NB = 2; parameter BW = 47; parameter FBW =47; number of busses bus width, in bits first pair bus width, in bits For xc4vlx60ff1148_20x32.v DUT parameter FILENAME = "comb_20x32.vec"; parameter COMB_MODE = 1; Set if outputs are combinatorial (not clocked) parameter NB = 20; number of busses parameter BW = 32; bus width, in bits parameter FBW = 27; first pair bus width, in bits Module Variables reg CLK, OE, DIR, RESET; wire [FBW-1:0] DIO1, DIO2; wire [BW-1:0] DIO3, DIO4, DIO5, DIO6, DIO7, DIO8, DIO9, DIO10, DIO11; Figure 4: Combinatorial Transceiver Verilog Module

8 File: xc4vlx60ff1148_2x55.v Desc: Parametized 245 Transceiver Author: DMO Date: Copyright (c) AtSpexLMO Test (2006). All rights reserved module xc4vlx60ff1148_2x315 ( DIR, OE, DIO1, DIO2 ); parameter DW = 47; If Data width=8, then default same as a TTL245 input DIR; direction, 1: DIO2=DIO1, 0: DIO1=DIO2 input OE; output enable, active low. 1: tristate I/O's inout [DW-1:0] DIO1, DIO2; Module Variables wire dir_in; wire oe_in; wire [DW-1:0] dio1_in, dio2_in; wire odd_oe, even_oe; Module Logic I/O buffers assign dir_in = DIR; assign oe_in = OE; assign dio1_in = DIO1; assign dio2_in = DIO2; assign DIO1 = odd_oe? dio2_in : {DW{1'bZ}}; assign DIO2 = even_oe? dio1_in : {DW{1'bZ}}; Output enables assign odd_oe =!dir_in &&!oe_in; assign even_oe = dir_in &&!oe_in; endmodule Figure 5: Automatic FPGA Test Vector Generation (Walking `1 s and 0 s)

9 D D D I I vec O I O O num E R : 0 1 LLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLH : 0 1 LHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHL : 0 1 LLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLH : 0 1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 4: 0 1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 5: LHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHL 6: LLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLH 7: LHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHL 8: LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 9: HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH 10: LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 11: LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLH 12: LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHL 13: LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLL 14: LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLL 15: LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLLL 16: LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLLLL 17: LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLLLLL 18: LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLLLLLL 19: LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLLLLLLL 20: LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLLLLLLLL 21: LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLLLLLLLLL 22: LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLLLLLLLLLL 23: LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLLLLLLLLLLL 24: LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLLLLLLLLLLLL 25: LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLLLLLLLLLLLLL 26: LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLLLLLLLLLLLLLL 27: LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLLLLLLLLLLLLLLL 28: LLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLLLLLLLLLLLLLLLL 29: LLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLLLLLLLLLLLLLLLLL 30: LLLLLLLLLLLLLLLLLLLLLLLLLLLHLLLLLLLLLLLLLLLLLLL 31: LLLLLLLLLLLLLLLLLLLLLLLLLLHLLLLLLLLLLLLLLLLLLLL 32: LLLLLLLLLLLLLLLLLLLLLLLLLHLLLLLLLLLLLLLLLLLLLLL 33: LLLLLLLLLLLLLLLLLLLLLLLLHLLLLLLLLLLLLLLLLLLLLLL 34: LLLLLLLLLLLLLLLLLLLLLLLHLLLLLLLLLLLLLLLLLLLLLLL 35: LLLLLLLLLLLLLLLLLLLLLLHLLLLLLLLLLLLLLLLLLLLLLLL 36: LLLLLLLLLLLLLLLLLLLLLHLLLLLLLLLLLLLLLLLLLLLLLLL 37: LLLLLLLLLLLLLLLLLLLLHLLLLLLLLLLLLLLLLLLLLLLLLLL 38: LLLLLLLLLLLLLLLLLLLHLLLLLLLLLLLLLLLLLLLLLLLLLLL 39: LLLLLLLLLLLLLLLLLLHLLLLLLLLLLLLLLLLLLLLLLLLLLLL 40: LLLLLLLLLLLLLLLLLHLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 41: LLLLLLLLLLLLLLLLHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 42: LLLLLLLLLLLLLLLHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 43: LLLLLLLLLLLLLLHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 44: LLLLLLLLLLLLLHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 45: LLLLLLLLLLLLHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 46: LLLLLLLLLLLHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 47: LLLLLLLLLLHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 48: LLLLLLLLLHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 49: LLLLLLLLHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 50: LLLLLLLHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 51: LLLLLLHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 52: LLLLLHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 53: LLLLHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 54: LLLHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 55: LLHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 56: LHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 57: HLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL

10 Figure 6: Xilinx Pad File Release i - par I.26 Copyright (c) Xilinx, Inc. All rights reserved. Thu May 11 12:13: INFO: The IO information is provided in three file formats as part of the Place and Route (PAR 1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a 2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This fil 3. The <design name>.pad file designed for parsing by customers. It uses the " " as a data fi INPUT FILE: xc4vlx60ff1148_2x315_map.ncd OUTPUT FILE: xc4vlx60ff1148_2x315_pad.txt PART TYPE: xcv50 SPEED GRADE: -6 PACKAGE: tq144 Pinout by Pin Number: Pin Number Signal Name Pin Usage Pin Name Direction IO Standard IO Bank Number Drive (ma) P1 VCCO 0 P2 TCK P3 DIO1<6> IOB IO BIDIR LVTTL 0 12 P4 DIO2<31> IOB IO BIDIR LVTTL 0 12 P5 DIO2<1> IOB IO_VREF_0 BIDIR LVTTL 0 12 P6 DIO1<29> IOB IO BIDIR LVTTL 0 12 P7 DIO1<39> IOB IO BIDIR LVTTL 0 12 P8 DIO1<11> IOB IO BIDIR LVTTL 0 12 P9 GND P10 VCCINT P11 DIO2<6> IOB IO BIDIR LVTTL 0 12 P12 DIO2<16> IOB IO BIDIR LVTTL 0 12 P13 DIO2<25> IOB IO_VREF_0 BIDIR LVTTL 0 12 P14 DIO2<34> IOB IO BIDIR LVTTL 0 12 P15 VCCINT P16 GCLKIOB GCK3 UNUSED 0 P17 VCCO 0 P18 GND P19 GCLKIOB GCK2 UNUSED 1 P20 DIO2<26> IOB IO BIDIR LVTTL 1 12 P21 DIO2<35> IOB IO BIDIR LVTTL 1 12 P22 DIO2<43> IOB IO_VREF_1 BIDIR LVTTL 1 12 P23 DIO2<27> IOB IO BIDIR LVTTL 1 12 P24 DIO2<39> IOB IO BIDIR LVTTL 1 12 P25 VCCINT P26 GND P27 DIO1<21> IOB IO BIDIR LVTTL 1 12 P28 DIO1<0> IOB IO BIDIR LVTTL 1 12 P29 DIO2<29> IOB IO BIDIR LVTTL 1 12 P30 DIO1<14> IOB IO_VREF_1 BIDIR LVTTL 1 12 P31 DIO2<14> IOB IO BIDIR LVTTL 1 12 P32 DIO2<30> IOB IO_WRITE BIDIR LVTTL 1 12

11 Figure 7: Test Source Template XC50 Virtex Xilinx chip #include "Cvir50.p2c" test #include "Cvir50.def" /* */ /* Default values will be applied to each test unless */ /* overridden by value assignment in the test. */ /* */ DPS_I_PClamp[1] = 30%; DPS_I_NClamp[1] = 5%; PMU_V_PCLAMP = 72%; PMU_V_NCLAMP = 66%; around 5 volts around -2volts AC_Vil = 0.0 V; AC_Vih = 3.0 V; AC_Vth = 1.5 V; AC_VLoad = 4.0 V; AC_Clk_Lead = ns; AC_Clk_Trail = ns; AC_Strobe = ns; /* */ /* Boundary Scan information */ /* */ loadbsdl("cvir50.bsm"); SCAN_CLK_FREQ = 5 MHZ; SCAN_VIL = 0.00 V; SCAN_VIH = 3.00 V; SCAN_VTH = 1.50 V; BSDL_TEST = no; /* */ /* Global declaration of DPS turn-on sequence. */ /* */ DPS_Turn_On_Sequence (DPS1,DPS2); /* */ /* Load VPU and SVF pattern files. */ /* */ LoadBit ("Cvir50.Rbt", PgmPat); LoadVPU ("Cvir50.cbv", VecPat); /* * * DC PARAMETRIC TEST CONDITIONS AND LIMITS * * */ /* CONTINUITY Test */ Continuity_Test: Continuity () { PMU_Force = -100 ua; PMU_Limit_Min = -2.0 V;

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