Description of Circuit. Fine Time Measurement : LVDS Receiver/Dribver. Production Readiness Review ATLAS Muon TDC (AMT)

Transcription

1 ATLAS Production Readiness Review ATLAS Muon TDC (AMT) 2 June 22@CERN Yasuo Arai (KEK) yasuo.arai@kek.jp Description of Circuit Fine Time Measurement : LVDS Receiver/Dribver

2 Block Diagram of the AMT-2

3 Asymmetric Ring Osc (8 stage example)

4 Tap Output Waveform (AMT-TEG) PLL OSC vs. Vg 25 f_pll(m Hz) MHz Sim (worst) Sim (typ) Sim (best) measurement Vg[V]

5 Layout of the Asym/ Ring OSC

6 Half Cycle Phase shift Can be Different Phase! (a) AMT-1 Control Voltage( VGN ) Ext. 4 MHz CLK Ring 8MHz Oscillator reset RESET* F1 F3 Phase Frequency Detector F2 LPF Cvg Int.4MHz CLK (b) AMT-2 Control Voltage( VGN ) Ext. 4 MHz CLK Ring 8MHz Oscillator reset F1 Phase Frequency Detector LPF Int.4MHz CLK Cvg Only 1 F/F RESET D Q F3 C D Q F2 C

7 PLL Stability σ = 15 PLL Osc. Ext. Clock Vdd[V] vs Fosc vs Vdd Operating Point 4 8 Fosc[MHz] 12

8 PLL Transition Characteristics (AMT-TEG)

9 Channel Buffer Load request register when all previous requests in register have been serviced Highest priority Channel to write into buffer Hardwired priority encoder Lowest priority Request register Ch. Ch. 1 Ch.22 Ch.23

10 Short Pulses Data Display 3ns : 3ns 3ns $a54a975 Head : TDC =5, EVID=74, BCID=$975 $45818e4 Combi: TDC =5, Ch=16, Width=$3, Time=$e4 $45818eb Combi: TDC =5, Ch=16, Width=$3, Time=$eb $c54a4 Trail: TDC =5, EVID=74, WordCount=4 $a54bd4f Head : TDC =5, EVID=75, BCID=$ d4f $45818e1 Combi: TDC =5, Ch=16, Width=$3, Time=$e1 $45818e8 Combi: TDC =5, Ch=16, Width=$3, Time=$e8 $c54b4 Trail: TDC =5, EVID=75, WordCount=4 :

11 Data Transfer Speed between Chan Buf and L1 Buf T Channel Buffer 5ns + 25ns x Nch Ch 1 Level 1 Buffer Ch 2 Ch N 6 Hit IntervalT [ns] 4 2 All hit accepted T = 5ns + 25ns x Nch Part of hit lost No. of Hit Channels N

12 Trigger Matching reject time reject reject offset coarse time Finds Hits in corresponding time window. Remove Old hits. mask window matching window time search window trigger time search limit trigger latency trigger Start pointer Mask window Read pointer Matching window Search window Write pointer data area mask data matched data

13 (a) full T recover T L1 Buffer Overflow Time Events (b) overflow flag Events with overflow data (c) 1 full T coarse time coarse time 1 recover T 1 full T coarse time bunch_count_offset event_count_offset count_roll_over bunch_count _reset 4MHz clock Load Bunch Count Event Count Load event_count _reset trigger Trigger FIFO 1 : : : Trigger FIFO Overflow 15 5 Trigger lost flag Trigger time tag Event number

14 Serial Output Serial clock Serial data stop start bit 31 bit 3 bit 1 bit parity stop start 36 bits/word LVDS output waveform at 4 Mbps Data 25ns Start Bit31 Bit3 Bit29 Strobe

15 CSR Registers & JTAG I/F DIO[11:] RA[4:] WR CS CSR Interface BSR ï ï ï CSR BSR BSR CSR1 ï ï Control registers ï CSR14 CSR15 (*) CSR16 CSR17 ï ï Status registers ï CSR21 TDI CORE reg CORE reg CORE reg M U X TDO Built In Self Test circuit Device ID register Bypass reg TMS TCK TRSTB TAP Controller Instruction register To ASD Control (*) (*) --- AMT-2 Only

16 ASD Control Function to set ASD registers through AMT JTAG port is added to reduce power and components on the mezzanine board. It is working correctly, but 1 additional register is inserted in JTAG chain by mistake because both chip has a TDO register. Scan Cell Scan Cell Scan Cell TDO reg data_out TDO reg

17 Low-Power LVDS Receiver 26 (3 in AMT-1) LVDS receivers are used in AMT-2. Previous design (Toshiba) uses large transistors in I/O buffer. Smaller input transistors are used in new design. Power Reduced : 15.5 mw -> 4 mw. Propagation Delay is also improved > 1.2 ma

18 Power Consumption Power Consumption of the AMT-2 becomes 15 mw/ch (total 36 mw). (AMT-1 is 33mW/ch, total 8 mw) 4 3 AMT-1-18mW 2 AMT-2 1