Differences Between HDL Compiler (Presto Verilog) and the Original HDL Compiler C

Transcription

1 C Differences Between HDL Compiler (Presto Verilog) and the Original HDL Compiler C This appix describes new features and the differences between HDL Compiler (Presto Verilog) and the original HDL Compiler, in the following sections: Verilog 2001 Features Other New Features and Enhancements Features and Variables Not Supported Deprecated Features Changes From the Original HDL Compiler Tool Implementation Differences Public Variables for HDL Compiler (Presto Verilog) / C-1

2 Verilog 2001 Features Table C-1 lists the Verilog 2001 features implemented by HDL Compiler (Presto Verilog). For additional information on these features, see IEEE Std For information about other new features and enhancements, see Table C-3 on page C-35. Table C-1 Feature Verilog 2001 Features Description As of Version Constant function support Allows parameter and local parameter assignments that contain calls to constant functions. Verilog 2001 constant functions are supported on the right-hand side of a parameter assignment, as shown below. module ram (input_bus); parameter SIZE = 1024; parameter word_width = clogb2(size); input [word_width -1 : 0] input_bus; function integer clogb2 (input [31:0] depth); begin for (clogb2=0; depth>0; clogb2=clogb2+1) depth = depth >> 1; function... The following usage is not supported: parameter mem_size = 256; input [my_log2(mem_size)-1:0] address_bus; // error... function integer my_log2 (input [31:0] size);... / C-2

3 Table C-1 Feature Verilog 2001 Features (Continued) Description Local parameter support Presto Verilog fully supports the localparam construct. As of Version No Verilog 2001 features were added. As of Version No Verilog 2001 features were added. As of Version Generate statement translate_off and translate_on SYNTHESIS macro For description and example, see generate Statements on page C-7. The //synopsys translate_off directive and the //synopsys translate_on directive are deprecated; their function is replaced with the SYNTHESIS macro and the appropriate conditional directives (`ifdef, `ifndef, `else, `if). For details, see Deprecated Features on page C-58. To susp translation of the source code for synthesis, Presto Verilog supports the macro SYNTHESIS. For details, see Standard Macros (SYNTHESIS, PRESTO, VERILOG_2001, and VERILOG_1995) on page 7-6 and Deprecated Features on page C-58. / C-3

4 Table C-1 Feature Verilog 2001 Features (Continued) Description Implicit net declarations for continuous assignments `line directive If an identifier appears on the left-hand side of a continuous assignment statement, and that identifier has not been declared previously, then Presto assumes an implicit scalar net declaration. For example, the following two module declarations are equivalent: module m1 (output out, input in); wire t ; assign t = in ; assign out = t ; module m2 (output out, input in) ; assign t = in ; assign out = t ; Notice that the explicit wire declaration is no longer needed. The `line directives are inserted by preprocessing tools to preserve information for other tools about the line numbers and file names of the original source files, so that diagnostic messages can still refer to them. As of Version Expanded ANSI-C-style port declarations See Full ANSI Style Declaration Support on page C-8. As of Version Casting operators Allows sign control; preserves the value of the argument. Casting operators are $signed() and $unsigned(). See See Controlling Signs With Casting Operators on page C-19. / C-4

5 Table C-1 Feature Verilog 2001 Features (Continued) Description Parameter passing by name (IEEE ) Allows setting parameters on subdesigns by parameter name; it is not sensitive to number or declaration order of parameters. You only need to specify the subset of parameters you want to set. For example, assuming module m1 (x, y); parameter p = 7; parameter q = 8; parameter r = 9; then m1 #(.r(3),.p(1)) u1 (x, y) is equivalent to m1 #(1,8,3) u1 (x, y); Implicit event expression list (IEEE 9.7.5) ANSI-C-style port declaration (IEEE ) Makes always blocks sensitive to any variable read. Syntax: (@*) The event expression does not need to list net and variable identifiers; they are automatically added to the event expression. If you do not use this syntax and the tool finds an incomplete sensitivity list, the tool will issue a warning. You can list types when declaring port values for example, module t (input [1:0] in, output [2:0] out). For additional examples, see Full ANSI Style Declaration Support on page C-8. As of Version Signed/unsigned parameters (IEEE 3.11) See Signed Quantities on page C-14. / C-5

6 Table C-1 Feature Verilog 2001 Features (Continued) Description Signed/unsigned nets and registers (IEEE 3.2, 4.3) Signed/unsigned sized and based constants (IEEE 3.2) New array functionality Multidimensional arrays (IEEE ) Arrays of nets (IEEE 3.10) New operators Part select addressing ([+:] and [-:] operators) (IEEE 4.2.1) Power operator (**) (IEEE 4.1.5) Arithmetic shift operators (<<< and >>>) (IEEE ) Sized parameters (IEEE ) New compiler directives `ifndef, `elsif, `undef (IEEE 19.4,19.3.2) New compiler directives `ifdef VERILOG_2001 and `ifdef VERILOG_1995 See Signed Quantities on page C-14. See Signed Quantities on page C-14. See New Array Functionality on page C-11. See New Operators on page C-27. See New Operators on page C-27. See New Operators on page C-27. See New Operators on page C-27. A bit range can be used when declaring parameters. See See New Operators on page C-27. See See Standard Macros (SYNTHESIS, PRESTO, VERILOG_2001, and VERILOG_1995) on page 7-6. The dc_shell variable for enabling/disabling Verilog 2001 mode is: hdlin_vrlg_std. Set hdlin_vrlg_std = 1995 to disable Verilog 2001 features. Default is hdlin_vrlg_std = 2001, which enables Verilog 2001 features. / C-6

7 Table C-1 Feature Verilog 2001 Features (Continued) Description Comma-separated sensitivity lists (IEEE and 9.7.4) Signals in the sensitivity list can be separated with commas. generate Statements The generate statement is an IEEE Verilog construct that makes the language easier to use by simplifying the RTL code needed to repeat a group of concurrent statements or component instantiations. In Example C-1, a generate loop is constructed around a flip-flop and executed three times making three flip-flops. Example C-1 generate statement module gen (clk, din, dout); parameter N = 3; input clk; input [N-1:0] din; output [N-1:0] dout; reg [N-1:0] dout; genvar i; generate for (i = 0; i < N; i = i+1) begin : my_generate_loop (posedge clk) dout[i] <= din[i]; generate HDL Compiler (Presto Verilog) builds three sequential generic elements SEQGENs which, when compiled, are implemented as shown in Figure C-2. / C-7

8 For additional information, see the IEEE Std , IEEE Standard Verilog Hardware Description Language. Figure C-1 generate Statement Compiled Gates Full ANSI Style Declaration Support HDL Compiler supports full ANSI style declarations as shown in Example C-2. Example C-2 Supported ANSI Style Declarations module m1 (input [3:0]a, output [3:0]b); module m2 (input [3:0]a, output reg signed [3:0]b); function [3:0] f (input [3:0] x); begin f = x; function begin / C-8

9 b = f(a); module m3 (input [3:0]a, output reg [3:0]b); task t (input [3:0] x); begin b = x; task begin t(a); module m4 (input [7:0] a, output reg [7:0] b); defparam t.testb = 8, t.testa=1, t.width=1; test #(8) t (a, b); module test #(parameter WIDTH=4, testa=5, testb=6) ( input [WIDTH-1:0] in, output[width-1:0] out); // Instead of declaring parameters inside the body of the module, // the ANSI style allows you to declare parameters this way. module m5 (input signed [7:0]a, output signed [7:0]b); module m6 (input signed a, output signed b); module m7 (input wire signed [7:0]a, output wire signed [7:0]b); / C-9

10 module m8 (input tri signed [7:0]a, output tri b); module m9 (input tri [7:0]a, output tri signed b); module m10 (input [3:0]a, output reg signed [3:0]b); function [3:0] f (input signed [3:0] x); begin f = x; function begin b = f(a); module m11 (input [3:0]a, output reg [3:0]b); task t (input signed [3:0] x, output reg signed [3:0] y); begin y = x; task begin t(a,b); / C-10

11 New Array Functionality HDL Compiler (Presto Verilog) supports multidimensional arrays of any variable or net data type. This added functionality is shown in Examples C-3 through C-6. / C-11

12 Example C-3 Multidimensional Arrays: Code and Gates module m (a, z); input [7:0] a; output z; reg t [0:3][0:7]; integer i, j; integer k; begin for (j = 0; j < 8; j = j + 1) begin t[0][j] = a[j]; for (i = 1; i < 4; i = i + 1) begin k = 1 << (3-i); for (j = 0; j < k; j = j + 1) begin t[i][j] = t[i-1][2*j] ^ t[i-1][2*j+1]; assign z = t[3][0]; a [0:7] / C-12

13 Example C-4 Arrays of Nets: Code and Gates module m (a, z); input [0:3] a; output z; wire x [0:2] ; assign x[0] = a[0] ^ a[1]; assign x[1] = a[2] ^ a[3]; assign x[2] = x[0] ^ x[1]; assign z = x[2]; Example C-5 Multidimensional Array Variable Subscripting reg [7:0] X [0:7][0:7][0:7]; assign out = X[a][b][c][d+:4]; Verilog 2001 allows more than one level of subscripting on a variable, without using a temporary variable. Example C-6 Multidimensional Array module test(in, en, out, addr_in, addr_out_reg, addr_out_bit, clk); input [7:0] in; input en, clk; input [2:0] addr_in, addr_out_reg, addr_out_bit; reg [7:0] MEM [0:7]; output out; assign out = MEM[addr_out_reg][addr_out_bit]; clk) if (en) MEM[addr_in] = in; / C-13

14 Signed Quantities HDL Compiler (Presto Verilog) supports signed arithmetic extensions. Function returns and data types reg and net can be declared as signed. This added functionality is shown in Examples C-7 through C-12. Example C-7 Signed I/O Ports: Code and Circuit // This results in a // sign-extension. // (that is, z[0] should be // connected to a[0]) module m1 (a, z); input signed [0:3] a; output signed [0:4] z; assign z = a; a [0:3] a [0] z [0:1] a [1] z [2] a [2] z [3] a [3] z [4] z [0:4] / C-14

15 Example C-8 Signed Constants: Code and Gates // Because 3 sb111 is signed, // a signed adder is used; z[0] will // not be logic 0. ADD_TC_OP denotes // a 2 s complement, that is, a // signed adder. module m2 (a, z); input signed [0:2] a; output [0:4] z; assign z = a + 3 sb111; ADD_TC_OP Example C-9 Signed Registers: Code and Gates //Because 4 sd5 is signed, a //signed comparator (LT_TC_OP) //is used. module m3 (a, z); input [0:3] a; output z; reg signed [0:3] x; reg z; always begin x = a; z = x < 4 sd5; LT_TC_OP / C-15

16 Example C-10 Signed Types: Code and Gates //Because in1, in2, and out are // signed, a signed multiplier // (MULT_TC_OP_8_8_8) //is used module m4 (in1, in2, out); input signed [7:0] in1, in2; output signed [7:0] out; assign out = in1 * in2; in1[7:0] in2[7:0] MULT_TC_OP_8_8_8 out[7:0] Example C-11 Signed Nets: Code and Gates // This results in a signed subtracter //(SUB_TC_OP). module m5 (a, b, z); input [1:0] a, b; output [2:0] z; wire signed [1:0] x = a; wire signed [1:0] y = b; assign z = x - y; a[0] a[1] b[0] b[1] sub z[0] z[1] z[2] SUB_TC_OP / C-16

17 Example C-12 Signed Values //Because 4 sd5 is signed, a //signed comparator (LT_TC_OP) //is used. module m6 (a, z); input [3:0] a; output z; reg signed [3:0] x; wire z; begin a[0] a[1] a[2] a[3] +v < z LT_TC_OP x = a; assign z = x < -4 sd5; Verilog 2001 adds the signed keyword in declarations: reg signed [7:0] x; It also adds a new feature for signed, sized constants. For example, 8'sb is an 8-bit signed quantity representing -1. If you are assigning it to a variable that is 8 bits or less, 8'sb is the same as the unsigned 8'b A behavior difference arises when the variable being assigned to is larger than the constant. This difference occurs because signed quantities are exted with the high-order bit of the constant, whereas unsigned quantities are exted with 0's. When used in expressions, the sign of the constant helps determine whether the operation is performed as signed or unsigned. HDL Compiler (Presto Verilog) enables signed types by default; to disable signed types, set hdlin_unsigned_integers to true. / C-17

18 Note: When synthesizing expressions containing variables declared as integer, the original HDL Compiler did not consider the integer type to be a hardware data type and generated unsigned components; HDL Compiler (Presto Verilog) synthesizes the signed versions of arithmetic operators for expressions whose type is integer. HDL Compiler (Presto Verilog) behavior conforms more closely to the IEEE Standard. Any designs that use the integer type for expressions that cannot be completely evaluated at the time of elaboration may be affected by this change. However, computations that are known constants at compile time are not affected (for example, calculation of for loop bounds). You should evaluate whether this change will affect your design. To obtain the original behavior, set hdlin_unsigned_integers to true. Note that if you use the keyword signed, any signed constant in your code, or explicit type casting between signed and unsigned types, HDL Compiler (Presto Verilog) issues a warning and forces hdlin_unsigned_integers back to false. Comparisons With Signed Types Verilog sign rules are tricky. All inputs to an expression must be signed to obtain a signed operator. If one is signed and one unsigned, then both are treated as unsigned. Any unsigned quantity in an expression makes the whole expression unsigned and the result doesn t dep on the sign of left-hand side. Some expressions always produce an unsigned result; these include bit and part-select and concatenation. See IEEE P1364/P5 Section / C-18

19 Example C-13 You need to control the sign of the inputs yourself if you want to compare a signed quantity against an unsigned one. The same is true for other kinds of expressions. See Example C-14 and Example C-13. Unsigned Comparison Results When Signs Are Mismatched module m8 (in1, in2, lt); // in1 is signed but in2 is unsigned input signed [7:0] in1; input [7:0] in2; output lt; wire uns_lt, uns_in1_lt_64; /* comparison is unsigned because of the sign mismatch, in1 is signed but in2 is unsigned */ assign uns_lt = in1 < in2; /* Unsigned constant causes unsigned comparison; so negative values of in1 would compare as larger than 8 d64 */ assign uns_in1_lt_64 = in1 < 8'd64; assign lt = uns_lt + uns_in1_lt_64; Example C-14 Signed Values module m7 (in1, in2, lt, in1_lt_64); input signed [7:0] in1, in2; // two signed inputs output lt, in1_lt_64; assign lt = in1 < in2; // comparison is signed // using a signed constant results in a signed comparison assign in1_lt_64 = in1 < 8'sd64; Controlling Signs With Casting Operators Use the Verilog 2001 casting operators, $signed() and $unsigned(), to convert an unsigned expression to a signed expression. In Example C-15, the casting operator is used to obtain a signed comparator. Note that simply marking an expression as signed might / C-19

20 Example C-15 give undesirable results because the unsigned value might be interpreted as a negative number. To avoid this problem, zero-ext unsigned quantities, as shown in Example C-15. Casting Operators module m9 (in1, in2, lt); input signed [7:0] in1; input [7:0] in2; output lt; assign lt = in1 < $signed ({1 b0, in2}); //Cast to get signed comparator. //Zero-ext to preserve interpretation of unsigned value as positive number. Sign Conversion Warnings When reading a design that contains signed expressions and assignments, HDL Compiler warns you when there are sign mismatches by outputting a VER-318 warning. This warning can be disabled by setting hdlin_warn_implicit_sign_conv to false. Default is true. Note that beginning with the U release, HDL Compiler no longer issues a signed/unsigned conversion warning (VER-318) if all of the following conditions are true: The conversion is necessary only for constants in the expression. The width of the constant would not change as a result of the conversion. The most significant bit (MSB) of the constant is zero (nonnegative). Consider Example C-16. Here, even though Presto Verilog implicitly converts the type of the constant 1, which is by default signed, to unsigned, the VER-318 warning is not issued because the above three conditions are true. / C-20

21 Example C-16 input [3:0] a, b; output [5:0] z; assign z = a + b + 1; Mixed Unsigned and Signed Types In releases before U , HDL Compiler would always issue a (VER-318) unsigned/signed warning if an arithmetic expression contained mixed unsigned and signed types, including constants, because implicit type conversion is required to make the expression compatible with the type being assigned. Note that integer constants are treated as signed types by default. The VER-319 warning indicates that the compiler has implicitly converted An unsigned expression to a signed expression A signed expression to an unsigned expression or it has assigned An unsigned right-hand side to a signed left-hand side A signed right-hand side to an unsigned left-hand side For example, in this code reg signed [3:0] a; reg [7:0] c; a = 4'sb1010; c = a+7'b ; / C-21

22 an implicit signed/unsigned conversion occurs the signed operand a is converted to an unsigned value and the VER-318 warning "signed to unsigned conversion occurs" is issued. Note that a will not be sign-exted. This behavior is in accordance with the Verilog 2001 standard. When explicit type casting is used, conversion warnings are not issued. For example, in the code above, to force a to be unsigned, you assign c as follows: c = $unsigned(a)+7'b ; no warning is issued. Consider the following assignment: reg [7:0] a; a = 4'sb1010; A VER-318 warning "signed to unsigned assignment occurs" is issued when this code is read. Note that although the left side is unsigned, the right side will still be sign-exted in other words, a will have the value 8'b after the assignment. If there is more than one implicit conversion in a line, such as the expression assigned to c in the example below, only one warning message will be issued. reg signed [3:0] a; reg signed [3:0] b; reg signed [7:0] c; c = a+4'b0101+(b*3'b101); / C-22

23 Example C-17 Note that a and b are converted to unsigned values and because the whole right side is unsigned, assigning it to c will also result in the warning. Note that integers are considered to have signed values and will generate VER-318 warnings accordingly. The code below uses integers and will issue VER-318 warnings. module m17(y, count1, z); input [3:0] y, count1;output [3:0] z; reg [3:0] x, z, count; (y, count1) begin x = 2; count = count1; while (x < 15) begin count = count + 1; x = x + 1; z = count; The code in Example C-17 generates eight VER-318 warnings. Modules m1 Through m9 1 module m1 (a, z); 2 input signed [0:3] a; 3 output signed [0:4] z; 4 assign z = a; module m2 (a, z); 9 input signed [0:2] a; 10 output [0:4] z; 11 assign z = a + 3'sb111; module m3 (a, z); / C-23

24 16 input [0:3] a; 17 output z; 18 reg signed [0:3] x; 19 reg z; 20 always begin 21 x = a; 22 z = x < 4'sd5; /* note that x is signed and compared to 4'sd5, which is also signed, but the result of the comparison is put into z, an unsigned reg. This appears to be a sign mismatch; however, no VER-318 warning is issued for this line because comparison results are always considered unsigned. This is true for all relational operators. */ module m4 (in1, in2, out); 28 input signed [7:0] in1, in2; 29 output signed [7:0] out; 30 assign out = in1 * in2; module m5 (a, b, z); 35 input [1:0] a, b; 36 output [2:0] z; 37 wire signed [1:0] x = a; 38 wire signed [1:0] y = b; 39 assign z = x - y; module m6 (a, z); 44 input [3:0] a; 45 output z; 46 reg signed [3:0] x; 47 wire z; 48 begin 49 x = a; assign z = x < -4'sd5; module m7 (in1, in2, lt, in1_lt_64); 55 input signed [7:0] in1, in2; // two signed inputs 56 output lt, in1_lt_64; 57 assign lt = in1 < in2; // comparison is signed // using a signed constant results in a signed comparison 60 / C-24

25 61 assign in1_lt_64 = in1 < 8'sd64; module m8 (in1, in2, lt); // in1 is signed but in2 is unsigned input signed [7:0] in1; 70 input [7:0] in2; 71 output lt; 72 wire uns_lt, uns_in1_lt_64; /* comparison is unsigned because of the sign mismatch; in1 is signed but in2 is unsigned */ assign uns_lt = in1 < in2; /* Unsigned constant causes unsigned comparison; so negative values of in1 would compare as larger than 8'd64 */ assign uns_in1_lt_64 = in1 < 8'd64; 81 assign lt = uns_lt + uns_in1_lt_64; module m9 (in1, in2, lt); 88 input signed [7:0] in1; 89 input [7:0] in2; 90 output lt; 91 assign lt = in1 < $signed ({1'b0, in2}); Example C-18 The eight VER-318 warnings generated by the code in Example C-17 are shown in Example C-18. Sign Conversion Warnings for m1 Through m9 Warning: /usr/00budgeting/vhdl-mr/warn-sign.v:11: signed to unsigned assignment occurs. (VER-318) Warning: /usr/00budgeting/vhdl-mr/warn-sign.v:21: unsigned to signed assignment occurs. (VER-318) / C-25

26 Warning: /usr/00budgeting/vhdl-mr/warn-sign.v:21: a is read but does not appear in the sensitivity list of this always block. (ELAB-292) Warning: /usr/00budgeting/vhdl-mr/warn-sign.v:37: unsigned to signed assignment occurs. (VER-318) Warning: /usr/00budgeting/vhdl-mr/warn-sign.v:38: unsigned to signed assignment occurs. (VER-318) Warning: /usr/00budgeting/vhdl-mr/warn-sign.v:39: signed to unsigned assignment occurs. (VER-318) Warning: /usr/00budgeting/vhdl-mr/warn-sign.v:49: unsigned to signed assignment occurs. (VER-318) Warning: /usr/00budgeting/vhdl-mr/warn-sign.v:76: signed to unsigned conversion occurs. (VER-318) Warning: /usr/00budgeting/vhdl-mr/warn-sign.v:80: signed to unsigned conversion occurs. (VER-318) Presto compilation completed successfully. Current design is now /usr/00budgeting/vhdl-mr/m1.db:m1 m1 m2 m3 m4 m5 m6 m7 m8 m9 Table C-2 describes what caused the warnings listed in Example C-18. Table C-2 Module Sign Mismatch Warnings (VER-318) Cause of warning m1, m4, and m7 These modules do not have any sign conversion warnings because the signs are consistently applied. m9 m2 This module does not issue a VER-318 warning because, even though in1 and in2 are sign mismatched, the casting operator is used to force the sign on in2. When a casting operator is used, no warning is returned when sign conversion occurs. In this module, a is signed and added to 3 sb111 which is signed and has a value of -1. However, z is not signed so the value of the expression on the right, which is signed, will be converted to unsigned when assigned to z. The VER-318 warning signed to unsigned assignment occurs is issued. / C-26

27 Table C-2 Module m3 Sign Mismatch Warnings (VER-318) (Continued) Cause of warning In this module, a is unsigned but put into the signed reg x. Here a will be converted to signed and a VER-318 warning unsigned to signed assignment occurs is issued. Note that in line 22 (z = x < 4'sd5) x is signed and compared to 4'sd5, which is also signed, but the result of the comparison is put into z, an unsigned reg. This appears to be a sign mismatch; however, no VER-318 warning is issued for this line because comparison results are always considered unsigned. This is true for all relational operators. m5 In this module, a and b are unsigned but they are assigned to x and y, which are signed. Two VER-318 warnings unsigned to signed assignment occurs are issued. In addition, y is subtracted from x and assigned to z, which is unsigned. Here the VER-318 warning signed to unsigned assignment occurs is also issued. m6 m8 In this module, a is unsigned but put into the signed register x. The VER-318 warning unsigned to signed assignment occurs is issued. In this module, in1 is signed and compared with in2, which is unsigned, and 8 d64, which is an unsigned value. For each expression, the VER-318 warning signed to unsigned conversion occurs is issued. New Operators New operator support is described in the following three sections: Variable Part-Select Overview Power Operator (**) Arithmetic Shift Operators (<<< and >>>) / C-27

28 Part-Select Addressing Operators ([+:] and [-:]) Verilog 2001 introduces variable part-select operators. These operators allow you to use variables to select a group of bits from a vector. In some designs, coding with part-select operators improves elaboration time and memory usage. For more information on coding recommations, see Use Variable Part-Select Operators to Improve Elaboration Time and Memory Usage on page This section contains the following: Variable Part-Select Overview Example Ascing Array and +: Example Ascing Array and -: Example Descing Array and -: Example Descing Array and +: Variable Part-Select Overview. A Verilog 1995 part-select operator requires that both upper and lower indexes be constant: a[2:3] or a[value1:value2]. The variable part-select operator permits selection of a fixed-width group of bits at a variable base address and takes the following form: [base_expr +: width_expr] for a positive offset [base_expr -: width_expr] for a negative offset The syntax specifies a variable base address and a known constant number of bits to be extracted. The base address is always written on the left, regardless of the declared direction of the array. The / C-28

29 language allows variable part-select on the left-hand side (LHS) and the right-hand side (RHS) of an expression. All of the following expressions are allowed: data_out = array_expn[index_var +: 3] (part select is on the right-hand side) data_out = array_expn[index_var -: 3] (part select is on the right-hand side) array_expn[index_var +: 3] = data_in (part select is on the left-hand side) array_expn[index_var -: 3] = data_in (part select is on the left-hand side) The table below shows examples of Verilog 2001 syntax and the equivalent Verilog 1995 syntax. Verilog 2001 syntax a[x +: 3] for a descing array a[x -: 3] for a descing array a[x +: 3] for an ascing array a[x -: 3] for an ascing array Equivalent Verilog 1995 syntax { a[x+2], a[x+1], a[x] } a[x+2 : x] { a[x], a[x-1], a[x-2] } a[x : x-2] { a[x], a[x+1], a[x+2] } a[x : x+2] { a[x-2], a[x-1], a[x] } a[x-2 : x] The original HDL Compiler tool allows nonconstant part-selects if the width is constant; HDL Compiler (Presto Verilog) permits only the new syntax. / C-29

30 Example Ascing Array and +:. The code below uses the +: operator to select bits from Ascing_Array. reg [0:7] Ascing_Array;... Data_Out = Ascing_Array[Index_Var +: 3]; The value of Index_Var determines the starting point for the bits selected. The bits selected are shown below as a function of Index_Var. Ascing_Array [ ] Index_Var = 0 Index_Var = 1 Index_Var = 2 Index_Var = 3 Index_Var = 4 Index_Var = 5 Index_Var = 6 not valid, synthesis/simulation mismatch; see note below. Index_Var = 7 not valid, synthesis/simulation mismatch: see note below. Note: Ascing_Array[Index_Var +: 3] is functionally equivalent to the following non-computable part-select: Ascing_Array[Index_Var : Index_Var + 2] Non-computable part-selects are not supported by the Verilog language. Ascing_Array[7 +:3] corresponds to elements Ascing_Array[7 : 9] but elements Ascing_Array[8] and Ascing_Array[9] do not exist. A variable part-select must always compute to a valid index, otherwise there will be a synthesis elaborate error and a run-time simulation error. / C-30

31 Example Ascing Array and -:. The code below uses the -: operator to select bits from Ascing_Array. reg [0:7] Ascing_Array;... Data_Out = Ascing_Array[Index_Var -: 3]; The value of Index_Var determines the starting point for the bits selected. The bits selected are shown below as a function of Index_Var. Ascing_Array [ ] Index_Var = 0 not valid, synthesis/simulation mismatch Index_Var = 1 not valid, synthesis/simulation mismatch Index_Var = 2 Index_Var = 3 Index_Var = 4 Index_Var = 5 Index_Var = 6 Index_Var = 7 Ascing_Array[Index_Var -: 3] is functionally equivalent to the following non-computable part-select: Ascing_Array[Index_Var - 2 : Index_Var] Example Descing Array and -:. The code below uses the -: operator to select bits from Descing_Array. reg [7:0] Descing_Array;... Data_Out = Descing_Array[Index_Var -: 3]; / C-31

32 The value of Index_Var determines the starting point for the bits selected. The bits selected are shown below as a function of Index_Var. Descing_Array [ ] Index_Var = 0 not valid, synthesis/simulation mismatch Index_Var = 1 not valid, synthesis/simulation mismatch Index_Var = 2 Index_Var = 3 Index_Var = 4 Index_Var = 5 Index_Var = 6 Index_Var = 7 Descing_Array[Index_Var -: 3] is functionally equivalent to the following non-computable part-select: Descing_Array[Index_Var : Index_Var - 2] Example Descing Array and +:. The code below uses the +: operator to select bits from Descing_Array. reg [7:0] Descing_Array;... Data_Out = Descing_Array[Index_Var +: 3]; / C-32

33 The value of Index_Var determines the starting point for the bits selected. The bits selected are shown below as a function of Index_Var. Descing_Array [ ] Index_Var = 0 Index_Var = 1 Index_Var = 2 Index_Var = 3 Index_Var = 4 Index_Var = 5 Index_Var = 6 not valid, synthesis/simulation mismatch Index_Var = 7 not valid, synthesis/simulation mismatch Descing_Array[Index_Var +: 3] is functionally equivalent to the following non-computable part-select: Descing_Array[Index_Var + 2 : Index_Var] Non-computable part-selects are not supported by the Verilog language. Descing_Array[7 +:3] corresponds to elements Descing_Array[9 : 7] but elements Descing_Array[9] and Descing_Array[8] do not exist. A variable part-select must always compute to a valid index, otherwise there will be a synthesis elaborate error and a run-time simulation error. Power Operator (**) This operator performs y x, as shown in Example C-19. Example C-19 Power Operators module m (a, z); / C-33

34 input [3:0] a; output [7:0] x, y, z; assign z = 2 ** a; assign x = a ** 2; assign y = b ** c // where b and c are constants Arithmetic Shift Operators (<<< and >>>) The arithmetic shift operators allow you to shift an expression and still maintain the sign of a value, as shown in Example C-20. When the type of the result is signed, the arithmetic shift operator (>>>) shifts in the sign bit; otherwise, it shifts in zeros. Example C-20 Shift Operator Code and Gates module s1 (A, S, Q); input signed [3:0] A; input [1:0] S; output [3:0] Q; reg [3:0] Q; or S) begin o o o o // arithmetic shift right, //shifts in sign-bit from left o Q = A >>> S; / C-34

35 Other New Features and Enhancements HDL Compiler (Presto Verilog) offers Verilog 2001 features see Table C-1 on page C-2 and other new features and enhancements listed in Table C-3. Table C-3 Other HDL Compiler (Presto Verilog) Features HDL Compiler (Presto Verilog) New or enhanced features Description As of Version Blocking and non-blocking assignments Net preservation hdlin_check_no_latch By default, you cannot make blocking and non-blocking assignments to the same variable. In previous versions, this was possible. Unloaded nets can be preserved. For details, see Internal Net Preservation on page The variable hdlin_check_no_latch is supported. (STAR ) As of Version No features were added. As of Version Variables added: hdlin_seqmap_async_search_ depth hdlin_seqmap_sync_search_ depth The hdlin_seqmap_search_depth variable is obsolete and has been replaced with the hdlin_seqmap_async_search_depth variable and the hdlin_seqmap_sync_search_depth variable Version Sequential cell preservation For details, see Sequential Cell Preservation on page / C-35

36 Table C-3 Other HDL Compiler (Presto Verilog) Features (Continued) HDL Compiler (Presto Verilog) New or enhanced features map_to_module enhancement translate_off and translate_on Description map_to_module supports tasks as well as functions. For details, see map_to_module and return_port_name on page The //synopsys translate_off directive and the //synopsys translate_on directive are deprecated. For details, see Deprecated Features on page C-58. Version Automatic detection of input file type DC Ultra datapath optimization Finite State Machines (FSMs) verification Automatic detection of finite state machines (FSMs) HDL Compiler can automatically detect if your design is a gate-level netlist or an RTL design and use the best reader for your design. For details, see Starting HDL Compiler on page 1-4. DC Ultra enables datapath extraction after timing-driven resource sharing and explores various datapath/ resource-sharing options during compile. For details, see Datapaths on page As of release , enumerated types used in FSMs are recognized by both Formality and DC Ultra (compare_design -fsm and compile -verify) and the typical FSM coding style, shown in Example 4-46 on page 4-40, can be verified by Formality. Automatic detection of finite state machines (FSMs) In the release, HDL Compiler introduces automatic detection and inference of finite state machines. Combined with the new automatic FSM extraction feature in Design Compiler, FSM synthesis is simplified to just reading and compiling your code. For details, see Finite State Machines on page / C-36

37 Table C-3 Other HDL Compiler (Presto Verilog) Features (Continued) HDL Compiler (Presto Verilog) New or enhanced features Description As of Version Displays synthesis progress Models simulator behavior Improved logic for left side array references Expanded MUX-OP inference Sharing array references Resource-sharing directives Can preserve the value of procedure-local variables across calls by inferring latches Reports on synthesis progress. This is helpful for printing out compile-time computations on parameters, or the number of times a loop executes. Uses the system task - $display. See Using $display During RTL Elaboration on page C-52. Simulates simulator behavior by allowing writing to out-of-bounds array locations using the new variable hdlin_dyn_array_bounds_check. See Writing to Out-of-Bounds Array Locations on page C-50. See Improved Logic for Array Reference on the Left Side on page C-53. Get MUX-OP s for both case and if statements and right side variable array reference x[a]. See Improved MUX_OP inference on page C-53. See Sharing Array References on page C-54. Manual control of resource sharing and implementation selection; these directives were not available in the new HDL Compiler (Presto Verilog) version See Sharing Using hlo_resource_allocation on page 6-7. New variable hdlin_infer_function_local_latches See Changes From the Original HDL Compiler Tool on page C-60. As of Version Arrays of instances defparam statement See Arrays of Instances on page C-46. See defparam Statement on page C-38. / C-37

38 Table C-3 Other HDL Compiler (Presto Verilog) Features (Continued) HDL Compiler (Presto Verilog) New or enhanced features Combinational while loop Resource sharing for conditional expressions Divide operator Modulus operator Shift operator inference Text macros hdlin_enable_vpp Description See Combinational while Loop on page C-40. See Sharing Using hlo_resource_allocation on page 6-7. See Divide Operator on page C-50. Operator now supports constant and variable operands. Synthetic ops can now be inferred for shift operators (<<, >>) Text macros are supported with sized constants. The functions of the preprocessor are built in to HDL Compiler, and the functions are automatically enabled. `undefineall See See `undefineall on page 7-8. New Verilog netlist reader The new reader incorporates algorithms that reduce the memory usage and CPU runtime of the read command. See New Verilog Netlist Reader on page C-55. defparam Statement The defparam statement allows overriding parameter values at lower levels in the hierarchy, enabling parameter values to be changed in any module instance. It works on submodules only, not on the current module or modules elsewhere in the design. See Example C-21. Example C-21 defparam Statement module top (x, y, q); input x, y; output q; defparam mid.bot.p2=2, mid.bot.p3=3; / C-38

39 middle mid (x, y, q); module middle (x, y, q); input x, y; output q; bottom #(0,1) bot (x, y, q); module bottom (a, b, q); input a, b; output q; parameter p0 = 100; parameter p1 = 200; parameter p2 = 300; parameter p3 = 400; assign q = a & b; p0=0, p1=1, p2=2, p3=3 In Example C-21, the original value of parameter p3 is 400. If you use the defparam statement, the value is changed as it is passed from the top to the middle and finally to the bottom design, in which p3 changes from 400 to 2. The defparam statement enables each module instantiation to customize declared parameters. The result of the code in Example C-21 is p0=0, p1=1, p2=2, and p3=3. There are three ways a module instantiation can override the value of a parameter in a submodule. For example, assume that module m1 (x,y); parameter p = 0; You can override the parameter p by coding defparam u1.p = 1; m1 u1 (x,y); or, / C-39

40 m1 #(1) u1 (x,y); or, m1 # (.p(1) u1(x,y); Combinational while Loop To create a combinational while loop, write the code so that an upper bound on the number of loop iterations can be determined. Examples of supported combinational while loops are provided in Examples C-22 through C-24. An example of an unsupported loop is shown in Example C-25. The loop iterative bound must be statically determinable; otherwise an error is reported. If the loop bound cannot be determined, the program limits the maximum number of iterations to the value set by the hdlin_loop_iteration_limit variable and reports an ELAB-900 error. The original HDL Compiler tool supports loops with known upper and lower bounds and known constant steps. For example, input [9:0] a; //... i = 0; while ( i < 10 &&!a[i] ) begin i = i + 1; // loop body The original HDL Compiler tool only supports while loops with event statements in them (implicit state machines). HDL Compiler (Presto Verilog) relaxes these restrictions but still needs to be able to determine an upper bound on the number of trips through the loop at / C-40

41 compile time. In HDL Compiler (Presto Verilog), there are no syntax restrictions on the loops. While loops that have no events within them, such as in the example below, are supported. input [9:0] a; //... i = 0; while ( i < 10 &&!a[i] ) begin i = i + 1; // loop body To support this, HDL Compiler (Presto Verilog) interprets the loop like a simulator. It stops when the loop termination condition is known to be false. Because it can t tell when a loop is infinite, it stops and reports an error after an arbitrary (but user defined) number of iterations (the default is 1000). In the original HDL Compiler tool, disable is recommed for early loop exits; for example, begin: loop_block for (i = 0; i < 10; i = i+1) begin if(a[i]) disable loop_block; // loop body But HDL Compiler (Presto Verilog) allows additional conditions in the loop condition permitting more concise descriptions. for (i = 0; i < 10 && a[i]; i = i+1) begin // loop body / C-41

42 A loop must unconditionally make progress toward termination in each trip through the loop, or it cannot be compiled. The example below makes progress (that is, increments i) only when!done is true and will not terminate. while ( i < 10 ) begin if (! done ) done = a[i]; // loop body i = i + 1; The modified version below, which unconditionally increments i, will terminate. This code creates the desired logic. while ( i < 10 ) begin if (! done ) begin done = a[i]; // loop body i = i + 1; In the next example, loop termination deps on reading values stored in x. If the value is unknown (as in the first and third iterations), HDL Compiler (Presto Verilog) assumes it might be true and generates logic to test it. x[0] = v; x[1] = 1; x[2] = w; x[3] = 0; // Value unknown: implies if(v) // Known TRUE: no guard on 2nd trip // Not known: implies if(w) // Known FALSE: stop the loop i = 0; while( x[i] ) begin // loop body i = i + 1; / C-42

43 Example C-22 This code terminates after three iterations when the loop tests x[3], which contains 0. In Example C-22, a supported combinational while loop, the code produces gates and an event control signal is not necessary. Supported while Loop Code module modified_s2 (a, b, z); parameter N = 3; input [N:0] a, b; output [N:1] z; reg [N:1] z; integer i; or b or z) begin i = N; while (i) begin z[i] = b[i] + a[i-1]; i = i - 1; In Example C-23, a supported combinational while loop, no matter what x is, the loop will run for 16 iterations at most because HDL Compiler (Presto Verilog) can keep track of which bits of x are constant. Even though it doesn't know the initial value of x, it does know that x >> 1 has a zero in the most significant bit (MSB). The next time x is shifted right, it knows that x has two zeros in the MSB, and so on. HDL Compiler (Presto Verilog) can determine when x becomes all zeros. / C-43

44 Example C-23 Supported Combinational while Loop module while_loop_comb1(x, count); input [7:0] x; output [2:0] count; reg [7:0] temp; reg [2:0] count; (x) begin temp = x; count = 0; while (temp!= 0) begin count = count + 1; temp = temp >> 1; Figure C-2 shows the compiled design, while_loop_comb1, from the code in Example C-23. Figure C-2 while_loop_comb1 Compiled Design x[7:0] count[2:0] / C-44

45 In Example C-24, a supported combinational while loop, HDL Compiler (Presto Verilog) knows the initial value of x and can determine x+1 and all subsequent values of x. Example C-24 Supported Combinational while Loop module whil_loop_comb2(y, count1, z); input [3:0] y, count1;output [3:0] z; reg [3:0] x, z, count; (y, count1) begin x = 2; count = count1; while (x < 15) begin count = count + 1; x = x + 1; z = count; Example C-25 is an unsupported combinational while loop. Example C-25 Unsupported Combinational while Loop module combinational-while-loop-unsupported ( x, y); input [3:0] x; output [3:0] x; reg [3:0] x; reg [3:0] count; while ( x < 15 ) begin count = count + 1; x = x + 1; / C-45

46 HDL Compiler (Presto Verilog) cannot detect the initial value of x and therefore cannot determine the value of x+1. Because it never detects what any bits of x are, it can never determine when x < 15 and cannot create gates for this code. Arrays of Instances This feature enables instantiations of modules that contain a range specification, which, in turn, allows an array of instances to be created. See See Naming Arrays of Instances on page 8-4. In Example C-26, the module test creates two pipeline registers, that is, a single pipeline with two stages. Example C-26 Module Test: Code and Gates module test ( D, CK, Q ); input D, CK; output Q; reg Q0, Q; (posedge CK) begin Q0 <= D; Q <= Q0; D CLK Q In Example C-27, the module array_inst uses the test module to make three pipelines three stages deep. / C-46

47 Example C-27 Arrays of Instances: Code and Gates module array_inst (clk, din, dout); parameter N=3; input clk; input [N-1:0] din; output [N-1:0] dout; reg [N-1:0] dout; wire [N-1:0] idout; test test1[n-1:0] (.D(din),.CK(clk),.Q(idout)); (posedge clk) begin dout <= idout; module test ( D, CK, Q ); input D, CK; output Q; reg Q0, Q; (posedge CK) begin Q0 <= D; Q <= Q0; Another example of array instantiation is shown below in which four copies of the dff module are instantiated. module dff (d, ck, q); input d, ck; output q;... / C-47

48 input ck; input [0:3] d; output [0:3] q; dff ff[0:3] (d, ck, q); HDL Compiler (Presto Verilog) unwraps the array instantiation as shown below. Note that ck is connected to each instance, whereas d and q have one bit connected to each instance. input ck; input [0:3] d; output [0:3] q; dff ff_0 (d[0], ck, q[0]); dff ff_1 (d[1], ck, q[1]); dff ff_2 (d[2], ck, q[2]); dff ff_3 (d[3], ck, q[3]); In this next example of array instantiation, x exactly matches the width of a on the submodule, so its full width is connected to each instantiated module. module submod (x, ck, y); input [0:3] d; input ck; output q;... input ck; input [0:3] x; output [0:3] y; submod ff[0:3] (x, ck, y); The new HDL Compiler unwraps the array instantiation as shown below. / C-48

49 input ck; input [0:3] d; output [0:3] q; submod M_0 (x, ck, y[0]); submod M_1 (x, ck, y[1]); submod M_2 (x, ck, y[2]); submod M_3 (x, ck, y[3]); In this next example of array instantiation, note that the declared ordering of bits [3:0] of y does not affect the instantiation of submod (compare to the previous example). Bits are connected by position not by number. module submod (x, ck, y); input [0:3] d; input ck; output q;... input ck; input [0:3] x; output [0:3] y; submod ff[0:3] (x, ck, y); HDL Compiler (Presto Verilog) unwraps the array instantiation as shown below. input ck; input [0:3] d; output [0:3] q; submod M_0 (x, ck, y[0]); submod M_1 (x, ck, y[1]); submod M_2 (x, ck, y[2]); submod M_3 (x, ck, y[3]); / C-49

50 Divide Operator HDL Compiler (Presto Verilog) supports division where the operands are not constant by instantiating a DesignWare divider. Note that when you compile a design that contains an inferred divider, you must have a DesignWare-Foundation license. Example C-28 Divide Operator: Code and Gates module divide (a, b, z); input [9:0] a, b; output [8:0] z; assign z= a / b; divide_dw_div_uns_10_10_0 Writing to Out-of-Bounds Array Locations Verilog simulators allow writing to out-of-bounds array locations; in simulation, this has no effect on the values stored in the array. However, HDL Compiler assumes that nonconstant array accesses are in bounds. This means that out-of-bounds accesses, as shown in Example C-29, might have uninted consequences and HDL Compiler will issue a warning that the access might be out of bounds. Example C-29 Out of Bounds Access module E (addr, data, clk, out, out_addr); reg [2:0] mem; input data, clk; output out; input [2:0] addr, out_addr; / C-50

51 // Value of addr could be 3..7: possibly out of bounds access clk) mem[addr] = data; // Read could be out of bounds too; // In simulation, 1 bx but for synthesis, 1 b0 or 1 b1 assign out = mem[out_addr]; If you get that warning and you can t guarantee that the address will be in-bounds, add an if statement, as shown in Example C-30, around the write to protect it by explicitly testing that the address is in bounds before the assignment. Example C-30 Added Code to Insure In-Bounds Access module E (addr, data, clk, out, out_addr); reg [2:0] mem; input data, clk; output out; input [2:0] addr, out_addr; clk) // Test that addr accesses an in-bounds location. if ( addr < 4) mem[addr] = data; assign out = mem[out_addr]; The HDL Compiler (Presto Verilog) option hdlin_dyn_array_bounds_check = true automatically adds the code, as shown in Example C-30. This allows you to implement simulator behavior and guarantees that no out-of-bounds access will affect values stored in the array. This option increases the area of the design. / C-51

52 Using $display During RTL Elaboration The $display system task is usually used to report on simulation progress; however, HDL Compiler (Presto Verilog) executes $display calls as it sees them. It usually cannot tell the value of variables, except compile-time constants like loop iteration counters. It will execute all the display statements on all the paths through the program as it generates the logic. Note that because HDL Compiler (Presto Verilog) executes all $display calls, error messages from the Verilog source can be executed and can look like unexpected messages. Using $display is useful for printing out any compile-time computations on parameters, or the number of times a loop executes. A $display example is shown below. module F (in, out, clk) parameter SIZE = 1; input [SIZE-1: 0] in; output [SIZE-1: 0] out; reg [SIZE-1: 0] out; input clk; //... `ifdef PRESTO always $display( Instantiating F, SIZE=%d, SIZE); `if F #(2) F2 (in1, out1, clk); F #(32) F32 (in1, out1, clk); Here is what is output to the screen while elaborating. dc_shell> elaborate TOP Running PRESTO HDLC... / C-52

53 Information: Building the design 'F' instantiated from design 'TOP' with the parameters "2". (HDL-193) Running PRESTO HDLC Instantiating F with SIZE = 2 Presto compilation completed successfully. Information: Building the design 'F' instantiated from design 'TOP' with the parameters "32". (HDL-193) Running PRESTO HDLC Instantiating F with SIZE = 32 Improved Logic for Array Reference on the Left Side Compare the code below. mem[addr] = data; vs. for (i = 0; i < size; i = i + 1) if ( i == addr ) mem[i] = data; The original HDL Compiler Builds different GTECH circuits for these two cases Requires using the style on the right to get the best results HDL Compiler (Presto Verilog) Builds the same GTECH circuit for each case Allows using the more concise style on the left Improved MUX_OP inference MUX_OPs offer significantly better timing than SELECT_OPs and, in some cases, better layout. / C-53

54 Using the original HDL Compiler, there is only one way to get a MUX_OP, and that is to use a case statement with the //synopsys infer_mux directive. With HDL Compiler (Presto Verilog), there are three ways to get a MUX_OP: Use a case statement with the //synopsys infer_mux directive. Use an if statement with the //synopsys infer_mux directive. Use a variable array reference: x[a]. Note that, for Presto, the case statement must be parallel, otherwise a MUX_OP is not inferred and an error is reported. Even when the //synopsys parallel_case directive is used, if the case statement is not truly parallel, an error is reported. The original HDL Compiler does not require parallel case statements. To avoid MUX_OPs for variable array references, set hdlin_build_selectop_for_var_index to true. Sharing Array References Array references with variable subscripts can be an overlooked cause of increased area. HDL Compiler (Presto Verilog) detects when you refer to the same array location more than once, and shares the logic. An example is shown below. out1 = p2[var_index][0]; //... out2 = p2[var_index][1]; T = p2[var_index]; out1 = T[0]; //... out2 = T[1]; / C-54