Chisel to Chisel 3.0.0

Transcription

1 Chisel to Chisel 3.0.0

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4 Generators: Type-Safe Meta-Programming for RTL Design Reuse Type-Safety Powerful Language Features 4

5 Hired Jonathan Bachrach 5

6 At the end of ParLab, we solved hardware design 6

7 ParLab Chip Highlight Reel 7

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10 And so, the problem of hardware design was forever solved. 10

11 Just kidding. 11

12 Solving Hardware Design Solving The Hardware Design Loop Specification Production RTL Design Verification Validation Physical Design Packaging Tapeout * from How to Draw Chip and Dale booklet. (Walt Disney, 1955) 12

13 What had to change? Hardware Design Ecosystem Stable and User-Friendly API External Collaborations 13

14 Platform-Specific or Application-Specific RTL Changes Chip RTL + scan interface + snapshotting + interactive debug Zynq FPGA + clock-generators + SRAMs with init + specialized layout ST 28nm FDSOI + SRAM macros + modified module hierarchy + specialized layout IBM 45nm SOI 14

15 What were we doing? Manually change RTL? Obfuscates/specializes RTL Use CAD tool scripts? Many unsupported use cases Python script to edit RTL Not reusable/robust/composable * from accessed 10/23/17 * from accessed 10/23/17 15

16 Realization: We need a software stack, but for hardware projects Rocket BOOM rocketchip libraries Hwacha chisel-utils language Chisel Frontend clang transforms compiler x86 ARM RISC-V FIRRTL platforms 16

17 Second-System-Syndrome: But... do we really need all that? Sodor: 6451 loc Hwacha: 6953 loc BOOM: 8298 loc RocketChip: 9578 loc Chisel: loc? 17

18 Specification RTL Design Verification Physical Design Production Validation Packaging Tapeout 18

19 For impact, we need an ecosystem Verilog Chisel PyChisel BIST/JTAG Stitching Early Area Estimation FPGA Snapshotting ASIC SRAMS FIRRTL FPGA Assertions Floorplanning Hints FPGA FAME-1 Retiming Verilog C++ Scala 19

20 Developing, Porting, Code Reviews, Testing, and so forth Spring 2015 Summer 2015 Fall 2015 Winter 2015 Spring 2016 Summer 2016 Fall 2016 Winter 2016 Spring 2017 Designed FIRRTL Compiler Designed Chisel 3 Frontend Ported RocketChip Ported Chisel Testers Added Fixed-Point Type Added Analog Type Added withclock Summer 2017 Released Chisel Fall 2017 Released FIRRTL

21 Chisel and FIRRTL have been released! Projects FireSim - Datacenter Emulation on FPGAs Strober - Fast+Accurate Power Sims. for Long Programs Hurricane 2 - Multi-Core DVFS (Sub-Core) Quick (and Semi-Accurate) Timing and Area Estimation Automatic Combinational Cycle Removal Snapshotting and Hardware Assertions for FPGAs Transformations New Features Chisel FIRRTL Hardware Types vs Hardware Components New types (e.g. Complex, DspReal, Fixed-Point, Analog) Chisel Library support (annotations) Invalidate API for safer connections 21

22 Intel: Fast and Semi-Accurate FIRRTL Timer 22

23 What had to change? A Chisel Compiler Stable and User-Friendly API External Collaborations 23

24 Emphasis on Clarity Chisel Reg(UInt(3)) Chisel Reg(UInt(3.W)) RegNext(3.U) RegInit(3.U) Reg(chiselTypeOf(3.U)) Register of type UInt, width of 3 Register whose next cycle s value is 3 Register whose initial value is 3 Register no initial value and width of Register of type UInt, width of 3 Register whose next cycle s value is 3 Register whose initial value is 3 Register no initial value and width of 2 24

25 Less Error-Prone API s Chisel def func[t<:chisel.data](other: T) = { io.out := Reg(null.asInstanceOf[T], Reg(next = other) next = other, null.asinstanceof[t]) } [info] [0.000] inferred type arguments Elaborating [Object] design... do not conform to method apply's type parameter [info] [0.022] bounds Done elaborating. [T <: Chisel.Data] Chisel def func[t<:chisel.data](other: T) = { io.out := RegNext(other) } [info] [0.000] Elaborating design... [info] [0.022] Done elaborating. 25

26 Lightweight Support for Multi-Clock/Reset withreset(io.alternatereset) { val altrst = RegInit(0.U(10.W))... } Everything in this scope with have io.alternatereset as the reset withclock(io.alternateclock) { val altclk = RegInit(0.U(10.W))... } Everything in this scope with have io.alternateclock as the clock 26

27 Exciting Future Work: The Unified Chisel Tester Tester Device Under Test The following image is a DRAMATIZATION of real experiences Fragmented Landscape BasicTester (Hardware Testing Hardware) PeekPokeTester (Interactive and Slow) AdvancedTester (Limited Concurrency) Lightweight, powerful, fast Multiple circuit drivers, multithreaded Integration with Verilator, VCS, Interpreter Unified Chisel Tester If you have thoughts - send them our way! (Current Chisel Testing Environment) 27

28 What had to change? A Chisel Compiler Stable and User-Friendly API External Collaborations 28

29 Documentation, Documentation, Documentation 29

30 30 Bootcamps and Tutorials

31 Open-Development via Github Issues/Pull Requests 31

32 Stack Overflow! 32

33 Academic Impact: 188 citations (in 5 years) 33

34 Active Users (That We Know Of) 34

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36 Ideas for Governance? Maintenance? Workshops? 36

37 Thanks to all Chiselers out there! (And many more!!) 37

38 So long (ASPIRE), and thanks for all the fish chips! 38