Free Chips Project: a nonprofit for hosting opensource RISC-V implementations, tools, code. Yunsup Lee SiFive
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1 Free Chips Project: a nonprofit for hosting opensource RISC-V implementations, tools, code Yunsup Lee SiFive
2 SiFive Open Source
3 We Open-Sourced the Freedom E310 Chip! 3
4 We Open-Sourced the Freedom E310 Chip! RTL & FPGA scripts Board Support Packages (BSP) Documentation & Board Schematic Forums 3
5 Rocket-Chip Generator Repository Statistics 4
6 Rocket-Chip Generator Repository Statistics 4
7 Rocket-Chip Generator Repository Statistics 4
8 SiFive s Contribution to Rocket-Chip Repository Our contributions are under the Apache v2 license 5
9 SiFive s Contribution to Rocket-Chip Repository Our contributions are under the Apache v2 license Rocket Core Added RV32I + M/A/F support, compressed support, blocking data cache, and data SRAM options 5
10 SiFive s Contribution to Rocket-Chip Repository Our contributions are under the Apache v2 license Rocket Core Added RV32I + M/A/F support, compressed support, blocking data cache, and data SRAM options TileLink Open cache-coherent interconnect with memory-mapped I/O support 5
11 SiFive s Contribution to Rocket-Chip Repository Our contributions are under the Apache v2 license Rocket Core Added RV32I + M/A/F support, compressed support, blocking data cache, and data SRAM options TileLink Open cache-coherent interconnect with memory-mapped I/O support Diplomacy Global parameter negotiation framework 5
12 SiFive s Contribution to Rocket-Chip Repository Our contributions are under the Apache v2 license Rocket Core Added RV32I + M/A/F support, compressed support, blocking data cache, and data SRAM options TileLink Open cache-coherent interconnect with memory-mapped I/O support Diplomacy Global parameter negotiation framework Other primitives Multi-clock support, clock crossings, and asynchronous reset flops 5
13 SiFive Blocks Repository 6
14 SiFive Blocks Repository Low-speed Peripherals SPI, UART, PWM, GPIO, PMU Written in Chisel with TileLink interfaces 6
15 SiFive Blocks Repository Low-speed Peripherals SPI, UART, PWM, GPIO, PMU Written in Chisel with TileLink interfaces High-speed Xilinx FPGA Peripherals Wrappers for MIG DDR block and PCIe block 6
16 SiFive Blocks Repository Low-speed Peripherals SPI, UART, PWM, GPIO, PMU Written in Chisel with TileLink interfaces High-speed Xilinx FPGA Peripherals Wrappers for MIG DDR block and PCIe block Our vision to make a plug-and-play SoC generator starts with these reusable building blocks 6
17 Freedom Repository 7
18 Freedom Repository Submodules both rocket-chip and sifive-blocks 7
19 Freedom Repository Submodules both rocket-chip and sifive-blocks Top-Level SoC Integration Serves as a good baseline to build an SoC with your own custom blocks 7
20 Freedom Repository Submodules both rocket-chip and sifive-blocks Top-Level SoC Integration Serves as a good baseline to build an SoC with your own custom blocks FPGA scripts are also open-sourced Freedom E300 Arty FPGA Dev Kit Freedom U500 VC707 FPGA Dev Kit 7
21 Freedom FPGA Dev Kits Start prototyping your innovative ideas on Freedom platforms! 8
22 Freedom FPGA Dev Kits Start prototyping your innovative ideas on Freedom platforms! 8
23
24 But, it takes a village to make open-source hardware real
25 Launching the Free Chips Project Non-Profit Home for Open-Source Codebase Mission: Home for Open-Source Codebase to Enable Faster, Better, Cheaper Chips Initial contributions from SiFive and Berkeley Call for participation! Any questions? Purpose Sustain and evolve open-source software tools and HDL code for system-on-chip (SoC) design Ensure free and open contributions are available to all of the SoC design community Manage publicly accessible, online repositories of source code, documentation and issues 016 SiFive. All Rights 10
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