Diplomatic Design Patterns
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1 Diplomatic Design Patterns Henry Cook Wesley Terpstra Yunsup Lee A TileLink Case Study 10/14/2017
2 Agenda Rocket-Chip Ecosystem Diplomacy TileLink Design Patterns DRYing out Parameterization Generation with a View Compositional Cake Deployment 2 SiFive
3 The Rocket-Chip Ecosystem for RISC-V Chisel A Domain-Specific Language for hardware construction embedded in Scala Rocket-Chip A collection of hardware generators implemented in Chisel Diplomacy A Scala framework for negotiating parameters between Chisel generators TileLink A parameterized chip-scale shared-memory interconnect protocol 3
4 Diplomacy 4
5 When Chisel Isn t Enough We d like to be able to see everything that will be in the system before we even start to emit any hardware descriptions How early can we detect misconfiguration? <> considered harmful wire width inference can mask problems Generators are nice... but parameterization itself is a source of complexity but each generator needs to agree with the others about what to generate 5
6 Diplomatic Parameterization Graphical abstraction of interconnectivity Directed Acyclic Graph (DAG) Node point where parameterized hardware is going to be generated Edge a directed pairing between a master and slave interface Modules may have many nodes and nodes may have many edges 6
7 Simple Example Graph 7 SiFive
8 Actual (small) Rocket-Chip Graph Tile AXI to TL TL to AXI Peripherals TL to AXI 8 SiFive
9 What Parameters Can Be Diplomatic? The cardinality of sources connected to a particular sink (transitive) The cardinality of sinks connected to a particular source (transitive) The type and size of operations issues by each master and slave The type and size of operations allowed on a particular address Other properties governing allowed behavior on particular regions (e.g. modifiability, executability, cacheability) Ordering requirements on operations over subgraphs (e.g. FIFO) Presence of certain fields within control wire bundles Widths of fields within with control or data wire bundles Presence of entire virtual networks or channels 9
10 How Diplomacy Negotiates Two-phase elaboration First, graph is created and parameters are negotiated (LazyModules) Second, Chisel hardware is elaborated (Module implementations) During the first ( diplomatic ) phase: One set of parameters flow outwards from master to slave nodes One set of parameters flow inwards from slave to master nodes Adapter nodes can modify parameters flowing through them All modules can place requirements on parameter values 10
11 Short Circuiting the Debug Loop What happens when negotiation fails? Error at Scala runtime What doesn t happen? Chisel elaboration Verilog emission Verilog compilation Simulation execution Waveform debugging 11
12 TileLink 12
13 TileLink: Graphical Structure 13 SiFive
14 TileLink: Graphical Structure Directed Acyclic Graph (DAG) (again) Agent (Node) point where messages are created Link (Edge) a directed pairing between two agents master and slave interface Modules may have many agents and agents may have many links 14
15 TileLink: Directed Channels 15 SiFive
16 TileLink: Modularity Spec defines threes levels of conformance Rocket-Chip uses Diplomacy to achieve even finer granularity Individual links specialized to the types of messages sent 16
17 TileLink: Composability Generality of interfaces All agents use the same transaction structure Scalability rules for hierarchy DAG prevents deadlock Strict prioritization of channels Necessary for individual transactions to make forward progress Decoupled handshaking rules Limit when and why messages can be rejected Deadlock freedom and forward progress guarantees! 17
18 TileLink: Transaction Structure 18 SiFive
19 Design Patterns 19
20 DRYing out parameterization Don t Repeat Yourself Every piece of knowledge must have a single, unambiguous, authoritative representation within a system
21 Hardware Generation With A View 21 SiFive
22 Combinational Composition Thin adapters that each serve a specific, orthogonalized function Zero-cycle response time is allowed (support is actually mandatory) Simplify verification at no design cost 22
23 Combinational Composition Modify control signals fragment burst messages into a series of single beat messages Modify message field widths widen the width of the data bus plane Manage inter-message transaction requirements enforce FIFO ordering across a series of messages and responses 23
24 Sequential Composition Decoupled nature of TileLink interfaces makes it easy to insert buffering at arbitrary point in the graph 24
25 Hierarchical Composition Any sub-graph can be swapped out for a different sub-graph that provides the same properties Inserting caches (or chains of caches) Filtering addresses into banks Transparently crossing clock domains Transparently converting between protocols Scala traits Interfaces that can provide concrete members Support multiple inheritance Build a system from layered components (cake pattern) 25
26 Compositional Cake 26
27 Deployment 27
28 Rocket-Chip: 2017 Rewrite Piecewise conversion to Diplomatic TileLink and AMBA using adapters between sub-graphs with different protocol versions Started from slaves and moved inward to masters Took about 6 months to complete Only remaining non-diplomatic Modules are the top-level test harness and leaf modules inside of the Rocket tiles 28
29 Future Work: Diplomacy Automatic punching of IOs via cross-module edges Ease arbitrary changes to granularity of module hierarchicalization Conversion between clock domains Cross at boundary of automatically inserted module wrappers Lightweight support for interrupts and other simple types that need to be routed to arbitrary locations, including to top-level IOs Diplomatic RoCC 29
30 Future Work: TileLink Critical Word First for cache blocks Richer performance hints Cache coherence protocol parameterization Deadlock freedom and forward progress proofs, formal models ChipLink 30
31 31 SiFive
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A Cache Hierarchy in a Computer System Ideally one would desire an indefinitely large memory capacity such that any particular... word would be immediately available... We are... forced to recognize the