Labeled RISC-V Demos

Transcription

1 Labeled RISC-V Demos Zihao Yu, Yungang Bao June 3 rd, Los Angeles Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) 1

2 We have provided a server for you! Please prepare your laptop with an SSH client Enjoy at the second part of this talk! Everything is prepared SSH read codes and run emulation in containers access our FPGA cloud to run real applications 2

3 Agenda Labeled RISC-V emulation flow Labeled RISC-V FPGA flow

4 Getting the source codes git clone ~/riscv-pard/labeled-risc-v $ ls bootrom firrtl project scripts vsrc chisel3 fpga README.md src context-dependent-environments hardfloat regression target csrc LICENSE riscv-tools torture emulator Makefrag sbt-launch.jar vsim FPGA and emulator building platform codes are also under src/main/scala 4

5 Read fpga/readme.md to start! Initialize submodules Install riscv toolchains Do not forget to install the linux-gnu toolchain 5

6 Build a minimal image for emulation labeled-risc-v/fpga $ make sw This command will Pull the riscv-bbl and riscv-linux repo bbl is a bootloader to boot linux on RISC-V Set the linux with a default config Build a linux image and bbl Read fpga/readme.md for more details ~/temp/riscv-pard/labeled-risc-v/fpga/build $ ls -l total 4716 lrwxrwxrwx 1 yzh yzh 47 Jun 3 19:42 bbl.elf -> /home/yzh/temp/riscv -pard/sw/riscv-pk/build/bbl -rwxrwxr-x 1 yzh yzh Jun 3 19:42 linux.bin lrwxrwxrwx 1 yzh yzh 48 Jun 3 19:42 vmlinux -> /home/yzh/temp/riscv -pard/sw/riscv-linux/vmlinux 6

7 Build and run the emulator labeled-risc-v/fpga/emulator $ make run-emu This command will Compile the scala project with PARDSimConfig into verilog code See labeled-risc-v/src/main/scala/pard/ PARDConfigs.scala Use verilator to compile the verilog code into an executable for emulation Convert the Image into a data file Run the executable to start emulation The data file will be used to initialize the memory 7

8 Observe the output of UART labeled-risc-v/fpga/emulator $ tail f build/test/serial@ initializing hart 1 plic_init... hart_plic_init... memory_init... boot_loader... load_kernel_elf... memcpy bytes, src , dest c000 8

9 The development flow before FPGA Add features to the scala source Write small program, run it on the emulator to test the features Debug with emulator Use assert() and printf() in the scala code catch unexpected behaviors dump the value of signals Observe the output of UART Run large scale of emulators with different random seeds Use the same random seed to replay the unexpected behavior 9

10 Agenda Labeled RISC-V emulation flow Labeled RISC-V FPGA flow

11 Generate a Vivado project labeled-risc-v/fpga $ make project PRJ=myprj BOARD=zcu102 This command will Generate the verilog code with PARDFPGAConfigzcu102 See labeled-risc-v/src/main/scala/pard/ PARDConfigs.scala Create a Vivado project with zcu102 as the target board Supported target boards are listed under labeled-risc- V/fpga/board Currently only Vivado is supported ~/temp/riscv-pard/labeled-risc-v/fpga/board/zcu102/build/myprj-zcu102 $ ls myprj-zcu102.cache myprj-zcu102.ip_user_files myprj-zcu102.xpr myprj-zcu102.hw myprj-zcu102.srcs

12 RISC-V subsystem configurations Varies with different boards with different resource Board # RISC-V cores Frequency # BTB entries L2 cache size Memory size zedboard 2 30 MHz KB 128 MB zcu MHz 40 2 MB 2 GB sidewind er MHz 40 2 MB 2 GB ultraz MHz KB 1 GB Board used in our FPGA cloud

13 Boot the FPGA Generate bitstream in Vivado Generate BOOT.BIN with Vivado SDK Build u-boot, linux image and dtb for PS Install a base system in a SD card Put everything above together to boot PS It is a long journey See labeled-risc-v/fpga/boot/readme.md for details

14 TileLink Bus AXI4 Bus CN Bus (Jtag-based) Basic Architecture LDom #1 LDom #2 LDom #3 LDom #4 PC GEM UART CN Switch Rocket Rocket Rocket Rocket Core Control Logic L1toL2 Network Cache Control Logic L2 HellaCache RocketChip MMIO Manager Memory Control Logic Jtag Port Eth0 UART*4 PRM (PS) Memory Controller (MIG7) Xilinx Zynq/Zynqmp Evaluation Board 14

15 Build the PRM tools Copy prm-sw/ directory to PRM Build the tools $ make PLATFORM=fpga -C axi-loader $ make PLATFORM=fpga -C partctl $ make PLATFORM=fpga -C stab ls axi-loader/build/ axi-loader-fpga fpga ls pardctl/build/ fpga pardctl-fpga ls stab/build/ fpga stab-fpga

16 Boot RISC-V subsystem on FPGA Use PRM tools to configure control plane registers and boot RISC-V subsystem Labeled-based virtualization without software hypervisor Labeled-based performance counters

17 Run redis and file copy Running redis server in partition QPS: % latency: 87ms Running file copying in another partition QPS: % latency: 120ms

18 Labeled-based performance isolation QPS: % latency: 99ms Redis L2 usage KB (74.9%) File copy L2 usage 64.06KB (25.02%) File copy Mem BW 48882tps LLC - 12:4 Mem BW 50ktps for file copy

19 Thanks Labeled RISC-V Demos 19