RISC-V Rocket Chip SoC Generator in Chisel. Yunsup Lee UC Berkeley

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Nicholas Simmons
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1 RISC-V Rocket Chip SoC Generator in Chisel Yunsup Lee UC Berkeley

2 What is the Rocket Chip SoC Generator?! Parameterized SoC generator written in Chisel! Generates Tiles - (Rocket) Core + Private Caches! Generates Uncore (Outer Memory System) - Coherence Agent - Shared Caches - DMA Engines - Memory Controllers! Glues all the pieces together 2

3 Rocket Chip SoC Generator Rocket Core FPU L1 Inst ROCC Accel. Tile L1 Data Rocket Core FPU L1 Inst L1 Network Coherence Manager ROCC Accel. Tile L1 Data HTIF! Generates n Tiles - (Rocket) Core - RoCC Accelerator - L1 I$ - L1 D$! Generates HTIF - Host DMA Engine! Generates Uncore - L1 Crossbar - Coherence Manager - Exports MemIO Interface TileLink / MemIO Converter 3

4 Why SoC Generators?! Helps tune the design under different performance, power, area constraints, and diverse technology nodes! Parameters include: - number of cores - instantiation of floating-point units, vector units - cache sizes, associativity, number of TLB entries, cache-coherence protocol - number of floating-point pipeline stages - width of off-chip I/O, and more 4

5 Why Chisel?! RTL generator written in Chisel - HDL embedded in Scala! Full power of Scala for writing generators - object-oriented programming - functional programming C++ code Chisel Program Scala/JVM FPGA Verilog ASIC Verilog C++ Compiler Software Simulator FPGA Tools FPGA Emulation ASIC Tools GDS Layout 5

6 Rocket Scalar Core PC IF ID EX MEM WB ITLB Int.RF DTLB PC Gen. I$ Inst. Int.EX D$ Commit Access Decode Access bypass paths omitted for simplicity Rocket Pipeline To RoCC to Hwacha Accelerator FP.RF FP.EX1 FP.EX2 FP.EX3-64-bit 5-stage single-issue in-order pipeline - Design minimizes impact of long clock-to-output delays of compiler-generated RAMs - 64-entry BTB, 256-entry BHT, 2-entry RAS - MMU supports page-based virtual memory - IEEE compliant FPU - Supports SP, DP FMA with hw support for subnormals 6

7 ARM Cortex-A5 vs. RISC-V Rocket Category ARM Cortex-A5 RISC-V Rocket ISA 32-bit ARM v7 64-bit RISC-V v2 Architecture Single-Issue In-Order Single-Issue In-Order 5-stage Performance 1.57 DMIPS/MHz 1.72 DMIPS/MHz Process TSMC 40GPLUS TSMC 40GPLUS Area w/o Caches 0.27 mm mm 2 Area with 16K Caches 0.53 mm mm 2 Area Efficiency 2.96 DMIPS/MHz/mm DMIPS/MHz/mm 2 Frequency >1GHz >1GHz Dynamic Power <0.08 mw/mhz mw/mhz - PPA reporting conditions - 85% utilization, use Dhrystone for benchmark, frequency/power at TT 0.9V 25C, all regular VT transistors - 10% higher in DMIPS/MHz, 49% more area-efficient 7

8 HTIF: Host-Target Interface! UC Berkeley specific block mainly used to emulate devices for simple test chips - Emulates system calls, console, block devices, frame buffer, network devices - No need for this block once the SoC has actual devices on the target machine! Consider it as a host DMA engine! A port for for host system to read/write - Core CSRs (control and status registers) - Target Memory 8

9 Important Interfaces in the Rocket Chip Rocket Core FPU L1 Inst client mngr client mngr ROCCIO TileLinkIO TileLinkIO ROCC Accel. Tile L1 Data Rocket Core FPU L1 Inst L1 Network Coherence Manager TileLink / MemIO Converter ROCC Accel. Tile L1 Data HTIF client client client client TileLinkIO TileLinkIO MemIO HTIFIO arb arb HostIO TileLink TileLink! ROCCIO - Interface between Rocket/Accelerator! HTIFIO - Read/Write CSRs! TileLinkIO - Coherence Fabric! MemIO - Simple AXI-like memory interface! HostIO - Host Interface to HTIF 9

10 Probe Grant Probe Grant TileLinkIO Client Client Cache Cache Acquire Release Finish Acquire Release Finish Manager - TileLinkIO consists of Acquire, Probe, Release, Grant, Finish 10

11 Probe Grant Grant UncachedTileLinkIO Client Client Cache Acquire Release Finish Acquire Finish Manager - UncachedTileLinkIO consists of Acquire, Grant, Finish - Convertors for TileLinkIO/UncachedTileLinkIO in uncore library 11

12 MemIO Master MemReqCmd MemReqCmd.valid MemReqCmd.ready Slave Decoupled(MemData) Decoupled(MemResp) - MemReqCmd consists of addr, rw (write=true), tag - MemData consists of 128 bit data payload - MemResp consists of 128 bit data payload, tag - Decoupled(interface) means an interface with ready/ valid signals 12

13 ROCCIO Rocket Decoupled(Cmd) Decoupled(Resp) CacheIO busy IRQ supervisor bit UncachedTileLinkIO PTWIO exception ROCC Accel.! Rocket sends coprocessor instruction via the Cmd interface! Accelerator responds through Resp interface! Accelerator sends memory requests to L1D$ via CacheIO! busy bit for fences! IRQ, S, exception bit used for virtualization! UncachedTileLinkIO for instruction cache on accelerator! PTWIO for page-table walker ports on accelerator 13

14 HTIFIO HTIF reset core_id Decoupled(CSRReq) Decoupled(CSRResp) Decoupled(IPIReq) Decoupled(IPIResp) Tile - reset signal and core_id routed from HTIF (historical reasons nothing technical) - CSR Read/Write requests go through CSRReq/CSRResp - IPI Requests go through IPIReq/IPIResp - HTIFIO likely to be modified in the near future 14

15 Rocket Chip C++ Emulator Setup Verilog Simulator pthread Rocket Chip HostIO RISC-V Frontend Server pthread MemIO DRAMSim2 15

16 ZYNQ FPGA Rocket Chip FPGA Setup Rocket Chip MemIO HostIO HostIO/AXI Convertor MemIO/AXIHP Convertor AXI HP AXI AXI Master AXI HP Slave ARM Processing System DDR3 DRAM RISC-V Frontend Server 16

17 Rocket Chip Berkeley Test Chip Setup Test Chip Rocket Chip MemIO MemIO Serializer HostIO MemSerialIO ZYNQ FPGA HostIO/AXI Convertor MemIO/AXIHP Convertor MemIO MemIO Deserializer AXI HP AXI AXI Master AXI HP Slave ARM Processing System RISC-V Frontend Server DDR3 DRAM 17

18 Rocket Chip SoC Setup Interrupts Rocket Chip TiileLinkIO Uncached TiileLinkIO Devices MemIO MemIO LPDDR3 Memory Controller LPDDR3 DRAM 18

19 Rocket Core FPU L1 Inst client mngr ROCCIO TileLinkIO Who should use the Rocket Chip Generator? People who would like to develop ROCC Accel. Tile L1 Data Rocket Core FPU L1 Inst L1 Network Coherence Manager ROCC Accel. Tile L1 Data HTIF client client client client TileLinkIO TileLinkIO HTIFIO arb HostIO TileLink! A RISC-V SoC - Look into Chisel parameters! New Accelerators - Drop in at ROCCIO level! Own RISC-V Core - Drop in at TileLinkIO level or MemIO level! Own Device - Drop in at TileLinkIO or UncachedTileLinkIO client arb mngr TileLinkIO TileLink / MemIO Converter TileLink MemIO 19

20 New Features: L2$ with Directory Bits Rocket Core FPU L1 Inst client L2Cache mngr client ROCC Accel. Tile L1 Data Rocket Core FPU L1 Inst L1 Network ROCC Accel. Tile L1 Data HTIF client client client client L2CacheCoherence L2Cache ManagerL2Cache L2Cache mngr mngr mngr mngr arb client client client client TileLink! Shared L2$ with multiple banks! Each L2$ will act as a coherence manager with directory bits (snoop filter)! These caches can be composed to build outer-level caches such as an L3$ mngr TileLink / MemIO Converter TileLink 20

21 New Features: ROCC interfaces with L2$ Rocket Core FPU L1 Inst ROCC Accel. Tile L1 Data Rocket Core FPU L1 Inst L1 Data ROCC Accel. Tile HTIF! ROCC talks directly to the L2$ to address more data client client client client client L2Cache mngr L1 Network arb L2CacheCoherence L2Cache ManagerL2Cache L2Cache mngr mngr mngr mngr TileLink client mngr client client client client TileLink / MemIO Converter TileLink 21

22 New Features on the Deck! Dual-issue Rocket Core! Hwacha Vector Unit (checkout hwacha.org)! Dump MemIO and use AXI 22

A 45nm 1.3GHz 16.7 Double-Precision GFLOPS/W RISC-V Processor with Vector Accelerators"

A 45nm 1.3GHz 16.7 Double-Precision GFLOPS/W ISC-V Processor with Vector Accelerators" Yunsup Lee 1, Andrew Waterman 1, imas Avizienis 1,! Henry Cook 1, Chen Sun 1,2,! Vladimir Stojanovic 1,2, Krste Asanovic