A Retrospective on Par Lab Architecture Research

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Sharleen Knight
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1 A Retrospective on Par Lab Architecture Research Par Lab SIGARCH Krste Asanovic, Rimas Avizienis, Jonathan Bachrach, Scott Beamer, Sarah Bird, Alex Bishara, Chris Celio, Henry Cook, Ben Keller, Yunsup Lee, Eric Love, Martin Maas, Quan Nguyen, Albert Ou, David Patterson, David Sheffield, Zhangxi Tan, Danny Tang, Stephen Twigg, Huy Vo, Andrew Waterman, Richard Xia, Brian Zimmer

2 Par Lab Lasagna Stack Easy to write correct programs that run efficiently on manycore Diagnosing Power/Performance Personal Health Image Hearing, Speech Parallel Retrieval Music Browser Design Patterns/Motifs Composition & Coordination Language (C&CL) C&CL Compiler/Interpreter Parallel Libraries Efficiency Sketching Languages Autotuners Legacy Communication & Schedulers Code Synch. Primitives Efficiency Language Compilers OS Libraries & Services Legacy OS Hypervisor Multicore/GPGPU Parallel Frameworks ParLab Manycore/RAMP Static Verification Type Systems Directed Testing Dynamic Checking Debugging with Replay Correctness

3 Early Ideas Elucidate computers behavior Standardize minimum set of performance counters (SHOT: Standardized Hardware Operation Trackers) Simplify computers behavior Reduce interference via memory system QoS (Globally Synchronized Frames) Opt-in efficiency-level programming Manage memory hierarchy in software only when desired (Virtualized Local Stores)

4 Bridging the Simulation Gap Lengthy, detailed simulation necessary to evaluate these ideas Need to run real (=> long-running) workloads Can t get parallelism via trace-based simulation (inaccurate for multicore) Software simulation woefully tardy 2 weeks to discover misconfigured experiment! Explored FAME (FPGA Architecture Model Execution), cf. SAME (Software)

RAMP Gold Rapid accurate simulation of manycore architectural ideas using FPGAs Initial version models 64 cores of SPARC v8 with shared memory system on $750 board Hardware FPU, MMU, boots our OS and

5 RAMP Gold Rapid accurate simulation of manycore architectural ideas using FPGAs Initial version models 64 cores of SPARC v8 with shared memory system on $750 board Hardware FPU, MMU, boots our OS and Par Lab stack! Software Simulator Cost Performance (MIPS) Time per 64 core simulation $2, hours RAMP Gold $2,000 + $ hour Download at: 5

6 Lessons Learned from RAMP Gold Separating functional model from timing model reduces resource use dramatically Model only $ tags, not $ data Multithreading essential for modeling large systems Improves utilization Obviates need for routing-intensive bypass paths Extra state is main cost, but RAMs cheap in FPGA Long program runs are essential! Mem BW partitioning idea looked optimal with reduced input sets, but worse than naïve on real data

Lessons Learned from RAMP Gold It s challenging to manually implement abstract FAME simulators All the usual HW design challenges + more indirection

7 Lessons Learned from RAMP Gold It s challenging to manually implement abstract FAME simulators All the usual HW design challenges + more indirection Ongoing work on autogenerating FAME simulators Ideas live on in DIABLO, a warehouse-scale computer simulator Simulates a 2000-node datacenter in 12U!!

8 Maven Vector-Thread Architecture Explored energyefficient data-parallel machines Considered MIMD, Decoupled Vector, and Vector-Thread architectures Evaluated 100s of design points via VLSI implementation + gatelevel simulation

9 Lessons Learned from Maven SIMD (Vector, Vector-Thread) architectures much more efficient than MIMD on DLP code Energy / Kernel (uj) Kernel: Masked Filter MIMD Vector VT Inst. Mem. Control Datapath Data Mem. Leakage

10 Lessons Learned from Maven VLSI implementation is essential to gain useful insight into design tradeoffs Energy efficiency is strong function of implementation details Need feedback from VLSI early in design process Verilog is awful language for HW generators Gate-level simulation a major pain point, but FAME can only help after detailed energy modeling Maven skirted this issue by only evaluating kernels

11 More Productive HW Design with Chisel Learned from RAMP Gold, Maven that popular HDLs aren t suited for generators In Chisel, write Scala programs that generate circuits Employing modern SW engineering practices and programming paradigms (OOP, functional) makes it easier to write generators Have built cache coherence generators; still learning how to build flexible CPU generators

12 Chisel Design Flow Chisel Program Scala/JVM C++ code FPGA Verilog ASIC Verilog C++ Compiler Software Simulator FPGA Tools FPGA Emulation ASIC Tools GDS Layout

13 RISC-V A clean, open ISA, defined after experiences with commercial ISAs in RAMP Gold, Maven Simple enough to use in architecture education, yet powerful enough to build high-performance implementations Growing software ecosystem: GCC, Linux, glibc, python Several hardware implementations (Rocket research cores, Sodor educational cores)

14 RISC-V is Real Processor Site Clock test DCDC site test site SRAM test site

15 Conclusion We think specialization is path to efficiency Blurring of HW/SW interface will greatly expand design space It s incumbent on us to conceive better tools and techniques to explore it

16 DEMO

Optical Flow Kernel on a 45nm RISC-V Vector Processor Optical flow computes the apparent

part of the final integrated demo Written in Python Loops Auto-Vectorized with Three

reordering transforms generates CPU, GPU, RISC-V vector code, and custom processing

17 Optical Flow Kernel on a 45nm RISC-V Vector Processor Optical flow computes the apparent motion of each pixel (direction and speed) across two frames of a video This kernel is part of the final integrated demo Written in Python Loops Auto-Vectorized with Three Fingered Jack (TFJ) TFJ is a loop-based auto vectorizer Parallelism extracted using reordering transforms generates CPU, GPU, RISC-V vector code, and custom processing engine implementations Target Machine 45nm RISC-V Vector Processor (has virtual Color code Optical flow field

18 Today s Target Machine: Real Silicon 45nm RISC-V Rocket/Hwacha Processor Written in Chisel Fabricated with IBM 45nm SOI Currently running up to 1GHz Photonics RX/TX Photonics RX/TX

19 Demo Setup 45nm RISC-V Vector Processor 1 GHz Front Side 32 MHz Virtex-6 FPGA Board Ethernet Laptop 512MB DRAM

20 Actual Setup

21 1 MB Emulated DRAM Processor Chip Highlights Chip Area: 3mm x 6mm 64 bit Rocket Scalar Core + 64 bit Hwacha Vector Core Processor Area: 1.6mm x 1.1mm Estimated Estimated 70m+ transistors Memory Controller Cache RISC-V Vector Core Vector Register-File

22 Forthcoming Chips Raven2 28nm RISC-V Rocket processor EOS16 45nm dual RISC-V Rocket/Hwacha processor EOS18 Energy-optimized EOS16

23 BACKUP

24 EOS14 Specification RISC-V 64-bit ISA Rocket 64 bit Scalar Core + Hwacha 64 bit Vector Core Shared IEEE DFMA, SFMA between Scalar and Vector Fabricated in IBM 45nm SOI Focus on functionality for initial system integration area/power not optimized Processor (Core + Uncore) Area: 1.6mm x 1.1mm Operating Frequency: > TT 1V 25C Estimated 504mW Estimated 622mW Estimated 622 pj/op, 311 pj/flop

25 EOS14 Block Diagram

26 EOS14 Floorplan

27 EOS16 Specification RISC-V 64-bit ISA Dual Rocket 64 bit Scalar Core + Hwacha 64 bit Vector Core Shared IEEE DFMA, SFMA between Scalar and Vector Fabricated in IBM 45nm SOI Focus on functionality for initial system integration area/power not optimized Processor (Core + Uncore) Area: 2.8mm x 1.1mm Operating Frequency: > TT 1V 25C Estimated 990mW Estimated 1222mW Estimated 611 pj/op, 306 pj/flop

28 EOS16 Block Diagram

29 EOS16 Floorplan

30 EOS16 Tile Floorplan

Integrating the Par Lab Stack Running Damascene on SEJITS/ROS/RAMP Gold

Integrating the Par Lab Stack Running on /ROS/RAMP Gold Kevin Klues, Yunsup Lee, Andrew Waterman Par Lab Winter Retreat 2010 Overall Goal of the Par Lab: Create Productive, Efficient, Correct, Portable