ANALOG MODELING WITH VERILOG-A USING CADENCE TOOLS. Eng. Sherief Fathi
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1 ANALOG MODELING WITH VERILOG-A USING CADENCE TOOLS Eng. Sherief Fathi
2 Hardware Description Language (HDL) In electronics, a hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits. Two HDLs used today: VHDL and Verilog Both are industrial standards and are supported by most software tools. German University in Cairo 2
3 Verilog-AMS Combines Verilog,... Discrete-event / discrete-value simulation Verilog-A, Continuous-time / continuous-value simulation Signal flow modeling Conservative modeling And some extras Discrete-event / continuous value simulation Automatic interface element insertion Digital Analog System System Gate Circuit Verilog Verilog-A Verilog-AMS
4 Mixed-Level Simulation (MLS) Digital Mixed-Signal IBS 2001 German University in Cairo 4
5 Verilog-A Able to model analog circuits and systems - Signal-flow models Model relates potentials only Useful for abstract models - Conservative models Model relates potentials and flows Device modeling and loading at interfaces German University in Cairo 5
6 Potential Potential Potentials and Flows V(a,b) + a b I(a,b) + + V(in) V(out) Flow Potential module resistor (a, b); electrical a, b; parameter r = 1; analog V(a,b) <+ r*i(a,b); endmodule module amp (out, in); output out; input in; voltage out, in; parameter a = 1; analog V(out) <+ a*v(in); endmodule Resistor Amplifier Conservative Model (potential & flow) Signal-Flow Model (potential only) German University in Cairo 6
7 Declaring Modules module mymod(p,n);... endmodule German University in Cairo 7
8 Ports module modname(outport1, outport2, inport, bidirectional); output outport1; output [3:0] outport2; input inport; inout bidirectional; electrical outport1, [3:0] outport2, inport, bidirectional; endmodule German University in Cairo 8
9 Constants parameter real res = 5e3 from (0:inf); parameter real percentage = 0.7 from [0:1]; parameter integer N = 4 from (0:inf); parameter real poles[0:3] = { 1.0, 3.198, 4.554, 2.00 }; parameter string transistortype = "NPN" from { "NPN", "PNP" }; German University in Cairo 9
10 Variables integer a[1:64]; real float; real gain_factor[1:30]; // an array of 64 integer values // a variable to store real value // array of 30 gain multipliers German University in Cairo 10
11 Signal Access on Nodes, Ports, Branches To get (probe) values: use access function in expression x gets voltage between a and ground: x = V(a) x gets voltage between a and b: x = V(a,b) x gets current between a and ground: x = I(a) x gets current between a and b: x = I(a,b) To set (source) values: use access function as target in contribution set voltage between a and ground to x: V(a) <+ x set voltage between a and b to x: V(a,b) <+ x set current between a and ground to x: I(a) <+ x set current between a and b to x: I(a,b) <+ x German University in Cairo 11
12 The Contribution Operator : <+ Accumulates potentials or flows to nodes, ports, and branches Order of contribution is not significant module rlc (a, b); electrical a, b; parameter R = 1 exclude 0; parameter C = 1; parameter L = 1 exclude 0; analog begin I(a,b) <+ V(a,b) / R; I(a,b) <+ C*ddt(V(a,b)); I(a,b) <+ idt(v(a,b) / L; end endmodule German University in Cairo 12
13 Assignment vs Contribution Example1: module test(p,n) ; inout p,n; electrical p,n; parameter integer a = 2; real r; analog begin r=a; // Now r=2 r=2*a; // The value of r is updated to r=4 V(n) <+ a; // This equation contributes by a value a, V(n) =a=2; V(n) <+ 2*a; // A new contribution is added to V(n), V(n) = a+2a =6; end endmodule German University in Cairo 13
14 Operators Arithmetic Operators Relational Operators Equality Operators Logical Operators Bit-Wise Operators Unary Reduction Shift Operators Conditional Operators Concatenations +, -, *,**, /, % <, <=, >, >= ==,!=, ===,!==!, &&, ~, &,, ^, ~^ &, ~&,, ~, ^, ~^ >>, <<?: {} German University in Cairo 14
15 Analog Operators Differentiator: ddt() Time derivative of its argument Integrator: idt() Time integral of its argument Optional initial condition Circular integrator: idtmod() Time integral of its argument passed through modulus operation Time delay: absdelay() Delayed version of its argument German University in Cairo 15
16 Standard mathematical functions German University in Cairo 16
17 Trigonometric and hyperbolic functions German University in Cairo 17
18 If Statement (SWITCH) Example 1 if (x1 >= 2) begin x2= 5*x1; end else if (x1<5) begin x2= x1/2; end else begin x2 = x1; end Example 2 if(analysis("ic")) begin x2= init_cond; end else if(analysis("tran")) x2= x1/2; end begin German University in Cairo 18
19 Example: Resistor and Conductor Resistor (potential source branch) Conductor (flow source branch) i + v + i=gv v=ri module res (a, b); electrical a, b; parameter real r = 1; analog V(a,b) <+ r*i(a,b); endmodule module cond (a, b); electrical a, b; parameter real g = 1; analog I(a,b) <+ g*v(a,b); endmodule German University in Cairo 19
20 Example: Capacitor and inductor Capacitor inductor module cap (a, b); electrical a, b; parameter c = 1; analog I(a,b) <+ C*ddt(V(a,b)); endmodule module ind (a, b); electrical a, b; parameter L = 1; analog V(a,b) <+ L*ddt(I(a,b)); endmodule German University in Cairo 20
21 Example: Multiplier //VerilogA for a multiplier, `include "constants.vams" `include "disciplines.vams module multiplier(in1,in2,out); input in1,in2; output out; electrical in1,in2,out; analog begin V(out) <+ V(in1) * V(in2); end endmodule German University in Cairo 21
22 Inserting Verilog-A model into Cadence Open Cadence then change the editor: editor= gedit German University in Cairo 22
23 Inserting Verilog-A model into Cadence From the library manager, create a new cell view with a type: veriloga German University in Cairo 23
24 Inserting Verilog-A model into Cadence Insert the VerilogA code: German University in Cairo 24
25 Inserting Verilog-A model into Cadence Choose highlight mode > verilog German University in Cairo 25
26 Inserting Verilog-A model into Cadence Insert the VerilogA code, save the file, and close. 1. If the model does not has a syntax error, you will be asked to create a symbol. 2. If the model has a syntax error, open the error log to identify errors and solve it. German University in Cairo 26
27 Inserting Verilog-A model into Cadence Define the directions of the pins i.e. : left, right, top, or bottom German University in Cairo 27
28 Inserting Verilog-A model into Cadence Modify the symbol optional, then Check & Save German University in Cairo 28
29 Inserting Verilog-A model into Cadence Now you can test your model by creating a new cell view of type Schematic, and make a simple test circuit: German University in Cairo 29
30 Inserting Verilog-A model into Cadence German University in Cairo 30
31 Inserting Verilog-A model into Cadence German University in Cairo 31
32 Example B: TEAM Memristor model /TCAS_memristor_model_paper_final.pdf German University in Cairo 32
33 Example B: TEAM Memristor model Note: You can access the parameters values from the schematic directly German University in Cairo 33
34 Some useful links Verilog-AMS Manual Verilog-A model library at German University in Cairo 34
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37 Operators German University in Cairo 37
38 Verilog-AMS Combines Verilog,... Discrete-event / discrete-value simulation Verilog-A, Continuous-time / continuous-value simulation Signal flow modeling Conservative modeling And some extras Discrete-event / continuous value simulation Automatic interface element insertion 38 CADENCE DESIGN SYSTEMS, INC.
39 Named Branches Named branches are explicitly declared Useful when defining distinct parallel potential branches module rlc (a, b); electrical a, b; parameter R = 1, C = 1, L= 1; branch (a, b) res, cap, ind; analog begin V(res) <+ R*I(res); I(cap) <+ C*ddt(V(cap)); V(ind) <+ L*ddt(I(ind)); end endmodule 39 CADENCE DESIGN SYSTEMS, INC.
40 Example: Capacitor with Initial Condition module cap (a, b); electrical a, b; parameter real c=0, ic=0; analog begin if (analysis("ic")) V(a,b) <+ ic; else I(a,b) <+ ddt(c*v(a,b)); end endmodule 40 CADENCE DESIGN SYSTEMS, INC.
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42 Accessing Net and Branch Signals Examples Vin = V(in); CurrentThruBranch = I( mybranch ); Indirect branch assignment An indirect branch assignment is useful when it is difficult to solve an equation. It has this format, V(n) : V(p) == 0; which can be read as "find V(n) such that V(p) is equal to zero." German University in Cairo 42
43 Operator Precedence [ ] bit-select or part-select ( ) parentheses!, ~ logical and bit-wise negation &,, ~&, ~, ^, ~^, ^~ reduction operators +, - unary arithmetic { } concatenation *, /, % arithmetic +, - arithmetic <<, >> shift >, >=, <, <= relational ==,!= logical equality & bit-wise AND ^, ^~, ~^ bit-wise XOR and XNOR bit-wise OR && logical AND logical OR? : conditional
44 Analog operators and equations Time derivative operator Time integral operator Circular integrator operator German University in Cairo 45
45 The Contribution Operator <+ Accumulates potentials or flows to nodes, ports, and branches Order of contribution is not significant module rlc (a, b); electrical a, b; parameter R = 1 exclude 0; parameter C = 1; parameter L = 1 exclude 0; analog begin I(a,b) <+ V(a,b) / R; I(a,b) <+ C*ddt(V(a,b)); I(a,b) <+ idt(v(a,b) / L; end endmodule
46 The Contribution Operator <+ Supports implicit equations Solves for x when x <+ f(x) module diode (a, c); electrical a, c; parameter is = 1f from (0:inf); parameter rs = 0 from [0:inf); analog begin I(a,c) <+ is * ($limexp((v(a,c) rs * I(a,c) ) / $vt) 1); end endmodule Limiting Exponential (helps convergence) a I(a,c) on both sides makes eqn implicit c
47 Example: Controlled Sources module vcvs (p, n, ps, ns); electrical p, n, ps, ns; output p, n; input ps, ns; parameter gain = 1; analog V(p,n) <+ gain*v(ps,ns); endmodule module ccvs (p, n, ps, ns); electrical p, n, ps, ns; output p, n; input ps, ns; parameter gain = 1; analog V(p,n) <+ gain*i(ps,ns); endmodule module vccs (p, n, ps, ns); electrical p, n, ps, ns; output p, n; input ps, ns; parameter gain = 1; analog I(p,n) <+ gain*v(ps,ns); endmodule module cccs (p, n, ps, ns); electrical p, n, ps, ns; output p, n; input ps, ns; parameter gain = 1; analog I(p,n) <+ gain*i(ps,ns); endmodule
48 Hysteretic Relay module relay (pout, nout, pin, nin); voltage pout, nout, pin, nin; input pin, nin; output pout, nout; parameter real thresh = 0, hyst = 0; real offset; analog thresh offset, +1)) offset = thresh offset, 1)) offset = hyst; if (V(pin,nin) thresh offset > 0) V(pout, nout) <+ 0; end endmodule Switch Branch
49 Event-Driven blocks Blocks of code executed upon an event Event types Name cross() timer() initial_step final_step Generates events At analog signal crossings Periodically or at specific times At beginning of simulation At end of simulation Time of the Last Zero Crossing; last_crossing()
50 Example: Record Zero Crossing Times module zero_crossings (in); voltage in; input in; parameter integer dir=1 from [-1:1] exclude 0; integer fp; real last; analog fp = $fopen( zero-crossings ); last = $last_crossing(v(in), dir)) $fstrobe( fp, %0.10e, $fclose(fp); end endmodule Record time of crossing
51 Example: Noisy Diode module diode (a, c); electrical a, c; branch (a, c) diode, cap; parameter real is=1e 14, rs=0, tf=0, cjo=0, phi=0.7; parameter real kf=0, af=1, ef=1; analog begin I(diode) <+ is*($limexp(v(diode)/$vt) 1); I(cap) <+ ddt(tf*i(diode) - 2*cjo*sqrt(phi * (phi * V(diode))); I(diode) <+ white_noise( 2 * `P_Q * I(diode) ); I(diode) <+ flicker_noise( kf * pow(abs(i(diode)), af), ef); end endmodule
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56 Example: Resistive RF Source module port (p, m); voltage p, m; parameter real r=50, dc=0, mag=0, ampl=0, freq=0, phase=0; analog begin V(p,m) <+ 2*dc r*i(p,m); V(p,m) <+ 2*ac_stim(mag); V(p,m) <+ white_noise(4*`p_k*r*$temperature); if (analysis( tran )) V(p,m) <+ 2*ampl*cos(2*`M_PI*freq*$abstime+phase); bound_step(0.1 / freq); end endmodule +
Index. A a (atto) 154 above event 120, 207 restrictions 178
Symbols! (negation) 174!= (inequality) 174!== (not identical) 174 # delay 166, 216 not in analog process 196 $abstime 83, 175 $bound_step 77, 190 $discontinuity 69, 79, 80, 191 $display 192 $driver_...
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