IC-CAP From Waferscanning to PlotOptimizer - Verilog-A Support. Slide 1

Transcription

1 Slide 1 MOS-AK Meeting May 2004, Stuttgart IC-CAP From Waferscanning to PlotOptimizer - Verilog-A Support Franz_Sischka@agilent.com 1 This poster presents some of the new features available in IC-CAP 2004, focussing on the requirements of MOS modeling engineers.

2 Slide 2 Scan the Wafer 2 Applying GUIs (customizable Graphical User Interface), the user can setup any kind of window with any IC-CAP functionality behind it. In the example above, 24 MOS transistors are specified with respect to their name, L and W info, switching matrix connections and subsite position. The info can be loaded and saved to an ASCII file. Due to the flexibility, other user interface scenarios are definable as well. After this info has been specified, the wafer prober is triggered by IC-CAP and steps all dies on the wafer. The measurement result is saved in a single ASCII data file (all devices of all dies/subsites, at all temperatures). An alternative possibility is to save each device, at each temperature, in individual ASCII data files.

3 Slide 3 Specify the Modeling Targets 3 After the measurement files have been saved, individual sub-info can be loaded back for device modeling. In the customizable user interface above, the different measurements (plots) of the different devices can be selected, as well as the merging plots for Isat and VTH vs. Length and VTH vs. Width.

4 Slide 4 Specify the Model Parameters for Optimization 4 The new PlotOptimizer interface lets the user specify the parameters to be optimized or tuned for the previously selected measurement plots. IC-CAP 2004 offers now 14 different optimizer algorithms, each with absolute or relative targets.

5 Slide 5 Start the Optimization or tune manually 5 In the plots, boxes can be specified to shrink the optimization to certain data subranges. Several boxes per plot can be specified. The optimizer can optimize an unlimited number of idvd, idvg, VTH vs.l, VTH vs.w, Idsat, CV, S-parameter data etc. at the same time. The corresponding simulation calls are automatically performed by IC-CAP.

6 Slide 6 IC-CAP and Verilog-A Linking IC-CAP2004 with ADS2003C, Verilog-A model syntax is supported, and thus, it will be shown how this works in IC-CAP. Shipping open Verilog-A code with ADS2003C : angelov.va diode.va bsim3.va Gummel-Poon.va A-TFT.va curtice.va bsim4.va mextram.va P-TFT.va mesfet.va bsimsoi.va hicum_0.va Parker-Skellern.va mos11.va hicum_2.va tom1.va mos9.va vbic.va tom3.va hisim.va ekv (only compiled) jfet.va juncap.va Note: IC-CAP 2004 also supports Verilog-A for the other simulators running under IC-CAP 6 IC-CAP 2004 supports Verilog-A models. The above example is for ADS2003C as the simulator under IC-CAP. Slide 7 IC-CAP & ADS & Verilog-A Verilog-A model was modified since last simulation IC-CAP Verilog-A ASCII Tiburon-DA compiler Tiburon ADS Verilog-A model was not modified since last simulation compiled Verilog-A cache 7 When a Verilog-A model is simulated the first time, the Tiburon-DA compiler in ADS ( checks if the actual ASCII version is more recent than what is saved in the compiled Verilog cache directory. If this is true, a compilation is called in realtime and ADS simulates with the new compiled verilog-a code. If the ASCII is older than what is stored in the cache directory, no re-compilation is required.

7 Slide 8 1. Creating a simple ADS Verilog-A text file `include "disciplines.vams" module diode_va(anode,cathode); electrical anode,cathode; parameter real Is=1e-14 from [0:inf];... real Vd, Id, Qd; analog begin v Vd = V(anode,cathode); i = I * (en* vt S 1) Id = I(anode); // DC diode I(anode,cathode) <+ Is*(exp(Vd/(N*$vt)) - 1); // capacitance (junction and diffusion) Qd = Tt*Id + Cjo*Vj*(1 - pow((1-vd/vj),(1-m))) / (1-M); I(anode,cathode) <+ ddt(qd); end endmodule qd = TT id vd ( ) ( 1 M) CJO VJ vd qj = M VJ 8 and here's the complete Verilog-A code for the slide above: cut here /* Simple, minimalistic Diode verilog-a demo, w/o temperature, w/o area, w/ noise and w/o reverse breakdown modeling. It is based on the diode example in $ADS_ROOT/veriloga/diode.va, provided by Tiburon-DA. The applied model equations are: DC fwd: id(vd) = Is * (exp( vd / (N * vt)) - 1) DC rev: id(vd) = -Is C(v): Cj(vd) = Cjo / (1 - vd/vj)^-m Cdiff: Cd(vd) = Tt * gd */ // Make reference to verilog-a discipline 'electrical' (nodes) `include "disciplines.vams" module diode_va(anode,cathode); electrical anode,cathode;

8 parameter real Is=1e-14 from [0:inf]; parameter real N=1 from [0:10]; parameter real Cjo=0 from [0:inf]; parameter real M=0.5 from [0.1:1]; parameter real Vj=0.7 from [0.1:10]; parameter real Fc=0.5 from [0.4:0.95]; parameter real Tt=1p from [0:inf]; real Vd, Id, Qd; real f1, f2, f3, fcp; analog begin f1 = (Vj/(1 - M))*(1 - pow((1 - Fc), (1 - M))); f2 = pow((1 - Fc), (1 + M)); f3 = 1 - Fc*(1 + M); fcp = Fc * Vj; Vd = V(anode,cathode); Id = I(anode); // intrinsic diode. if (Vd < 0) I(anode,cathode) <+ - Is; else I(anode,cathode) <+ Is * (exp( Vd / (N * $vt)) - 1); // capacitance (junction and diffusion). if (Vd <= fcp) Qd = Tt * Id + Cjo * Vj * (1 - pow((1 - Vd / Vj), (1 - M))) / (1 - M); else Qd = Tt * Id + Cjo*( f1 + ( 1 / f2 ) * ( f3 * ( Vd - fcp ) + ( 0.5 * M / Vj ) * ( Vd * Vd - fcp * fcp))); I(anode,cathode) <+ ddt(qd); end endmodule

9 Slide 9 define veriloga_diode (A C) 2. Calling the ADS Verilog-A file from IC-CAP ;specify where to find the verilog-a code #load "veriloga", "C:\tmp\diode.va" ;specify the circuit R:RS A Ai R=1m DMain:diode Ai C ; call the verilog-a model by referring ; to its name in the diode.va file model DMain diode_va \ Is = 1E-17 \ N = 1 \ Cjo = 1f \ M =.4 \ Vj =.7 \ Fc =.5 end veriloga_diode except these two specials, the rest is an ordinary ADS netlist!! 9 calling a Verilog-A code from within IC-CAP is as simple as calling a built-in model of a simulator. Slide 10 After that, you can use the Verilog-A for all kinds of simulations see demo_features\6_simulators\2_ads\3_user_def_mdls\3_verilog-a\diode_veriloga.mdl 10