EE E6930 Advanced Digital Integrated Circuits. Spring, 2002 Lecture 18. Introduction to Verilog-A/Verilog-AMS
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1 EE E6930 Advanced Digital Integrated Circuits Spring, 2002 Lecture 18. Introduction to Verilog-A/Verilog-AMS
2 References D. Fitzpatrick and I. Miller, Analog Behavior Modeling with the Verilog-A Language, Kluwer Academic Publishers, cdsdoc documentation on Verilog-A On-line course reader paper.
3 Introduction Verilog and VHDL dominate the market for digital modelling (with about equal market share). The language are functionally equivalent and most simulators support both (and allow you to mix them!). Both are standardized by the IEEE. There has been a desire to ext these languages into the analog space by supporting the solution of continuous-time differential-algebraic equations. Verilog-A (later Verilog- AMS) and VHDL-AMS were such extensions. Both are making their way through the slow standards process although Verilog-AMS has the (significant) weight of Cadence behind it.
4 Two domains Verilog-AMS captures two different simulation domains Digital simulation domain Discrete event simulation kernel Analog simulation domain (Verilog A) Differential equation solver. Solutions change continuously between between individual solutions. Time-step selection deps on tolerances. Verilog-AMS provides mapping modules to provide translation of values and times from one domain to the other to create a true mixed-signal simulation environment.
5 Use of HDL In the digital world, HDLs are used for both simulation and synthesis. In the analog world, HDLs will be used primarily for simulation and perhaps synthesis is the very limited context of parameterized library elements (fixed circuit topologies).
6 Digital domain In our digital classes, we have learned VHDL. Verilog is identical functionality (the syntax is just different). Here is an AOI gate: // Verilog code for AND-OR-INVERT gate module AOI (A, B, C, D, F); input A, B, C, D; output F; assign F = ~((A&B) (C&D)); module;
7 Digital domain We also have the equivalent of a VHDL process statement in Verilog reg F; or B or C or D) begin F = ~((A&B) (C&D)); Just like in VHDL, to synthesize combinational logic using an always block, all variables must be assigned under all conditions and all inputs must be in the sensitivity list. (Otherwise, you will make a latch!)
8 Digital domain One can combine continuous assignments, (structural) hierarchy, and an always statement. // continuous assignments Assign selb = ~sel; Assign fb = ~((a&sel) (b&selb)); Assign f = ~fb; // structural INV G1 (sel, selb); AOI G2 (selb, a, sel, b, fb); INV G3 (.a(fb),.f(f)); // always block or a or b) Begin if (sel == 1) f = a; else f = b;
9 Digital domain Creating latches // Positive edge-triggered D flip-flop with reset module d_flop(clock, reset, d, q, q_n); input clock, reset, d; output q, q_n; reg q; assign q_n = ~q; clock or posedge reset) if (reset == 1) q <= 0; else q <= d; module;
10 Verilog-A Contributional operator <+ assigns an expression to a signal. Expression can be linear, non-linear, algebraic, or differential/integral functions of inputs signals. // Resistor module res(p, n); inout p, n; electrical p, n; parameter real r=0 from (0:inf]; parameter real res_value = 25; res #(.r(res_value)) mod(a1, a2); analog V(p, n) <+ r*i(p, n); Endmodule;
11 Analog operators Time derivative operator // capacitor module cap(p, n) inout p, n; electrical p, n; parameter real c=0 from [0:inf); analog I(p, n) <+ c*ddt(v(p, n)); module;
12 Analog operators Time integral operators idt(expr,ic) // PID controller model with differential input and single output module pid(in1,in2,out); input in1, in2; output out; electrical in1, in2, out; parameter real kp=1, ki=1, kd=1; real vin; analog begin vin = v(in1, in2)/2; v(out) <+ kp*vin + ki*idt(vin, 0) + dc*ddt(vin); module
13 Analog operators Transition operator module ideal_dac(in, out); input [0:dac_size-1] in; output out; electrical in, out; parameter real dac_size = 2 from (1:inf); parameter vth = 2.5; parameter real trise = 0 from [0:inf); parameter real tfall = 0 from [0:inf); real code; integer pow2 [0:dac_size]; analog for (i=0; i<= dac_size;i=i+1) pow2[i] = pow(2,i); code = 0; for (i = 0; i < dac_size; i=i+1) code = code + (V(in[i]) > vth)? Pow2[i] : 0; V(out) <+ transition(code/pow2[dac_size], 0, trise, tfall); module
14 Slew operator Analog operators
15 Analog operator Delay operator module delay_op(out, in); inout out, in; electrical out, in; analog V(out) <+ delay(v(in), 50n); module
16 Analog operators Laplace transform operators laplace_zp(expr, numer, denom). Zeros and poles of the filter are specified as pairs of real numbers, specifying the real and imaginary components of each zero or pole. laplace_nd(expr, numer, denom). Zeros and poles of the filter are specified as polynomial coefficients from lower order term to highest laplace_zd(expr, numer, denom). Zeros are specified as pairs of real numbers. Poles are specified as polynomial coefficients. laplace_np(expr, numer, denom). Zeros are specified as polynomial coefficients. Poles are are specified as pairs of real numbers.
17 Analog operators Laplace transform operators module laplace_op(out, in); inout out, in; electrical out, in; analog V(out) <+ laplace_np(v(in), { 1 }, {-0.81, 0.59, -0.81, -0.59, -0.31, 0.95, -0.31, -0.95, -1.0, 0.0}); module
18 Analog operators Z-transform operators zi_zp(expr, numer, denom,t,trf,t0) zi_nd zi_zd zi_np T is the period of the filter, trf specifies the transition time, t0 specifies the time of the first transition.
19 Analog operators Z transform operators Module discrete_op(out, in); inout out, in; electrical out, in; analog V(out) <+ zi_nd(v(in), {1.0}, {1.0}, 10u); module
20 Access to simulation environment $realtime() bound_step(). Sets an upper bound on the time step in simulation. module v_sine_generator(out); output out; voltage out; parameter real freq = 1K from (0:inf), ampl = 1, offset = 0; analog begin V(cout) <+ ampl * sin(`m_two_pi * freq * $realtime) + offset; bound_step(0.05/freq); module
21 Analog events Cross event module sample_hold (in, out, clk); input in, clk; output out; electrical in, out, clk; parameter real slewrate = 1.0e-9 from (0:inf); parameter real clk_vth = 2.5; real v; analog begin if (analysis( static ) (V(clk) > clk_vth)) v = V(in); // passing clk_vth, -1)) v = V(in); // sampling phase V(out) <= slew(v, slewrate); module
22 Timer event Analog events
23 Examples $discontinuity function tells simulator about discontinuities, but doesn t mean the simulator will handle them correctly! module v_deadband_amp(inp,inm,out); input inp,inm; output out; electrical inp, inm, out; parameter real vin_low = -1m, vin_high = 1m from (vin_low:inf), vout_dead = 0, gain_left = 1, gain_right = 1; real vout, vin; analog begin vin = V(inp, $discontinuity(1); if (vin >= vin_high) vout = gain_right*(vin-vin_high) + vout_dead; else if (vin <= vin_low) vout = gain_left*(vin-vin_high) + vout_dead; else vout = vout_dead; V(out) <+ vout; module module trisource (vout); output vout; electrical vout; parameter read wavelength = 10.0, amplitude = 1.0; integer slope; real wstart; analog wavelength)) begin slope = +1; wstart = $realtime; wavelength)) begin slope = -1; wstart = $realtime; $discontinuity(1); v(vout) <+ amplitude * slope * (4 * ($realtime wstart) / wavelength 1); module
24 Examples $strobe lets you print during a simulation module period_measure(in); input in; voltage in; parameter real vth = 0; integer crossings; real latest, previous; analog begin crossings=0; previous = 0; latest = begin crossings = crossings+1; previous= latest; latest = begin if (crossings < 2) $strobe( Could not measure period.\n ); else $strobe( period = %g, crossings = %d\n, latest-previous, crossings); module
25 Examples Indirect contributional statements 2 d x dt dx dt 2 t 0 2 o x() t o analog begin if (analysis( dc )) V(dx) <+ w0; else V(dx) <+ ddt(v(x)); V(x) : ddt(v(dx)) == -w0*w0*v(x);
26 disciplines and natures These are the standard electrical discipline declarations (contained in the standard definitions file): // current in amperes nature current units = A ; access = I; abstol = 1e-12; nature // potential in volts nature voltage units = V ; access = V; abstol = 1e-6; nature discipline electrical potential voltage; flow current; discipline; electrical n1, n2; V(n1, n2) I(n1, n2)
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