Agenda: Day Two. Unit 6: Specifying Timing Exceptions DAY 2. I/O Paths and Exceptions. Constraining I/O Interface Paths

Transcription

1 Agenda: Day Two 6-1 DAY 2 Unit I/O Paths and Exceptions Lab 5 Constraining I/O Interface Paths 6 7 Introduction to Timing Models (QTM) 8 Performing STA 9 Summary 10 Customer Support 6-1 Unit 6:

2 Unit Objectives 6-2 After completing this unit, you should be able to: List 4 timing exception commands and state their legal start and end points Specify false path exception in 3 design examples Write down the relationship between the Setup and Hold Multipliers when applying a multicycle path exception State the command to look for ignored exceptions Give 2 recommendations to specify timing exceptions effectively 6-2 Unit 6:

3 The Inputs and Outputs of PrimeTime 6-3 Gate-Level Netlist Constraints Exceptions Setup File Technology Libraries SDF PrimeTime Timing Models in.db format Reports Log, Script Files Our Focus 6-3 Unit 6:

4 Five Step Static Timing Analysis Flow 6-4 READ CONSTRAIN EXCEPTIONS CHECK Our Focus ANALYZE 6-4 Unit 6:

5 What are Timing Exceptions? 6-5 F1 F2 single clock cycle Timing exceptions are are used to to override the the default single-cycle constraints described by by create_clock, set_input_delay, and set_output_delay. 6-5 Unit 6:

6 Timing Exception Commands 6-6 Timing exceptions can be be applied to to any timing path: set_false_path Removes timing constraints from a timing path set_multicycle_path Allows more than one clock cycle for a timing path set_max_delay set_min_delay Specifies max and min delays on paths report_exceptions Reports current timing exceptions reset_path Restores the default timing constraints on specified paths 6-6 Unit 6:

7 Applying Exceptions 1/2 6-7 When using from and to options, you need to specify legal path start and end points: Start Input Ports and Clock Pins of Registers End Output Ports and Data Pins of Registers Start & End Clock Objects, Registers A D Q R1 clk1 clk2 D R2 Q pt_shell> set_false_path from A to R1/D pt_shell> set_false_path from clk1 to clk2 The complete commands for the example shown above should be: set_false_path from [get_pins A] to [get_pins R1/D] set_false_path from [get_clocks clk1] to [get_clocks clk2] When specifying register cell names for the start and end points, (under the hood) PrimeTime will look for the actual start and end pins of the register cell and apply the timing exception correctly for you. You can be very specific with timing exceptions with -to/-from/-through options by specifying rise or fall edges. New options include: -rise_from -fall_from -rise_to -fall_to -rise_through -fall_through 6-7 Unit 6:

8 Applying Exceptions 2/2 6-8 When using the through option, any pin can be used to describe the path: D R1 Q U12 Z D R2 Q clk pt_shell> set_false_path through U12/Z The path from R1/CP to R2/D will be false Assumption: No fanin/fanout When using the through option, multiple through arguments mean AND, multiple pins in one through are an OR. Example: set_false_path through A through B through {C D} means set a false path through the path that goes through A and B and (C or D). 6-8 Unit 6:

9 Multiple Paths 6-9 pt_shell> set_multicycle_path 2 -from -from FFA/CP \ -through Multiply/Out -to -to FFB/D FFB/D Two-Cycle Path -through -from FFA In Multiply Out D FFB -to CP One-Cycle Path Add sel In this example, it is sufficient to specify Multiply/Out using the through option, without the -from and to. 6-9 Unit 6:

10 Logically False Paths 6-10 A B B 1 mux1 The paths through both A s and both B s cannot happen: 10 They are logical false paths! Use the -through option: A mux2 set_false_path through mux1/a through mux2/a set_false_path through mux1/b through mux2/b You can find logical false paths with the report_timing true/-false/-justify command. This command will apply input combinations and trace through the netlist to find whether the reported path is logically correct. Consult the PrimeTime User Guide for a detailed explanation. Generally, you would only set this path as a false path if it appears in the timing reports with a violation Unit 6:

11 Paths Between Asynchronous Clocks 6-11 CLKA (100 Mhz from OSC1) FUNC_CORE Des_A Des_B N D Q D Q X D Q CLKB (100 Mhz from OSC2) current_design FUNC_CORE /* Make sure register-register paths meet timing */ create_clock -period 10 [get_ports CLKA] create_clock -period 10 [get_ports CLKB] /* Don t optimize logic crossing clock domains */ set_false_path -from [get_clocks CLKA] -to [get_clocks CLKB] set_false_path -from [get_clocks CLKB] -to [get_clocks CLKA] CLKA and CLKB are asynchronous to each other. To exclude Timing analysis between these 2 clock domains, specify the path(s) as false paths Unit 6:

12 Constrain Tri-states at the Top-Level 6-12 Tri-states can be the cause of many false paths. set_false_path -through [get_pins U1/DATA_BUS_OUT[1]] \ -through [get_pins U1/DATA_BUS_IN[1]] UART U1 TIMER U2 DATA_BUS_OUT DATA_BUS_IN DATA_BUS CPU U3 TOP_BLOCK 6-12 Unit 6:

13 Multi-cycle Paths 6-13 Clock period is is ns. ns. Per Specification, the the adder takes 6 clock cycles. How do do you constrain the the design? A B D E D E A B Q Q < 60 ns C_reg D Q + 64 E Y Clk D Q shift_reg 6-13 Unit 6:

14 Timing with Multi-cycle Constraints 6-14 create_clock -period [get_ports CLK] CLK] set_multicycle_path 6 setup -to -to [get_pins C_reg[*]/D] Launch Capture CLK -10 0ns C_reg/D IDEAL: T H < Adder_Delay < (60 - T SU ) C_reg/D PT assumes change could occur near any clock edge causing metastability! Where does PT perform hold analysis? T SU = setup time T H = hold time PT will perform the setup analysis on edge 6, i.e. at 60 ns. This will allow the adder s logic to have a delay of (60 setup_time uncertainty) Unit 6:

15 Default Hold Check 6-15 IMPLICIT! set_multicycle_path -setup -setup 6 -to -to [get_pins [get_pins C_reg[*]/D] C_reg[*]/D] set_multicycle_path -hold -hold 0 -to -to [get_pins [get_pins C_reg[*]/D] C_reg[*]/D] Launch Default Hold Check Capture CLK -10 0ns C_reg/D (50 + T H ) < Combo_Logic < (60 - T SU ) Why is hold check performed at 50 ns? The default Hold check is always performed one edge before the setup check. PT assumes that the clock edges at ns can cause metastability if they occur at the same time the data changes. Putting the hold check at 50 ns is the safest Unit 6:

16 Set the Proper Hold Constraint 6-16 OVERRIDE! set_multicycle_path -setup -setup 6 -to -to [get_pins [get_pins C_reg[*]/D] C_reg[*]/D] set_multicycle_path -hold -hold 5 -to -to [get_pins [get_pins C_reg[*]/D] C_reg[*]/D] M H = M S -1 Hold checks for : M H = 5 M H = 4 M H = 3 M H = 2 M H = 1 M H = 0 Setup Check with M S = 6 CLK -10 0ns C_reg/D Now allows change between T H and (60 - T SU ) D Q + E DESIRED RESULT: ALLOW 60ns for ADDER C_reg D Q E MH stands for Hold Multiplier, MS for Setup Multiplier. The Setup multiplier counts up with increasing clock cycles, the Hold multiplier counts up with decreasing cycles. The origin (0) for the Hold Multiplier is always at the Setup Multiplier 1 position Unit 6:

17 Precedence of Timing Exceptions 6-17 F1 F2 More than one exception set on the path from F1 to F2. set_false_path has higher precedence! (see student notes) clk1 clk2 set_false_path from clk1 to to clk2 set_max_delay 7 from F1 F1 to to F2 F2 PrimeTime uses the following general precedence rules, when applying multiple exceptions to the same path: set_false_path > set_max_delay or set_min_delay > set_multicycle_path pin > clock -from > -to > -through tighter constraint > looser constraint For more detailed information refer to the PrimeTime User Guide: Advanced Timing Analysis Unit 6:

18 Ignored Timing Exceptions 6-18 PrimeTime will warn you when invalid exceptions are applied. pt_shell> set_false_path -from FF1/Q Warning: Object 'FF1/Q' is not a valid startpoint. (UITE-216) How would you correct this exception? set_false_path -from FF1/Q -- Invalid because this is an INVALID start point. The exception needs the CLK pin of the flip-flop, so the correct syntax would be: set_false_path -from FF1/CLK 6-18 Unit 6:

19 Always Check for Invalid Exceptions 6-19 pt_shell> check_timing Warning: Warning: There There are are timing timing exceptions exceptions which which are are ignored. ignored. pt_shell> check_timing -verbose -ignored Warning: Warning: There There are are timing timing exceptions exceptions which which are are ignored. ignored. From From To To Setup Setup Hold Hold FF1/Q FF1/Q * FALSE FALSE FALSE FALSE To remove any unwanted exceptions, use the reset_path command, e.g.: reset_path from FF1/Q You may also use the command report_exceptions ignored to view ignored exceptions Unit 6:

20 Reduce Number of Timing Exceptions 6-20 To reduce the run-time for timing analysis, minimize the total number of exceptions! The paths from F1_reg to F2_reg are false. How many exceptions do each of the following commands generate? 32 F1 F2 F3 clk1 clk2 set_false_path set_false_path -from -from F1_reg[*]/CP F1_reg[*]/CP -to -to F2_reg[*]/D F2_reg[*]/D 1 for for {set {set i i 1} 1} {$i {$i <= <= 32} 32} {incr {incr i} i} { { set_false_path set_false_path -from -from F1_reg[$i]/CP F1_reg[$i]/CP -to -to F2_reg[$i]/D F2_reg[$i]/D } } set_false_path set_false_path -from -from F1_reg[*]/CP F1_reg[*]/CP 3 set_false_path set_false_path -from -from [get_clocks [get_clocks clk1] clk1] -to -to [get_clocks [get_clocks clk2] clk2] 4 2 The most efficient way to specify timing exceptions is between clock domains! 6-20 Unit 6:

21 Optimizing Analysis Time 1/ The -through option requires more CPU for large designs Do not use -through unless it is necessary Sub-Optimal: set_multicycle_path 2 -from U1/CP -through U2/A -through U3/B -through U4/A -through U5/C -to -to U6/D Optimal: set_multicycle_path 2 -to -to U6/D To help PT s run time, use -to option when possible Unit 6:

22 Optimizing Analysis Time 2/ Use set_disable_timing instead of set_false_path -through when there is one pin. Slow Sub-Optimal: set_false_path -through [get_pins ADDER/CI] Fast Optimal: set_disable_timing [get_pins ADDER/CI] 6-22 Unit 6:

23 Lab Overview and Review 6-23 LAB 60 min Apply Multicycle and false path exceptions on a complex design Lab Review How do you know where in a design to apply a multicycle path constraint? After applying a multicycle path constraint, how can you verify the constraint has been applied correctly? Answers will follow Unit 6:

24 Test For Understanding 6-24 A path between 2 flops are controlled by a 200 MHz clock. The path delay is 13 ns worst case. Clock has a network delay of 3 ns, and an uncertainty of 1 ns. Assume both setup and hold time are 0.5 ns. The best case delay of this path is known to be 6 ns. Write down the exceptions such that there will not be any setup or hold violations: How can you constrain a path from an asynchronous Reset input port to the Rst pin of a flop? The worst case absolute delay is 3 ns and the best case absolute delay is 0.9 ns Unit 6: