Compile RISC_CORE. Learning Objectives. After completing this lab, you should be able to: Perform a top-down compile strategy on the RISC_CORE design

Transcription

1 15 Learning Objectives After completing this lab, you should be able to: Perform a top-down compile strategy on the RISC_CORE design Lab Duration: 75 minutes Lab 15-1 Synopsys S38

2 Flow Diagram for Lab Create top_level.tcl constraints Modify runit.tcl to compile the RISC_CORE Execute runit.tcl; saves your design to mapped/risc_core.db Generate and analyze constraint and timing reports characterize one cell Explore different compile strategies to solve timing Save the solution in mapped/risc_core_final.db Lab 15-2

3 Top-Level Constraints for RISC_CORE Warning: These are not the same constraints that were used in constraints.tcl! Clock period Clock skew Operating Conditions Wire Load Model Driving Cell on all input ports except Clk Load on all output ports Input Delay on all input ports except Clk Output Delay on all output ports 4.0 ns 0.25 ns The worst-case (1.62V, 125 C) is represented by the library core_slow.db. Automatic selection buf1a3, pin Y buf1a2, pin A 2.0 ns 2.0 ns Task Create the constraints file top_level.tcl. The easiest way is to copy and modify the constraints.tcl file in order to apply the top-level constraints given in the table. Please double check the constraints are not the same. 2. Modify runit.tcl, to compile RISC_CORE only, and to include top_level.tcl instead of constraints.tcl. Multiple instances must be resolved before you compile the design. Remember to perform test-ready compile using scan option. Make sure runit.tcl saves the compiled design to mapped directory as RISC_CORE.db. Verify runit.tcl with the one at the end of this lab before moving on to next step. 3. Execute runit.tcl from UNIX shell and log the output to runit.log file. The compile step may take over 10 minutes. mapped/risc_core.db (the resulting design) will be the starting point for further optimization steps. 4. Report the compile results. Elapsed Time: Area: WNS: TNS: Lab 15-3

4 Task 2. Analyze Detailed Reports Answers are in the back of this lab. 1. Answer the following questions regarding the constraint report. Question 1. Are there any design rule violations? Question 2. What is the worst negative slack (WNS) in the design RISC_CORE? Question 3. In which cell (instance) is the worst of the violating timing paths ending? 2. Answer the following questions regarding the timing report. Question 4. Which design contains the critical path startpoint? Which design contains the endpoint? Question 5. Which of the two designs contain most of the combinational logic of the critical path? Suppose you wanted to recompile only one of the designs containing the critical path. This would be advantageous if a CPU-intensive compile strategy was going to be applied to fix the violation. (using a high map effort incremental compile). You would need to create a constraint script for the design containing the critical path. Question 6. Which DC commands could be used to accurately constrain the design containing the critical path, in terms of top-level IO timing, driving cells, and output loads? Lab 15-4

5 Task 3. characterize / write_script After verifying that the worst timing violation is between two blocks, you can now push the top-level constraints down onto the block with the bigger portion of the critical path. 1. Invoke Design Compiler and load the saved mapped RISC_CORE design. 2. Verify the current design is RISC_CORE. 3. characterize (with the constraints option) one of the cells containing the critical path. Remember that characterize works on a cell, not a design. For example, if the cell I_ALU contains most of the combinational logic in the critical path, issue the command: characterize constraints [get_cells I_ALU] Question 7. What is the design name of I_ALU? 4. Generate a constraints file for the cell you characterized by using the write_script command. Use the file extension _w.tcl to distinguish this script file as one generated by the write_script command. Remember that write_script echoes all the constraints on the current_design. current_design ALU write_script -output scripts/alu_w.tcl Recompile the sub block. Since a medium effort compile of this design did not yield a violation-free circuit on the first compile, a different compile strategy may be in order. For example, a higher map effort, a critical range, the set_flatten option, or use the DesignWare Foundation library. Lab 15-5

6 Task 4. Second-pass Compile with Characterize Try following compile strategies to get zero WNS (Worst Negative Slack) and TNS (Total Negative Slack), or try to minimize these values. Feel free to explore your own strategies to solve the timing violations or to reduce area. 1. Compile ALU with characterize constraint. # Verify that the current_design is ALU current_design ALU compile -inc map high 2. Report the following values for ALU from the compile log: Elapsed Time: WNS: TNS: current_design RISC_CORE report_constraint -all 3. Report the following values for RISC_CORE: WNS: Question 8. What sub block has the WNS now? Question 9. What blocks other than ALU have negative slack paths? The last command report_constraint -all shows all violating endpoints. 4. Use the following command to see the detailed path of the 4 biggest violators: report_timing -max 4 You might consider characterizing another cell, or try to group the blocks that are part of a critical path. Lab 15-6

7 Task 5. Second-pass Compile with DW Foundation This task demonstrates a different approach. The original block with the biggest violator (ALU) will be recompiled starting from the unmapped source to take advantage of high-level synthesis (HLO). 1. Perform the following commands to use the DW Foundation library and to start from the unmapped source for the block with the largest violations. # To get a fresh starting point delete all designs and # read mapped/risc_core.db. remove_design -design read_db mapped/risc_core.db # activate DW Foundation library set synthetic_library dw_foundation.sldb lappend link_library $synthetic_library # remove the block with biggest violations remove_design ALU # Read in unmapped file, for High-Level Optimizations read_db unmapped/alu.db # Apply characterized constraints and compile ALU source scripts/alu_w.tcl compile scan Report the following values: Elapsed Time: Area: WNS: TNS: 2. Report the DW implementations for ALU. report_resources Question 10. What are the DesignWare implementations in the design ALU? 3. Resolve remaining violations on design RISC_CORE. # Change back to RISC_CORE and compile incrementally for # the rest of RISC_CORE design current_design RISC_CORE link compile scan inc map high Lab 15-7

8 Task 6. Fix Hold Time 1. The design RISC_CORE might still show hold time violations. Verify with report_constraint -all. report_constraint -all 2. Use the following commands to fix hold time violations: set_fix_hold [all_clocks] compile scan inc -only_design_rule 3. Report area and timing information from the compile log: Elapsed Time: Area: WNS: TNS: 4. Enter the following command to see any remaining violations: report_constraint all You might see a number of small setup violations. You will fix them as you work to improve RISC_CORE area in the next step. Task 7. Improve Area 1. Set an area constraint to improve a desings size. The area of RISC_CORE was roughly Pick an area constraint which is ~15% less than that, like You could pick a value of zero, but the compile time will go up. set_max_area compile scan -inc -map high 2. Report area and timing information from the compile log: Elapsed Time: Area: WNS: TNS: Lab 15-8

9 3. Verify that RISC_CORE meets all design requirements: report_constraint all You have just successfully synthesized the RISC_CORE design. The only violation is with regard to the area goal of DC made its best effort to improve RISC_CORE s size. Task 8. Save the Final Gate-level Netlist 1. Save the design RISC_CORE, along with its entire hierarchy, to the mapped directory as RISC_CORE_final.db. 2. Quit DC. Lab 15-9

10 Answers / Solutions Example top_level.tcl # Create user defined variables set CLK_PORT [get_ports Clk] set CLK_PERIOD 4.0 set WC_SKEW 0.25 set DRV_CELL buf1a3 set DRV_PIN Y set OUTPUT_LOAD [load_of ssc_core_slow/buf1a2/a] set INPUT_DELAY 2.0 set OUTPUT_DELAY 2.0 set ALL_INS_EX_CLK [remove_from_collection \ [all_inputs] [get_ports Clk]] reset_design set_operating_conditions max slow_125_1.62 create_clock -period $CLK_PERIOD -name my_clock \ $CLK_PORT set_dont_touch_network [get_clocks my_clock] set_clock_uncertainty $WC_SKEW [get_clocks my_clock] set_driving_cell lib_cell $DRV_CELL -pin $DRV_PIN \ $ALL_INS_EX_CLK set_load $OUTPUT_LOAD [all_outputs] set_input_delay -max $INPUT_DELAY -clock my_clock \ $ALL_INS_EX_CLK set_output_delay max $OUTPUT_DELAY -clock my_clock \ [all_outputs] Lab 15-10

11 Example runit.tcl # Directory Structure set UNMAPPED_DIR unmapped set SCRIPT_DIR scripts set MAPPED_DIR mapped set REPORTS_DIR reports # List of designs to be compiled set DESIGNS_LIST {RISC_CORE} foreach module $DESIGNS_LIST { read_db $UNMAPPED_DIR/$module.db current_design $module link source echo scripts/top_level.tcl uniquify compile -scan write -hierarchy -output $MAPPED_DIR/$module.db redirect $REPORTS_DIR/$module.rpt \ {report_constraint -all_violators} redirect append $REPORTS_DIR/$module.rpt \ {report_timing} } quit Question 1. Are there any design rule violations? There should be no design rule violations in design RISC_CORE. If there had been, it would have been reported in the constraint report. Question 2. What is the worst negative slack (WNS) in the design RISC_CORE? The largest negative slack may vary. If you go through several recompile iterations you should record this number to verify that you are improving the design. In some versions, the violation is approximately 0.6 ns. Lab 15-11

12 Question 3. In which cell (instance) is the worst of the violating timing paths ending? The results may vary with different versions of DC. You can select the cell in the GUI to obtain the name. In some versions, the critical path ends in I_ALU. Question 4. Which design contains the critical path startpoint? Which design contains the endpoint? The cell containing the startpoint and endpoint will vary with different versions of DC. In some versions, the critical path starts at a registered output of DATA_PATH, and ends in ALU. Question 5. Which of the two designs contain most of the combinational logic of the critical path? All of the combinational logic is in the ALU. Question 6. Which DC commands could be used to accurately constrain the design containing the critical path, in terms of top-level IO timing, driving cells, and output loads? To only compile one subdesign, use characterize to push the top-level constraints down onto that subdesign. Question 7. What is the design name of I_ALU? ALU Question 8. What sub-block has the WNS now? It is still the ALU block. Question 9. What blocks other than ALU have negative slack paths? PRGRM_CNT_TOP and the output ports (path goes through INSTRN_LAT, DATA_PATH and REG_FILE) Question 10. What are the DesignWare implementations in the design ALU? The implementations should be bk (Brent Kung), cla (carry look ahead) and clf (fast carry look ahead). Lab 15-12