Pipelined MIPS CPU Synthesis and On-Die Representation ECE472 Joseph Crop Stewart Myers

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1 Pipelined MIPS CPU Synthesis and On-Die Representation ECE472 Joseph Crop Stewart Myers 2008

2 Table of Contents Introduction... 3 Steps Taken and Simulation... 3 Pitfalls... 8 Simulated Delay... 9 APPENDIX A Synthesized Pipelined MIPS CPU APPENDIX B Pipelined MIPS CPU On-Die Representation APPENDIX C Encounter Configuration File APPENDIX D Synthesis Configuration Code APPENDIX E Pipelined MIPS CPU Verilog Code

3 Introduction This project involved the creation of an on-die representation of a pipelined MIPS CPU from code acquisition to synthesis to final die layout. Although we have had experience with ModelSIM and writing Verilog from other projects during this term, many of the tools required to complete the synthesis and on-die representation were completely new to us. We will explain all the steps taken to reach the final representation, how we simulated our pipelined CPU, the pitfalls we encountered and how we overcame them, and we will explain how we simulated the delay and what those delay values were. Steps Taken and Simulation 1. If you haven t already, create a test bench for your verilog code. 2. Place all of your.v files in the verilog_input folder. 3. Modify the dc_syn file inside of the synthesis folder to include all of your.v files read_verilog../verilog_input/file1.v read_verilog../verilog_input/file2.v 4. Change both of the current_ design parameter to contain the name of your test bench module. Also, make sure your test bench module has a clock input current_design mips_pipeline_testbench 3

4 5. Create a clock in the design: change the create_clock command to have the get_ports parameter to point you your clock register. Ours was named clk. create_clock clk -name cpu_clock -period 5 6. Change the names of the output files to something useful. write -format verilog -hierarchy -output../synthesized_verilog/pipeline_testbench.gate.v write_sdc../synthesized_verilog/pipeline_testbench.sdc 7. Open a terminal, navigate to the synthesis folder, and execute the following command. This starts the Design Vision program and creates gate-level synthesized verilog. If you don t have your current design listed as your test bench thing will go wring and you may or may not get errors. design_vision-xg -f dc_syn 8. After the Design Vision program loads choose Schematic -> New Design Schematic View. If not already selected, make sure your test bench is loaded in the drop-down box at the top of the screen. If you didn t set the current_design parameter correctly your test bench will load as a very small design instead of your whole cpu. 9. After ogling your cool design close Design Vision. 4

5 10. Make sure your gave-level verilog was synthesized correctly by running is in modelsim and verifying identical operation to your original code. It should be located in: synthesized_verilog/[name].gate.v 11. Three reports are generated from the synthesis, an area report, clock report and a delay report; they are placed in the synthesis/reports folder. Verify the clock was asserted correctly to you design by opening the clock report, you should see something like this: Clock Period Waveform Attrs Sources clk 5.00 {0 2.5} {clk} If the clock report looks correct, open the delay report. If it s wrong your test bench or synthesis configuration file are incorrect. The delay report will tell you if your selected clock period will work for the gate simulated gate delays from Design Vision. It should look something like this: Point Incr Path clock clk (rise edge) clock network delay (ideal) dut/wb_memtoreg_reg/ck (DFFTRX1MTH) 0.00 # 0.00 r data required time data required time 4.91 data arrival time slack (MET)

6 12. Change the directory in your shell to the encounter folder. 13. Edit encounter.conf in the encounter folder. 1. Make sure your.lib and.lef are pointed to correctly set rda_input(ui_timelib) "../cell_lib_files/scmetro_cms9flplvt_tt_1p2v_25c.lib" set rda_input(ui_leffile) "../cell_lib_files/lef/cms9flp_8lm_2thick_tech.lef../cell_lib_files/lef/cms9flplvt_m_macros.lef" 2. Make sure your test bench is your top cell! set rda_input(ui_topcell) "mips_pipeline_testbench" 3. Make sure your timing and netlist files are pointed to correctly set rda_input(ui_netlist) "../synthesized_verilog/[name].gate.v" set rda_input(ui_timingcon_file) "../synthesized_verilog/[name].sdc" 14. Run Cadence encounter! We found it in /usr/local/apps/cadence/soc/current/bin/encounter 15. Navigate to Design -> Design Import -> Load and select your encounter.conf file and click OK. You should see a black square with gray horizontal lines on the screen. 6

7 16. Add power rings by navigating to Power -> Power Planning -> Add Rings. Type "VSS VDD" into the "Net(s):" area, specify metal layers and ring width (We used Top/Bottom Metal5 and Left/Right Metal6), and select "center in channel". click update to see what values it is actually going to use. Click OK. 17. Add horizontal power buses by navigating to Route -> Special Route and clicking OK (the default values are usually acceptable). 18. Navigate to Place -> Standard Cells and click OK, this will place all of the standard blocks. This step can take a while so be patient. To make the cells show up by clicking on the "Physical View" button in the top right corner of the screen. 19. Now go to Edit -> Pin Editor and click on your clock(s) in the list of pins and change "USE:" to "CLOCK". 20. Add filler blocks to connect the power rails between the standard cells with Place -> Physical Cells -> Add Filler and click on select. Highlight all fillers and click "add". Then click Close and then click OK. This will add filler blocks, fitting the largest block it can into each hole. 21. To route the blocks run Route -> Nanoroute -> Route with the default options. Sometimes unnecessarily ugly routes will be taken, manually fix these to ensure a clean signal path if you would like. 22. Now run Timing -> Optimize with Post-Route selected. 7

8 23. Verify the layout by running Verify -> Verify Geometry, if there is a violation use Tools -> Violation Browser to see a list of the violations. Also run Verify -> Verify Connectivity to look for unconnected pins. 24. Export your design by running Design -> Save -> GDS/OASIS and specify a name such as counter.gds (the default options are sufficient). Then save the SOC Encounter design with Design -> Save Design As -> SoCE and click OK. Finally, exit SOC Encounter. 25. That s it! you re done! Pitfalls The first pitfall we encountered was simply trying to obtain Verilog source code that we could synthesize and model on-die. We visited opencores.org and viewed all the projects written in Verilog. Not only were there very few projects written in Verilog, but those that initially appeared suitable turned out to have been deleted, or contained notes to the effect there were still bugs to work out. After a couple of hours of searching, we decided to use our existing pipelined MIPS code from the final project. Thus we were able to move on to the synthesis phase. Synthesis is where we ran into the second pitfall. When synthesizing our Verilog code, we discovered that the current_design parameter in the Design View configuration file had to be changed to the name of our pipelined MIPS module. Failing to change that variable caused Design Vision to list all elements of our pipelined MIPS CPU, e.g. the rom32, the forwarding unit, etc., separately and would not combine them into an integrated chip. Apparently the program needed to know hierarchy of all elements of the 8

9 CPU and the current_design parameter serves as the entry point, overview file, of that hierarchy. We ran Design Vision many, many times before discovering this error. After synthesizing our CPU, we ran into a third major pitfall when trying to time the synthesized CPU in Design Vision. We began synthesis by using the pipelined testbench which contained a clock, but did not have a clock as input. When using the testbench, Design Vision said we had no clock and we couldn t time our CPU. We had to have an output Y and input A, then set them equal to each other on the posedge of the clock, along with running our MIPS pipeline module, and with no reset signal. For whatever reason, these changes added a clock to our synthesis and we could time the pipelined CPU. After synthesizing we were able to move on to the on-die representation phase where we encountered only minor, easily remedied issues such as forgetting to check or uncheck a dialog box entry, etc. All these issues were quickly taking care of by rereading the online tutorial. Simulated Delay Following is the report created by Design Vision on simulated delay: **************************************** Report : timing -path full -delay max -max_paths 1 Design : mips_pipeline_testbench Version: X SP2 Date : Fri Dec 12 14:29: **************************************** # A fanout number of 1000 was used for high fanout net computations. Operating Conditions: tt_1p2v_25c Library: scmetro_cms9flp-lvt_tt_1p2v_25c Wire Load Model Mode: top Startpoint: dut/wb_memtoreg_reg (rising edge-triggered flip-flop clocked by clk) Endpoint: dut/mem_zero_reg (rising edge-triggered flip-flop clocked by clk) Path Group: clk 9

10 Path Type: max Point Incr Path clock clk (rise edge) clock network delay (ideal) dut/wb_memtoreg_reg/ck (DFFTRX1MTH) 0.00 # 0.00 r dut/wb_memtoreg_reg/q (DFFTRX1MTH) f U335/Y (BUFX2MTH) f U970/Y (AO22X2MTH) f U258/Y (BUFX4MTH) f U282/Y (AOI22X1MTH) r U278/Y (OAI2BB1X2MTH) f U268/Y (AO22X2MTH) f dut/ex_alu/add_145/u1_2/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_3/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_4/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_5/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_6/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_7/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_8/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_9/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_10/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_11/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_12/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_13/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_14/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_15/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_16/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_17/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_18/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_19/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_20/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_21/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_22/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_23/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_24/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_25/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_26/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_27/co (ADDFX2MTH) f U272/Y (NAND2X1MTH) r U267/Y (NAND3X2MTH) f dut/ex_alu/add_145/u1_29/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_30/co (ADDFX2MTH) f dut/ex_alu/add_145/u1_31/y (XOR3X1MTH) f U251/Y (NAND2X1MTH) r U252/Y (OAI2B11X2MTH) f U269/Y (NOR2XLMTH) r U259/Y (NAND2XLMTH) f U289/Y (NOR2X1MTH) r dut/mem_zero_reg/d (DFFTRX1MTH) r data arrival time 4.90 clock clk (rise edge) clock network delay (ideal) dut/mem_zero_reg/ck (DFFTRX1MTH) r library setup time data required time data required time 4.91 data arrival time slack (MET)

11 APPENDIX A Synthesized Gate Level Pipelined MIPS CPU 11

12 APPENDIX B Pipelined MIPS CPU On-Die Representation 12

13 APPENDIX C Encounter Configuration File ################################################ # # # SOC Encounter Input configuration file # # # ################################################ global rda_input set rda_input(ui_netlist) "../synthesized_verilog/pipeline_testbench.gate.v" set rda_input(ui_timingcon_file) "../synthesized_verilog/pipeline_testbench.sdc" set rda_input(ui_topcell) "mips_pipeline_testbench" set rda_input(ui_netlisttype) {Verilog} set rda_input(ui_ilmlist) {} set rda_input(ui_settop) {1} set rda_input(ui_celllib) {} set rda_input(ui_iolib) {} set rda_input(ui_areaiolib) {} set rda_input(ui_blklib) {} set rda_input(ui_kboxlib) "" set rda_input(ui_timelib) "../cell_lib_files/scmetro_cms9flp-lvt_tt_1p2v_25c.lib" set rda_input(ui_smoddef) {} set rda_input(ui_smoddata) {} set rda_input(ui_dpath) {} set rda_input(ui_tech_file) {} set rda_input(ui_buf_footprint) {BUFX2MTH} set rda_input(ui_delay_footprint) {BUFX2MTH} set rda_input(ui_inv_footprint) {INVX1MTH} set rda_input(ui_leffile) "../cell_lib_files/lef/cms9flp_8lm_2thick_tech.lef../cell_lib_files/lef/cms9flplvt_m_macros.lef" set rda_input(ui_core_cntl) {aspect} set rda_input(ui_aspect_ratio) {1.0} set rda_input(ui_core_util) {0.7} set rda_input(ui_core_height) {} set rda_input(ui_core_width) {} set rda_input(ui_core_to_left) {30} set rda_input(ui_core_to_right) {30} set rda_input(ui_core_to_top) {30} set rda_input(ui_core_to_bottom) {30} set rda_input(ui_max_io_height) {0} set rda_input(ui_row_height) {} set rda_input(ui_ishortrackhalfpitch) {0} set rda_input(ui_isvertrackhalfpitch) {1} set rda_input(ui_ioori) {R180} set rda_input(ui_isorigcenter) {0} set rda_input(ui_exc_net) {} set rda_input(ui_delay_limit) {1000} set rda_input(ui_net_delay) {1000.0ps} set rda_input(ui_net_load) {0.5pf} set rda_input(ui_in_tran_delay) {120.0ps} set rda_input(ui_captbl_file) {} set rda_input(ui_cap_scale) {1.0} set rda_input(ui_xcap_scale) {1.0} set rda_input(ui_res_scale) {1.0} set rda_input(ui_shr_scale) {1.0} set rda_input(ui_time_unit) {none} set rda_input(ui_cap_unit) {} set rda_input(ui_sigstormlib) {} set rda_input(ui_cdb_file) {} set rda_input(ui_echo_file) {} set rda_input(ui_qxtech_file) {} set rda_input(ui_qxlib_file) {} set rda_input(ui_qxconf_file) {} set rda_input(ui_pwrnet) {VDD} set rda_input(ui_gndnet) {VSS} set rda_input(flip_first) {1} 13

14 set rda_input(double_back) {1} set rda_input(assign_buffer) {0} set rda_input(ui_pg_connections) [list \ {PIN:VDD:} \ {PIN:VSS:} \ ] set rda_input(pin:vdd:) {VDD} set rda_input(pin:vss:) {VSS} 14

15 APPENDIX D Synthesis Configuration Code #synopsys synthesis script set hdlin_auto_save_templates true set hdlin_check_no_latch true set hdlin_warn_sens_list true define_name_rules MYrules -map { {{"\\[", "_"}, {"\\]", "_"}} } read_verilog../verilog_input/out.v current_design mips_pipeline_testbench link ##### constraints are below ##### #erase all attributes and constrains from the current design reset_design #set wire loading mode to top #set_wire_load_mode top # Create clock with 5ns period create_clock clk -name clk -period 5 change_names -rules "MYrules" -hierarchy # Compile with completely disolved design compile -ungroup_all # Make sure we are at the top level set current_design mips_pipeline_testbench # Generate area and constraints reports on the optimized design report_area >./reports/area.rpt # Generate timing report for worst case path report_timing >./reports/delay.rpt report_clock >./reports/clock.rpt # Save the compiled design write -format verilog -hierarchy -output../synthesized_verilog/pipeline_testbench.gate.v write_sdc../synthesized_verilog/pipeline_testbench.sdc

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