Introduction to Design Compiler
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1 Introduction to Design Compiler Courtesy of Dr. An-Yeu +1 (479)
2 What is Synthesis Synthesis = translation + optimization We will get a gate level circuit with timing information after Synthesis 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 2
3 Design Compiler Initialize the environment: initrc dc-m Start Design Compiler: dc_shell: command line tool design_vision: GUI or by start_gui in dc_shell 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 3
4 Design Compiler Design Compiler maps Synopsys design block to gate level design with a user specified library Technology Library RTL Design timing info 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 4
5 Synthesis Design Flow Specification RTL Coding Prepare Setting Design Environment Setting Design Constraint Cell Library Compile Design Analysis Gate-level Netlist 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 5
6 Synthesis Design Flow Develop the HDL design description and simulate the design description to verify that it is correct. Set up the environment Set the appropriate technology, synthetic, and symbol libraries, target libraries, and link libraries. Set the necessary compilation options, including options to read in the input files and specify the output formats. Read the HDL design description Define the design. Set design attributes Set design rules Set realistic constraints (timing and area goals) Determine a compile methodology 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 6
7 Timing Library Timing library higher level abstract view of the timing and power of this circuit suitable for use by the ASIC tools. Essentially, these tools run many, many circuit-level simulations to create characterization data stored in a.lib (Liberty) file. This file is a text file Synopsys tool reads a binary format (.db) which is compiled from.lib file to accelerate the process 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 7
8 Timing Library What s inside (thousands of lines) cell (NAND3X0) { cell_footprint : "nand3x0 "; area : ; Std. cell general information cell_leakage_power : e+04;... pin (IN1) { fanout_load : ; direction : "input"; fall_capacitance : ; Pin information capacitance : ; rise_capacitance : ;... internal_power () { when : "!IN2&!IN3"; rise_power ("power_inputs_1") { Power information /* index_1 = input transition time */ index_1(" , , , , , , "); values (" , , , , , , "); } fall_power ("power_inputs_1") { /* index_1 = input transition time */ index_1(" , , , , , , "); values (" , , , , , , "); }. 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 8
9 Timing Library Continue pin (QN) { direction : "output"; power_down_function : "!VDD + VSS"; function : "(IN3*IN2*IN1)'";... timing () { related_pin : "IN1"; timing_sense : "negative_unate"; cell_rise ("del_1_7_7") { /* index_1 = input net transition time */ index_1("0.016, 0.032, 0.064, 0.128, 0.256, 0.512, 1.024"); /* index_2 = total output net capacitance */ Timing information index_2("0.1, 3.75, 7.5, 13, 26, 52, 104"); values( " , , , , , , ", \ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , "); } 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 9
![Initial Setup File->Setup [Using FreePDK45 Example] You will need initrc FreePDK45 before starting design compiler set_app_var search_path ".](/docs-images/87/97245971/images/10-2.jpg "$::env(pdk_dir)/osu_soc/lib/files $synopsys_root/libraries/syn/\" set_app_var link_library \"* gscl45nm.db\" set_app_var target_library \"gscl45nm.db\" set_app_var symbol_library \"generic.")
10 Initial Setup File->Setup [Using FreePDK45 Example] You will need initrc FreePDK45 before starting design compiler set_app_var search_path ". $::env(pdk_dir)/osu_soc/lib/files $synopsys_root/libraries/syn/" set_app_var link_library "* gscl45nm.db" set_app_var target_library "gscl45nm.db" set_app_var symbol_library "generic.sdb" If DesignWare Lib is used, add dw_foundation.sldb into link_library 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 10
11 Read File Read netlists or other design descriptions into Design Compiler File/Read Support many different formats: DDC (binary):.ddc Verilog:.v VHDL:.vhd EDIF 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 11
12 Analyze & Elaborate & Link File/Analyze The analyze command reads the Verilog RTL into an intermediate internal representation. File/Elaborate The elaborate command recursively resolves all of the module references starting from the top-level module also infers various registers and/or advanced data-path components. File/Link Design Link all parts together 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 12
13 Setting Design Environment Setting Design Environemnt: Operating Environment (a) Input Driving Strength (b) Output Loading (c) Input/Output Delay (d) Wire Load Model (e) (d) set_input_delay (b) set_driving_cell (a) Set_operating_conditions U1 U2 M1 (d) set_output_delay (c) set_load (e) set_wire_load_model 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 13
14 Setting Operating Condition Attributes/Operating Environment/Operating Condition (GUI) Maximum => slow ( setup time ) Minimum => fast (hold time) 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 14
15 Setting Input Drive Set input Attribute/Operating Environment/Drive Strength 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 15
16 Setting Output Loading(GUI) Attribute/Operating Environment/Load 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 16
17 Input/Output Delay Delay Calculation: clock cycle >= DFF clk-q delay + c + DFF setup Input delay = DFF clk-q delay + a Output delay = e + DFF setup 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 17
18 Command line Set operation conditions: set_operation_conditions min_library lib_name min condition max_library lib_name max condition Ex: set_operating_conditions -min_library fast -min fast -max_library slow -max slow Ex: set_operating_conditions -min_library fsd0a_a_generic_core_1d32vbc -min BCCOM -max_library fsd0a_a_generic_core_1d08vwc -max WCCOM Set driving cells set_driving_cell library max_lib_name lib_cell DFFX2 pin{q} [get_ports your_port] set_drive [drive_of max_lib_name/dffx2/q ] [get_ports your_port] Setting Output Loading set_load [load_of max_lib_name/dffx1/d ] [get_ports your_port] 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 18
19 Setting Input Delay Select input ports Attributes/Operating Environment/Input Delay Specify minimum input delay Specify maximum input delay 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 19
20 Setting Output Delay Select output ports Attributes/Operating Environment/Output Delay Specify minimum output delay Specify maximum output delay 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 20
21 Setting Wire Load Model Wire load model estimates wire capacitance based on chip area & cell fanout Setting this information during compile in order to model the design more accurately Attributes/Operating Environment/Wire Load 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 21
22 Design Constraints Constraints are goals that the Design Compiler uses for optimizing a design into target technology library. Design Rule Constraints : technology-specific restriction Ex: maximum transition, maximum fanout, maximum capacitance. Optimization Constraints : design goals and requirements Ex: maximum delay, minimum delay, maximum area, maximum power. During compile, Design Compiler attempts to meet all constraints. If constraints too tight, it may not meet those 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 22
23 Setting Design Constraints Optimization Constraints Basic clock constraints concept Constraint for Special Circuit Constraints for Power & Area Design Rule Constraints Final check constraints before compile 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 23
24 Define Clock Specification What should be defined? Period Waveform Uncertainty Skew Latency Source latency Network latency Transition Input transition Clock transition (option) All register-to-register path are constrained now 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 24
25 Specify Clock Constrains Select clock port Attributes/Clocks/Specify Combinational delay is constraint by: set_max_delay 10 -from all_input -to all_output Or create virtual clock create_clock -period 10 -name clk 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 25
26 Command Line creat_clock : define your clock s waveform & respect the set-up time requirements of all clocked flip-flops create_clock -name "CLK" -period 10 -waveform {0 5} [get_ports CLK ] set_fix_hold : respect the hold time requirement of all clocked flip-flops set_fix_hold [get_clocks CLK] set_dont_touch_network : do not re-buffer the clock network set_dont_touch_network [get_clocks CLK] 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 26
27 Setting Area&Power Constraint Attributes/OptimizationConstraints/Design Constraints Area Unit : Equivalent gate count um x um Transistors set_max_area 0 set_max_total_power 0.0uw set_max_dynamic_power set_max_leakage_power 0.0uw 0.0uw 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 27
28 Design Rule Constraints Vendors impose design rules that restrict how many cells are connected to one another based on capacitance, transition,and fanout You may apply more conservative design rules to: Anticipate the interface environment your block will see Prevent the design from operating cells close to their limits, where performance degrades rapidly DC respects design rules as highest priority of all in the following order: set_max_transition set_max_fanout set_max_capacitance 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 28
29 Check Design Check Design Execute check_design command before you optimize your design Some possible issues Error (bus width mismatch) Error: In design bcd7segs, cell decoder has more pins than it s reference d1 has ports Warnings (dangling ports) Warning: In design converter, port A is not connected to any nets Check Timing After setting constraints, verify that there are no remaining unconstrained paths: check_timing 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 29
30 Compile the Design The compile command optimizes and maps the current_design Design/Compile design compile -map_effort medium compile_ultra 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 30
31 Report Design & Timing Generating Reports Design / Report Timing / Report 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 31
32 Save the Design Write out the design netlist after synthesis 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 32
33 Check Constraints Use the following reports to check constraints before compiling Design/Report XXXX Report Design In this report you can check the operating condition and wire load model Report Clocks Notice that all the information about timing is at Timing/Report XXX 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 33
34 Report Design Report Design Hierarchy Hierarchy report shows the component used in your block & hierarchy Report Reference Reference report shows statistical result about reference in the design Report Net Net report shows the statistical results of each net Report Area Area report shows the um 2 of the design Report Power Power report shows the estimated power consumption Report Constraints Constraints report shows if compiled design meets your constraints 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 34
35 Generate Text Report Extract report data with command line redirect xxx_area.rpt { report_area } redirect xxx_power.rpt { report_power } redirect xxx_hierarchy.rpt { report_hierarchy } redirect xxx_nets.rpt { report_nets } redirect xxx_constraints.rpt { report_constraints } redirect xxx_reference.rpt { report_reference } 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 35
36 Report Timing Timing / Report Timing Path Fractional part length 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 36
37 Timing Report Timing report shows maximum or minimum delay path of design, the default is to display one maximum delay path (critical path) redirect xxx_timing.rpt { report_timing } 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 37
38 What is Slack Slack is the resulting margin between required & actual arrival time Positive slack or zero means meet constraints Negative slack means violate constraints Setup Time Check (max delay check) Slack_setup = Data Required Time Data Arrival Time Hold Time Check (min delay check) Slack_hold = Data Arrival Time - Data Required Time 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 38
39 Save Design Save your design to file before you quit Design Compiler File/Save saves your design in the ddc format File/Save As can save your design in other Write formats Verilog:.v VHDL:.vhd EDIF Synopsys DDC formats Timing Constraints:.sdc write -hierarchy -format ddc -output xxx.ddc write -hierarchy -format verilog -output xxx.v write_sdc xxx.sdc 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 39
40 Save Files Save gate-level netlist. File -> Save As Save your design. File - Save Save the timing information. File - Save Info - Design Timing, choose sdf format. write -format verilog -hierarchy -output "ALU_s.v" find (design, ALU) write -format db -hierarchy -output "ALU_s.db" find (design, ALU) write_sdf ALU_s.sdf Save script file with the constraints you have made. File - Save Info - Design Setup Re-run all steps automatically. File - Execute Script 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 40
41 Gate-Level Simulation (Verilog) Write out gate-level netlist File/Save As Verilog (for File format) dc_shell> write -format verilog hierarchy -output chip.vg Get SDF File/Save Info Design timing Select chip.sdf dc_shell> write_sdf version 2.1 -context verilog chip.sdf Modify your testbench file $sdf_annotate ( the_sdf_file_name, top_module_instance_name); Simulation with timing information back-annotated 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 41
42 Example Design Example: Adder64 (combinational) Script provided: dc_shell -f dc.tcl Lab4: Adder128 (combinational) Modify Adder64.v file to create 128 bit adder Compare synthesized results against 64bit adder FPGen (sequential with clock pin name clk, system verilog format) add dw_foundation.sldb into link_library analyze -format sverilog $systemverilogs current_design FPGen create_clock -period $myperiod_ns clk 11/2/2017 CSCE/ELEG 4914: Advnaced Digital Design 42
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