Processor Core Customization: Your SOC design team s fastest route from C to gates

Transcription

1 WHITE PAPER Processor Core Customization: Your SOC design team s fastest route from C to gates The manager s quick guide to leading your SOC design team out of verification Hell and toward a successful first-time tapeout SOC complexity has skyrocketed in the last several years thanks to the relentless application of Moore s Law. The result: a double-edged sword that allows SOC design teams to reach for the technological stars while, at the same time, being dragged into verification Hell. It need not be this way. The solution is remarkably familiar and easier than you might think. The state of SOC design How did we get here? Figure 1 shows the answer. The custom-ic revolution started with gate arrays in the early 1980s. Prior to the introduction of gate arrays, the development of custom chips was limited to a few companies that had the money and resources to develop their own ICs. Gate array vendors hid much of the complexity and cost of physical IC design and allowed logic-design teams to cast their designs in silicon instead of circuit boards. The result was electric. Many more companies could afford custom chips using the gate-array route and system complexity jumped. By 1990, with the introduction of logic synthesis, logic-design teams could tackle even more complex system designs by creating standard-cell ASICs. System complexity jumped again and the cost to use this design methodology also jumped, to accommodate the required EDA tools, but logic designers could still create ASICs while staying relatively aloof from the nitty gritty aspects of physical design. By the era of the SOC (essentially an ASIC with an on-chip processor, RAM, and ROM) and the advent of nanometer lithographies, the party started to wind down. Design complexities of many millions of logic gates meant that system designs were now very complex. Gate-level verification became a real burden. The cost and time required for verification started to approach that of the design itself.

2 Page 2 Figure 1: As custom IC design has evolved from gate arrays to multicore SOCs, verification as a component of overall development has grown to become larger than design in terms of cost and time. Now the industry is in the era of the multicore SOC and chip-level complexities have hit new highs. For many design projects, verification represents more than half of the development cost. Design is no longer the leading consideration. Something has clearly gone wrong. Usually, companies promising a solution to this growing problem invoke the phrase higher level of abstraction. But just what does that phrase mean and why will a higher abstraction level help? The starting point: algorithms The place to start is with the most fundamental part of system design: algorithm development. Systems are collections of independently and dependently operating algorithms. For example, a multimedia player uses one algorithm to decompress a media stream, another to decode the video into a series of images, and yet another algorithm to decode the audio into sound. Baseband radio chips employ a very large variety of algorithms such as FFTs and inverse FFTs, rake filters, Viterbi and Turbo decoders, etc. All systems are based on the execution of one or more algorithms. Algorithm development is the first step in the system-development process because it creates the building blocks needed to construct the system. The left side of Figure 2 illustrates a conventional path for getting from an algorithm to a piece of silicon. It s important to understand this path because it embodies that lower level of abstraction that s causing all the trouble.

3 Page 3 Figure 2: RTL-centric design, shown on the left, forces SOC engineers to manually implement designs at low abstraction levels. As system complexity increases, this approach becomes expensive and unwieldy. A processor-centric approach eliminates the low-level manual design and speeds the process of getting to a gate-level design. The left side of Figure 2 illustrates a flow that starts with the algorithm development. These days, algorithm development is done using C or C++ (or sometimes MATLAB). The resulting compiled code is proven on an inexpensive PC or, in some cases, an array of inexpensive PCs. When the algorithm is proven, it will usually exist as a floating-point model, which is then converted into a fixed-point model to ease the eventual conversion into a gate-level design. At that point, designers take the C or C++ code and manually translate it into a hardware description language (HDL) such as Verilog or VHDL. The HDL description is the language of logic synthesis, which represents the automated portion of the conventional flow that takes the design from C to gates. After the initial design, simulation indicates areas that can be optimized to meet performance, timing, or power goals. Much of this optimization is manual as well. Finally, when simulation and logic verification indicate that a design is correct and sufficiently

4 Page 4 verified, it s submitted for logic synthesis and then physical design. Much of this work becomes redundant and unnecessary when your design team uses hardware IP like a processor core. At this point, it s critical to note that much of the manual design effort goes into converting the algorithmic C or C++ code into HDL. Manual conversion is slow, error-prone, and consequently it s expensive. Also note that the algorithm is already coded and proven in C/C++. It already runs successfully on a processor. However, the C/C++ version of the algorithm run on a general-purpose processor or DSP may not meet one or more of the design s power/price/performance criteria and so further optimization is needed. If the criteria were all met by running the C/C++ algorithm code on a processor, there would be no need to develop hardware the processor would be enough. "There must be some way out of here," said the joker to the thief There is a middle path. It s called processor customization. This path has been open since the first days of SOCs, when processors first appeared on ASICs. As long as the silicon is going to be custom tailored for a specific application, the processor can be custom tailored as well. However, the relative lack of processor designers and the complexity of developing and maintaining an associated tool chain have stopped designers from using custom-tailored processors in the past. It hasn t been easy to create an efficient processor design that performs well and it s harder still to develop and support a software-development tool chain for a custom processor core. The costs for getting a custom-designed processor core and tools simply haven t been reasonable. If your SOC design team were to approach a conventional processor vendor and ask for a custom processor that efficiently ran a specific algorithm optimally along with the requisite software-development tools, they d get one of two answers. The first would simply be No. The second would be a cost quote that would make this alternative design approach economically out of reach. That s no longer true however. Automated tools are now available that allow logic designers and software developers specifically not processor designers to custom tailor processors for specific on-chip SOC tasks. The customized processors are optimized to run targeted algorithms faster than can general-purpose processors and DSPs because new registers and instructions have been added so that multiinstruction sequences become single-instruction sequences. Because they are guaranteed correct-by-construction, these processors require much less gate-level verification. Because all of the needed processing capability comes in one optimized IP core, design is simplified; There s no longer a need for a separate controller core and a DSP in many SOC designs that might have otherwise needed two processor cores. Fully automated processor-optimization tools can produce a custom processor directly from an algorithm s C/C++ source code in much less than a day. These optimized processor cores can be 3-10x faster than general-purpose processor cores, which is fast enough to satisfy many project needs. Further analysis and optimization performed by developers trained to use the customization tools (although still not

5 Page 5 processor designers) can run x faster and often reaches the speed of direct, gate-level RTL conversions. Yet the costs are similar to what you d expect to pay for non-optimized, general purpose processor cores that lack the application-specific optimizations and therefore require more clock rate or even a hardware assist to meet project performance goals. Your existing SOC-design team can do the job itself and can escape from the need to perform gate-level verification on millions of gates. That s effort and time saved and, the truth is, the faster your team gets from concept to chip, the better. You need that competitive design edge and your SOC design team deserves the tools they need to win. Contact us today.

6 Page 6 An Open Invitation To start your design team on that different path to successful tapeout, the path that avoids verification Hell, contact Tensilica for assistance. For more information on the unique abilities and features of the customizable family of Xtensa processor cores and associated development tools, see send an to sales@tensilica.com, or contact Tensilica directly at: US Sales Offices: Santa Clara, CA office: Scott Blvd. Santa Clara, CA Tel: Fax: San Diego, CA office: 1902 Wright Place, Suite 200 Carlsbad, CA Tel: Fax: Boston, MA office: 25 Mall Road, Suite 300 Burlington, MA Tel: x8352 Fax: International Sales Offices: Yokohama office (Japan): Xte Shin-Yokohama Building 2F , Shin-Yokohama, Kohoku-ku, Yokohama , Japan Tel: ( ) Fax: ( ) Israel: Amos Technologies Moshe Stein moshe@amost.co.il Beijing office (China HQ): Room 1109, B Building, Bo Tai Guo Ji, 122th Building of Nan Hu Dong Yuan, Wang Jing, Chao Yang District, Beijing, PRC Postcode: Tel: (86) Fax: (86) Taiwan office: 7F-6, No. 16, JiHe Road, ShihLin Dist, Taipei 111, Taiwan ROC Tel: Fax: Seoul, Korea office: 27th FL., Korea World Trade Center, 159-1, Samsung-dong, Kangnam-gu, Seoul , Korea Tel: Fax: UK office (Europe HQ): Asmec Centre Eagle House The Ring Bracknell Berkshire RG12 1HB Tel : Fax :