Hardware Implementation and Verification by Model-Based Design Workflow - Communication Models to FPGA-based Radio

Transcription

1 Hardware Implementation and Verification by -Based Design Workflow - Communication s to FPGA-based Radio Katsuhisa Shibata Industry Marketing MathWorks Japan 2015 The MathWorks, Inc. 1

2 Agenda Challenges on Wireless Communication System Design -Based Design Workflow Hardware Implementation by Code Generation Verification User Stories 2

3 Challenges on Wireless Communication System Design It s about Collaboration Encode Decode Modulati on Demodul ation DAC ADC RF / Analog Front- End Algorithms / System Verification / Test Digital Hardware RF / Analog Hardware 3

4 -Based Design Workflow Executable Specification -Based Design entry point Satisfies system requirements Double Precision / Floating Point in MATLAB and/or Simulink with Toolbox Elaboration Develop implementation friendly architecture in Simulink Convert to fixed-point using Fixed-Point Designer Implement by Code Generation Generate HDL code using HDL Coder Customize code generation to meet implementation goals (area, speed, etc.) Import custom and vendor IP Verification HDL Verifier HDL co-simulation FPGA-in-the-loop verification DPI-C generation for EDA-integrated verification System Requirements Executable Specification Elaboration Implement by Code Generation Verification Continuous Verification 4

5 A Typical Structure Executable Specification Data Source Component Algorithm Environment Analysis Component Algorithmic System-level Testbench Algorithm interacts with outside environment through other components Algorithm is stimulated with data source Algorithm performance is analyzed by system level metrics 5

6 Executable Specification / Elaboration Data Source Analysis Encode Decode Modulati on Demodul ation DAC ADC RF / Analog Front- End Environment Demodulation equalisation channel estimation Fixed Point model OFDM demodulation synch. equalisation channel estimation OFDM demodulation 6

7 Executable Specification / Elaboration with Simulink Simulink ing and Simulation Environment for -Based Design Multi-domain system design Visualize and Analysis Application specific Add-on Communications System Toolbox LTE System Toolbox Fixed-Point Designer Data type conversion from Floating point to Fixed point Analyze the conversion effect Recommend word length and rounding mode 7

8 Hardware Implementation by Code Generation Demodulation equalisation equalisation channel estimation channel estimation Fixed Point model OFDM demodulation OFDM demodulation synch. HDL Refine Algorithm/System for hardware implementation Should be bit/cycle accurate, Fixed Point data type required Debug / Review with Algorithm/System engineers Explore alternative options for better implementation Optimize resource utilization DSP unit, register, etc. Integrate with existing code / IP 8

9 Hardware Implementation by Code Generation From to Hardware by HDL Coder Data Source Analysis Algorithm Algorithmic System-level Testbench RTL HDL (VHDL, Verilog) Component Component HDL Coder Environment Generate HDL from MATLAB, Simulink and Stateflow Device independent code Readable / Synthesizable Verilog / VHDL supported Easy operation from GUI tool HDL Workflow advisor Create reports / Scripts Resource usability, traceability, etc. Compilation, Simulation and Synthesis 9

10 MATLAB & Simulink Support for HDL generation HDL Coder Over 200 blocks supported Core Simulink Blocks Basic and Array Arithmetic, Look-Up Tables, Signal Routing (Mux/Demux, Delays, Selectors), Logic & Bit Operations, Dual and single port RAMs, FIFOs, CORDICs Signal Processing Blocks NCOs, FFTs, Digital Filters (FIR, IIR, Multirate, Adaptive), Rate Changes (Up &Down Sample), Statistics (Min/Max) Communications Blocks Psuedo-random Sequence Generators, Modulators / Demodulators, Interleavers / Deinterleavers, Viterbi Decoders MATLAB Function Stateflow 10

11 HDL Workflow Advisor HDL Coder Step-by-step guidance through code generation process setup HDL code generation FPGA synthesis and analysis 11

12 Create Report and Scripts HDL Coder Documents generated code in an HTML report Resource Utilization Report Optimization Report Traceability Report HDL Coding Standard Report Generate scripts to control EDA tools Compilation, Simulation Synthesis Lint 12

13 Verification Integrating with other Verification Activities Verification is commonly cited as the single biggest cost in hardware design Significant investment in developing simulations for verification SystemVerilog and UVM test frameworks SystemC/TLM virtual platforms Shift towards model-based verification Enabling techniques like Constrained Random testing Reusable / Parameterized testbench Rather than recreate a behavioural model, we can reuse the assets developed in the system models in MATLAB & Simulink Maintains connection with earlier part of the flow Removes risk of manual error in test framework Avoids duplicating effort 13

14 Co-simulation with HDL simulators Data Source Component Co-simulation with 3 rd -party HDL simulator Algorithm Environment HDL code execution in 3 rd -party HDL simulator Analysis Co-Sim Component Flexible HDL sources Handwritten or generated code Algorithmic System-level Testbench HDL Verifier Automatic co-simulation Combined analysis and debugging in both simulators RTL HDL (VHDL, Verilog) HDL Verifier Reuse of existing testbench in MATLAB/Simulink 3 rd -party HDL Simulator 14

15 Advantages of Co-Simulation with HDL simulators No need to recreate testbench in HDL Reuse existing system level model as testbench Flexible testbench creation in Simulink Parameterized / Integrated multi-domain testbench Automatically generated co-simulation models and Wizards for legacy HDL code Easy configuration Visualize simulation result in MATLAB/ Simulink Better insight to the result 15

16 FPGA-in-the-Loop Verification Data Source Component FIL simulation with FPGA development board HDL code execution on FPGA Algorithm Environment Flexible HDL sources Handwritten or generated code Analysis FIL Component Algorithmic System-level Testbench MATLAB and Simulink Automated FIL Encapsulation of algorithm within GBit Ethernet MAC HDL Verifier Automatic handshaking HDL Verifier Reuse of existing testbench in MATLAB/Simulink 16

17 Advantages of FPGA-in-the-Loop Verification Flexible testbench creation in Simulink Parameterized / Integrated multi-domain testbench Re-use system level test bench for FPGA verification No need to recreate testbench in T&M hardware Building confidence that the algorithm works on real hardware No need to wait until other components become ready 17

18 FPGA-in-the-Loop supports more FPGA boards natively 35 Number of FPGA Boards Supported by FIL Xilinx VC Altera Cyclone V GT 5 0 Arrow SoCKit (Altera Cyclone V SoC) 18

19 System Verilog DPI-C Component Generation Reuse of models in SystemVerilog Testbench Data Source Analysis Algorithm Algorithmic System-level Testbench Component Component Environment Develop System components (IP and test benches) in Simulink and MATLAB, Simulate, and Verify Export Components as C code with SystemVerilog wrappers DPI-C DPI-C DPI-C DPI-C Integrate Components with components in the HDL Simulator SystemVerilog Testbench Environment HDL Verifier Simulink Coder Verify Verification of the complete system design! 19

20 Verification workflow using System Verilog DPI-C component Generation Generate C Code as DPI-C components for HDL testbench Hand-coded or Generated HDL code Reuse system-level for HDL verification HDL Simulator/System Verilog C Code(DPI) HDL Code 20

21 Advantages of System Verilog DPI-C component generation Generate System Verilog component directly from MATLAB/Simulink algorithms Available Parameterized component generation Small impact to existing EDA environment 21

22 Hitachi Drives Adoption of - Based Design Challenge Improve a fragmented workflow and reduce FPGA development time Solution Adopt -Based Design with MATLAB and Simulink Results Engineering headcount halved HDL verification accelerated Development time reduced by over 30% Link to article Development workflow after the introduction of -Based Design. We have adopted -Based Design with MATLAB and Simulink as our standard development workflow for FPGA design. As a result, we have improved communication between teams, reduced development time, and reduced risk by evaluating system performance early in the design process. Noritaka Kosugi, Kazuyuki Hori, Yuji Ishida, and Makoto Hasegawa Hitachi 22

23 Customer Presentation at MATLAB EXPO 2014 Generating code for FPGAs with HDL Coder to prototype future wireless communications systems. 23

24 Customer Presentation at MATLAB EXPO 2014 Development and Adoption of Algorithm & RTL-integrated Verification Platform 24

25 Summary Challenges on Wireless Communication System Design It s about Collaboration -Based Design Workflow Help your communication system project in Digital hardware implementation and verification Hardware implementation by Code Generation Help Digital hardware engineers Better collaboration with Algorithm/System Engineer, RF/Analog Engineer Optimize implementation by automatic / systematic exploration Verification by reusing MATLAB/Simulink model Co-simulation with HDL simulator FPGA-in-the-loop simulation System Verilog DPI-C Component generation This is a proven-workflow by User Stories 25