ICS 51: Introduction to Computer Organization

Transcription

1 ICS 51: Introduction to Computer Organization Sample problems for Quiz #4 ( Solution ) on Spring [Cache Design] Given a fully associative cache has 4 cache lines and each of them contains the following tag and block pairs. You job is to run a series of the load instructions on a simple processor which has 4 registers. This processor will also always replace the least recently used cache line to store a new item when the cache is full. At the initial state, the cache lines are ordered by the reversed order they are accessed, e.g. the cache line with tag 0 and block FA has been accessed most recently while the one with tag 6 and block has been accessed least recently. Assume the load instructions fetch data from a (8 x 8-bit) memory shown above, answer the following questions: a. How many cache hits and misses are for these instructions? 2 hits, 3 misses b. Assume a load with a cache hit needs 2 cycles, and a load with a cache miss needs 20 cycles. How many cycles are required to execute the above load instructions? 2 x x 20 = 64 cycles

2 2. [Cache Design] The target processor has a cache with 4 cache lines and a memory with 8 entries. You job is to run a series of the load instructions on this processor with 4 registers. Validity bit is 1 if the cache line is valid and 0 if it s invalid. This processor will also always replace the least recently used cache line (LRU) to store a new item when the cache is full. At the initial state, the least recently used cache line is denoted with LRU on the line next to the corresponding cache entry. At the beginning, the cache is partially filled and the registers are empty. Note: The LRU is the cache line that hasn t been used the longest, if a cache line is reused in a HIT, then it is recently used. a. For each instruction, show the changes in cache and the registers.

3 b. How many cache hits and misses are for these instructions? 2 Hits and 4 misses

4 3. [Cache/Memory Design] What is the final state of the memory after execution of following codes using the default value in the registers below? lw $R4, 5($R1) add $R1, $R2, $R3 sw $R1, 0($R3) add $R4, $R3, $R4 R1 R2 R3 R4 0xEF 0x02 0x12 0x34 Ans: 4. [ Instruction Set Architecture ] A simple processor was designed to support 100 instructions with the following instruction format. Assume all instructions are 16 bits. Each of them is performing an operation taking operands from two source registers and then storing the result to the destination register. Answer the following questions. a. How many bits are required to represent the opcodes? Ceil (log 2 100) = 7 b. How many bits are required to represent the operands? 16-7 = 9

5 c. How many bits are required to represent each operand? 9 / 3 = 3 d. What is the maximum number of registers does this processor have? 2 3 = 8 5. [ Instruction Set Architecture ] Given the memory values below and one target register R ( i.e. the result of each load is saved in the target register R), what values do the following instructions load in register R? Address Value Instruction Value of R Load immediate Load direct 20 Mem[20] = 40 Load indirect 20 Mem[mem[20]] = mem[40] = [ Instruction Set Architecture ] Assume a computer that has 32 8-bit registers, 128KB byte-addressable memory (meaning that each byte has a unique address) and can perform 130 distinct operations. Given the following register-memory instruction format: OP REG MEM (Hint: Note: OP stands for the code of the operation to be performed, REG stands for the index of the register to be used and MEM stands for the address of the 8-bit memory

6 words to be used.) How many bits are needed to properly express such an instruction? OP: ceil (log 2 (130)) = 8 REG: log 2 (32) = 5 MEM: log 2 (128KB) = log 2 (128 x 2 10 ) = log 2 (2 17 ) = 17 Total bits: = [ Instruction Set Architecture/ Addressing Modes] In ARM LC2K Assembly, determine the type of each of the following instructions in terms of addressing modes (direct, indirect, indexed, immediate) and instruction format (1,2,3-addressable, no address). Add R1, R2, R3 (R3 R1 + R2) Register direct, 3-addressable LW R1, R2, #100 (r2 mem[r1+100]) Indexed, 3-addressable J #1000 (unconditional jump to specified target address, i.e., #1000) Direct, 1-addressable JALR R1 (Unconditional jump to address in R1) Register Indirect, 1-addressable BEQ R1, R2, #1000 ( if R1=R2, goto to address #1000) Direct, 3-addressable