1DT157 Digitalteknik och datorarkitekt. Digital technology and computer architecture, 5p

Transcription

1 1DT157 Digitalteknik och datorarkitekt Digital technology and computer architecture, 5p

2 Homework #1 Tanenbaum Chapter 3 Problems 6,7,11,19,23 Submit electronically to the TAs:

3 Binary Numbers Appendix A

4 Finite Precision Numbers Numbers larger than 999 Negative numbers Fractions Irrational numbers Complex numbers

5 Radix Number Systems (1) The general form of a decimal number.

6 Radix Number Systems (2) The number 2001 in binary, octal, and hexadecimal.

7 Conversion from One Radix to Another(1) Decimal numbers and their binary, octal, and hexadecimal equivalents.

8 Conversion from One Radix to Another(2) Decimal numbers and their binary, octal, and hexadecimal equivalents.

9 Conversion from One Radix to Another(3) Examples of octal-to-binary and hexadecimal-to-binary conversion.

10 Conversion from One Radix to Another(4) Examples of octal-to-binary and hexadecimal-to-binary conversion.

11 Conversion from One Radix to Another(5) Conversion of the decimal number 1492 to binary by successive halving, starting at the top and working downward. For example, 93 divided by 2 yields a quotient of 46 and a remainder of 1, written on the line below

12 Conversion from One Radix to Another(6) Conversion of the binary number to decimal by successive doubling, starting at the bottom. Each line is formed by doubling the one below it and adding the corresponding bit. For example, 749 is twice 374 plus the 1 bit on the same line as 749.

13 Representing Negative Numbers Signed magnitude One s complement Two s complement Excess 2 m - 1

14 Negative Binary Numbers (1) Negative 8-bit numbers in four systems.

15 Negative Binary Numbers (2) Negative 8-bit numbers in four systems.

16 Binary Arithmetic (1) The addition table in binary.

17 Binary Arithmetic (2) Addition in one s complement and two s complement.

18 Overflow Overflow means that a number cannot be represented In Two s complement addition: If numbers are of opposite signs overflow cannot occur If numbers are of the same sign and the result is of different sign the overflow! Rule: carry in to sign bits!= carry out of sign bits

19 The Microarchitecture Level Chapter 4

20 The Data Path The data path of the example microarchitecture used in this chapter. Composed of an ALU, a shifter, a register file (incl. a decoder), two busses, memory interface, and logic control Can have arbitrary registers Ones presented here are for the book ISA (IJVM)

21 Memory Organization Logic diagram for a 4 x 3 memory. Each row is one of the four 3-bit words.

22 Memory Organization (2) (a) A noninverting buffer. (b) Effect of (a) when control is high. (c) Effect of (a) when control is low. (d) An inverting buffer.

23 Arithmetic Logic Unit Inputs: A, B Output: O Control Input: F0,F1, INC, ENA, ENB, INVA Control Output: Z, N, (V = XOR of the last 2 carries) Shift Unit: 2 control signals: SLL8, SAR1

24 ALU operations Useful combinations of ALU signals and the function performed.

25 Data Path Timing Timing diagram of one data path cycle.

26 Memory Operation MAR: memory address register MDR: data address register Read: Load MAR Signal read from memory Result arrives in MDR, next cycle Result cannot be used until cycle after Write Load MAR Load MDR Signal write to memory; done

27 Memory Operation Mapping of the bits in MAR to the address bus.

28 Program Fetch PC: program counter MBR: program instruction (byte because IJVM in book --- normally it would be 32 bits) Fetch cycle (read only) PC = PC +1 Signal Read to memory (fetch) Instruction comes in MBR next cycle Execute current MBR

29 Microinstructions The microinstruction format for the Mic-1. Describes completely ALL signals for 1 cycle

30 Microinstruction Control: The Mic-1 (1) The complete block diagram of our example microarchitecture, the Mic-1.

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32 Microcode Microcode implements all instructions as a sequence of cycles: a microroutine The instruction points to the entry point of the microroutine: MBR is a jump to the starting point of the microroutine that implements this instruction The microcode needs sequencing: MBR jump Explicit address of next microinstruction is given Can modify the explicit next address depending on ALU output control Can change the opcode (MBR) jump by ORing it with the explicit address Microcode sequencing is extremely simple (no MPC addition!)

33 Microinstruction Control: The Mic-1 (2) A microinstruction with JAMZ set to 1 has two potential successors.

34 Microinstructions and Notation All permitted operations. Any of the above operations may be extended by adding << 8 to them to shift the result left by 1 byte. For example, a common operation is H = MBR << 8.

35 Implementation of IJVM Using the Mic-1 (1) The microprogram for the Mic-1.

36 Implementation of IJVM Using the Mic-1 (2) The microprogram for the Mic-1.

37 Implementation of IJVM Using the Mic-1 (3) The microprogram for the Mic-1.

38 Implementation of IJVM Using the Mic-1 (4) The microprogram for the Mic-1.

39 Implementation of IJVM Using the Mic-1 (5) The microprogram for the Mic-1.