4. MICROPROGRAMMED COMPUTERS

Transcription

1 Structure of Computer Systems Laboratory No MICROPROGRAMMED COMPUTERS This laboratory work presents the principle of microprogrammed computers and an example of microprogrammed architecture, in two variants: the first uses horizontal microprogramming, and the second uses vertical microprogramming. The aim is to exemplify how to choose the format of microinstructions, to follow their execution, and to implement simple transfer, arithmetic and logical instructions with the microinstructions presented. 4.1 Principle of Microprogrammed Computers Introduction Microprogrammed computers are characterized by the fact that the control signals are combined in control words, each bit of a word representing a control signal. The succession of the control words which indicate the correct sequence of elementary operations (micro-operations) that should be executed for each instruction is stored in a control memory. Each control word in the control memory represents a microinstruction, and it executes one or more micro-operations. The sequence of microinstructions form a microprogram. The main difference between a computer with hardwired control unit and one with microprogrammed control unit consists in the way in which the control unit passes from a state to another in order to generate the control signals: In a hardwired unit, a state corresponds to a phase, characterized by the activation of a phase signal. In a phase, certain control signals are generated that are required to execute an instruction. In a microprogrammed unit, a state corresponds to a microinstruction, which encodes the micro-operations that should be executed during the same clock cycle. To execute an instruction of the computer, a sequence of microinstructions must be executed. A microprogrammed control unit has two main functions: The control function, which defines the micro-operations that should be executed. This definition usually comprises the selection of the operands, selection of the operation to be executed, selection of the destination for a result, etc. The sequencing function, which defines the address of the next microinstruction to be executed. This definition refers to identifying the source for the next address, controlling the test conditions, or generating the address value directly Horizontal and Vertical Microprogramming In horizontal microprogramming, a microinstruction contains the following main fields (Figure 4.1):

2 2 Structure of Computer Systems Laboratory No. 4 Figure 4.1 General format of a horizontal microinstruction. One or more control-signal fields, which activate the control signals of the circuits; The address field, which contains the address of the next microinstruction that will be executed if a certain condition is true. If this condition is false, the next microinstruction from the control memory will be executed. The condition field, which selects the next microinstruction that will be executed. There is one bit for each internal CPU control signal, and one bit for each system bus control signal. The condition field indicates the condition in which a branch is executed in the microprogram, and the address field contains the address of the next microinstruction to be executed when a branch is taken. Such a microinstruction is interpreted as follows: 1. To execute the microinstruction, all the control signals indicated by a bit of 1 in the controlsignal field are activated, and all the control signals indicated by a bit of 0 are deactivated. The activated control signals will determine the execution of one or more micro-operations. 2. If the condition indicated by the condition field is false, the next microinstruction in the microprogram is executed. 3. If the condition indicated by the condition field is true, the microinstruction indicated by the address field is executed. The horizontal microprogramming is also called hardware microprogramming. In this case, the length of the microinstructions is high, and they control many hardware resources operating in parallel. To each resource of the computer a field or bit is assigned, by which the resource is controlled. The meanings of the microinstruction fields do not depend on the meanings of other fields. None of the fields can have two or more different meanings for identical values contained by that field. The disadvantage of horizontal microprogramming is that the bits of the microprogram word cannot be used efficiently. Not all microinstructions allocate useful meanings to all the available fields. A microprogram word with fewer bits can be designed, so that the meanings of the bits will depend on the particular microinstruction. At one extreme, a microprogram word with only two fields can be obtained: the first field contains a code which indicates the meaning of the second field. This type of microprogramming is called vertical microprogramming. All the resources of the computer are controlled by the same field at different times, indicated by the code field. The structure of a computer using vertical microprogramming may be simple, but the speed of execution reduces proportionally with the number of distinct meanings of the code field in the microinstruction. The vertical microinstructions execute simple operations, such as: load, store, add, branch. This type of microinstructions are similar to the machine-language instructions, which contain an opcode and one or more operands; this is the reason why vertical microprogramming is also called software microprogramming. In practice, diagonal microinstructions are used, which combine the characteristics of horizontal and vertical microinstructions: they have an enhanced capability to simultaneously control the hardware resources of the computer, and, in the same time, they are easy to understand and to implement.

3 Structure of Computer Systems Laboratory No. 4 3 The length of a microinstruction depends not only on its type (horizontal or vertical), but also on the encoding degree. The simplest microinstruction is not encoded at all, so that a control signal is assigned to each bit. This solution offers the maximum flexibility, because changing a microprogram only requires to change the contents of the control memory. The encoding on groups implies to combine in different fields the bits that control the mutually exclusive resources of the computer. To each field a decoder is attached. At the other extreme, the microinstruction could be completely encoded. This solution requires a minimum number of bits for the microinstruction word, but the flexibility offered is also minimal Structure of a Microprogrammed Control Unit Figure 4.2 presents the main elements of a microprogrammed control unit. Figure 4.2. Block diagram of a microprogrammed control unit. The microinstructions are stored in the control memory. The control address register contains the address of the next microinstruction to be read. When a microinstruction is read from the control memory, it is transferred to the control buffer register. This register activates the control signals. Reading a microinstruction from the control memory has the effect of executing that microinstruction. The sequencing logic loads the control address register and activates the read signal. Compared to a hardwired control unit, the microprogrammed control unit has the same inputs (instruction register, ALU flags, clock signal) and outputs (control signals). The control unit operates as follows: 1. To execute an instruction, the sequencing logic activates the READ signal for the control memory. 2. The word whose address is specified in the control address register is read into the control buffer register.

4 4 Structure of Computer Systems Laboratory No The contents of the control buffer register activate the control signals and generate nextaddress information for the sequencing logic. 4. The sequencing logic loads a new address into the control address register based on the nextaddress information from the control buffer register and the ALU flags. Figure 4.2 shows two decoders. The first decoder translates the opcode in the instruction register into a control memory address. The second decoder is not used for horizontal microinstructions, but it is used for vertical microinstructions. This decoder translates the code which indicates the action to be performed by the microinstruction into individual control signals. The control memory may be a ROM or a RAM. In the latter case, the contents of this memory may be changed under the control of the microprogram, resulting in a dynamic microprogramming. A structure of this type is usually called Writable Control Store and allows the user to load its own microprograms in order to extend the existing instruction set. Some structures have a mixed configuration, and contain both a ROM and a RAM. Part of the microinstructions are fixed, and others are temporarily stored in RAM. If a certain instruction must be executed and its associated microprogram is not found in RAM, this microprogram has to be loaded into a free area in memory. In this case, a possibility must exist to load the microprogram at any memory address. The branch addresses in such a microprogram should be relative rather than absolute. The main advantage of using the microprogramming to implement a control unit is that it simplifies the design of the control unit. A hardwired control unit must contain complex logic for sequencing micro-operations of the instruction cycle. On the other hand, the decoders and sequencing logic used in a microprogrammed control unit are very simple. The main disadvantage of microprogrammed control units is that they are slower than the hardwired units of comparable technology. Usually, a microinstruction is executed in two clock cycles, required to read the microinstruction and to activate the control signals. In a computer with hardwired control unit, each micro-operation is executed in one clock cycle. There are several solutions to increase speed, such as the following: Using a control memory with a reduced access time; Overlapping execution of the current microinstruction with loading of the next microinstruction from the control memory; Reducing the number of microinstructions by executing several concurrent operations during a microinstruction cycle; Combining microprogramming with hardwired control, so that each microinstruction will generate a control sequence for several micro-operation cycles Example of Computer with Horizontal Microprogramming Datapath Structure The microarchitecture presented as example (Figure 4.3) contains 16 registers. At the instruction (macroinstruction) level the following registers are accessible: PC AC SP Program Counter; Accumulator register; Stack Pointer. The other registers are only accessible at the microprogramming level. These registers are the following: IR Instruction Register; TIR Temporary Instruction Register; 0, +1, -1 Registers that store the constants 0, +1, and 1, respectively;

5 Structure of Computer Systems Laboratory No. 4 5 AMASK, BMASK Registers that store masks used to extract the various fields from the instruction word; A, B,..., F Registers with no specific functions. Each register may place their contents onto the A and B buses, and each register may be loaded from the C bus. The A and B buses are connected to the inputs of the ALU, which may perform the following functions: A + B; A AND B; A; NOT A. The ALU function is selected by the F 0 and F 1 signals. The ALU generates two condition flags: N (Negative) and Z (Zero). Figure 4.3. Example of microarchitecture. The ALU output is connected to the shifter, which can shift to the right or to the left with one position. It is possible to shift a register R to the left with two positions by computing the sum R+R and

6 6 Structure of Computer Systems Laboratory No. 4 shifting the sum to the left with one position. The function of the shifter is selected by the S 0 and S 1 signals. The A and B buses are connected to the ALU through two latches, LA and LB. These latches are needed because the ALU is a combinational circuit that calculates continuously the output for the current inputs and the selected function. This organization can cause problems for instructions such as A := A+B. After storing the result in A, the value on the A bus changes, which determines the output of the ALU and the value on the C bus to change also. Consequently, the erroneous value may be stored in A. By inserting latches on the A and B buses, they will store the initial values A and B, so that the ALU is protected from the changes on the buses when a new value is stored in a register. The load of LA and LB latches is controlled by the L 0 and L 1 signals, respectively. For communication with the memory, the microarchitecture contains two registers: MAR (Memory Address Register) and MBR (Memory Buffer Register). MAR can be loaded from LB, in parallel with an ALU operation; this loading is enabled by the M 0 signal. MBR can be loaded with the output of the shifter in parallel with, or in place of, storing the result in a register; the enable signal is M 1. Writing into memory from MBR is enabled by the M 2 signal, and reading from memory in MBR is enabled by the M 3 signal. The data read from memory may be applied to the left input of the ALU through the AMUX multiplexer. The A 0 signal determines whether LA or MBR is applied to the input of ALU Microinstruction Format To establish the format of horizontal microinstructions, first all the signals needed to control the datapath must be determined. These signals can be divided into the following functional groups (the number of signals in each group is shown): 16 Load of bus A; 16 Load of bus B; 16 Load registers from bus C; 2 Control of latches LA and LB (L 0, L 1 ); 1 Control of AMUX (A 0 ); 2 Control of ALU function (F 0, F 1 ); 2 Control of shifter (S 0, S 1 ); 4 Control of MAR and MBR (M 0, M 1, M 2, M 3 ); 2 Read and write from / to memory (RD, WR). As an initial solution, a 61-bit control register may be used, with one bit for each control signal. The number of bits needed to control the datapath may be reduced with the cost of increasing the number of circuits. The control information for bus A may be encoded on 4 bits, using a decoder to generate the 16 control signals. The control information for bus B may be encoded similarly. For bus C, it is possible to store a value in several registers, but this feature is not useful in practice. Therefore, the control information for bus C may also be encoded. The number of signals reduces with 3 12 = 36, so that 25 signals will be needed. The L 0 and L 1 signals may be replaced with the clock signal, since these signals are always needed. Then the number of signals would be 23. An extra signal that may be useful is a signal that enables or disables to store the contents of bus C into the registers. In some circumstances, it is desirable to perform an ALU operation in order to set the status flags N and Z, without storing the result of the operation. This signal is denoted by ENC (ENable C). The number of control signals is now 24. The RD signal may be used to control the load of MBR from the system bus (instead of the M 3 signal), and the WR signal may be used to control the transfer of MBR to the system bus (instead of the M 2 signal). This observation reduces the number of independent signals to 22. Figure 4.4 shows a possible microinstruction format, which contains two additional fields: COND and ADDR. The microinstruction contains the following 13 fields: AMUX Control the left input of the ALU: 0 = LA; 1 = MBR.

7 Structure of Computer Systems Laboratory No. 4 7 COND Branch condition: 00 = no branch; 01 = branch if N = 1; 10 = branch if Z = 1; 11 = unconditional branch. ALU ALU function: 00 = A+B; 01 = A AND B; 10 = A; 11 = NOT A. SH Shifter function: 00 = no shift; 01 = shift right; 10 = shift left. MBR Load MBR from the shifter: 0 = no load; 1 = load. MAR Load MAR from LB: 0 = no load; 1 = load. RD Memory read: 0 = no read; 1 = load MBR from memory. WR Memory write: 0 = no write; 1 = write MBR into memory. ENC Control the store of results in registers: 0 = no store; 1 = store. C Select the destination register, if ENC = 1: 0000 = PC, 0001 = AC, 0010 = SP etc. B Select the source for bus B: 0000 = PC, 0001 = AC, 0010 = SP etc. A Select the source for bus A: 0000 = PC, 0001 = AC, 0010 = SP etc. ADDR Branch address (0-255). Figure 4.4. Format of horizontal microinstructions Microinstruction Sequencing A basic ALU cycle consists of loading the LA and LB latches, performing the operation by the ALU and the shifter, and storing the result. For a correct sequencing of the operations, a clock with 4 phases (sub-cycles) is used. The operations in each phase are the following: 1. The next microinstruction to be executed is loaded into the control buffer register. 2. The contents of the source registers are placed onto the A and B buses and these contents are stored into LA and LB. 3. When the inputs are stable, the ALU and the shifter generate a stable output and MAR is loaded, if it is required. 4. When the shifter s output is stable, the contents of the C bus are stored into the destination register and MBR is loaded, if these operations are required. A control section is added to the datapath. The detailed block diagram is shown in Figure 4.5. The control memory CM is a fast memory that stores the microinstructions. The microinstructions are 32-bit wide, and the addressing space is 256 words. The control address register is MPC (Micro Program Counter), and the control buffer register is the microinstruction register MIR. In phase 1 the microinstruction register MIR is loaded from the control memory. In phase 2 the contents of MIR are stable, and its various fields control the datapath. The DEC A and DEC B decoders perform a 4:16 decoding of each field, to control the signals that enable the outputs of registers. In the same phase, the clock signal activates the LA and LB latches, and supplies stable inputs for the ALU. While the data are placed onto the A and B buses, the MPC is incremented to generate the address of the next microinstruction. In phase 3 the ALU and the shifter generate stable results. Although the ALU is a combinational circuit, the time needed to generate the result is determined by the carry propagation time, and not by the gate delays. In phase 4 the contents of the C bus may be stored into the working registers and into MBR. The DEC C decoder has as input the ENC field, the fourth line of the clock generator and the C field, generating 16 control signals. A register is loaded if the following conditions are met: ENC = 1; The current phase is 4;

8 8 Structure of Computer Systems Laboratory No. 4 The register is selected by the C field. The MBR is also loaded in phase 4 if the MBR field is 1. Figure 4.5. Detailed block diagram of the architecture that uses horizontal microprogramming. A mechanism is needed to allow conditional branches. For this reason, two fields are present in each microinstruction: ADDR, which is the address for the potential successor of the current microinstruction, and COND, which determines whether the next microinstruction is loaded from the microprogram counter MPC or from the ADDR field. Each microinstruction contains a potential branch, because branches are frequently used in microprograms. By allowing each microinstruction to have two potential successors, the execution speed is increased. The selection of the next microinstruction is performed by the microsequencer circuit (MS) during phase 4, when the N and Z status flags of the ALU are valid. The MS circuit combines the N and Z flags with the two bits of the COND field in order to generate an output signal. The output of the MS circuit controls the MMUX multiplexer. Access to memory requires a considerably longer time than the time required to execute a single microinstruction. For the example to be more realistic, we assume that if a microinstruction begins a memory read operation by activating the RD signal, this signal must also be active during the next microinstruction executed. Data becomes available after two microinstructions from the moment when the read operation is initiated.

9 Structure of Computer Systems Laboratory No The Microassembly Language To write microprograms, a symbolic language is needed. A possible notation is to specify a microinstruction in each line, by indicating each field that contains a non-zero value. For example, to add the AC and A registers and to store the result into the AC register, we may write: ENC = 1, C = 1, B = 1, A = 11 Another possibility is to use a notation in the style of a high-level language. In the microprogramming language chosen, named MAL, notations similar to the Pascal language are used. Storing a value into a register is denoted by an assignment instruction. The previous example becomes: ac := ac + a; To indicate the operation performed by the ALU, we may write: ac := ac + a; a := band (ir, amask); ac := a; a := inv (a); {add} {logical AND} {identical function} {logical NOT} The shift operations are denoted by the lshift and rshift functions, for example, tir := lshift (tir + tir); Unconditional branches are indicated by the goto instruction. Conditional branches may test the N or Z flag, for example: if n then goto 15; The assignments and branches can be combined in the same line. In order to test a register without storing it into another register, we introduce the alu pseudo-variable. To this pseudo-variable a value may be assigned, that is applied to one of the inputs of the ALU, for example: alu := tir; if n then goto 40; The TIR is passed unchanged through the ALU by selecting the identical function, so that the most significant bit may be tested. Using the alu variable implies ENC = 0. The memory read and write operations are indicated by rd and wr, respectively. The order of the different parts of the source lines is arbitrary. Each line is labeled with the memory address. Table 4.1 presents examples of horizontal microinstructions in the microassembly language MAL. The contents of the microinstruction fields are also indicated. Table 4.1. Examples of horizontal microinstructions in the MAL language. Microinstruction A M U X C O N D U A L S H M B R M A R R D W R E N C C B A mar:=pc; rd; rd; ir:=mbr; pc:=pc+1; mar:=ir; mbr:=ac; wr; alu:=tir; if n then goto 9; ac:=inv(mbr); tir:=lshift(tir); if n then goto 25; alu:=ac; if z then goto 22; ac:=band(ir,amask); goto 0; tir:=lshift(ir+ir); if n then goto 30; A D D R

10 10 Structure of Computer Systems Laboratory No Example of Computer with Vertical Microprogramming To clarify the difference between horizontal and vertical microprogramming, we redesign the microarchitecture in order to use vertical microinstructions Vertical Microinstructions Vertical microinstructions will contain three fields of 4 bits each. The first field, denoted by OP, contains the operation code. The other two fields are denoted by R1 and R2, and they specify two registers. The R1 field controls both the A and C buses. For branch microinstructions, the R1 and R2 fields are combined to form a single 8-bit field, denoted by R. Each vertical microinstruction performs a single function. Different microinstructions are needed for the ALU operations, memory read and write, branches, since the fields that control these functions are no longer present. The list of the vertical microinstructions is presented in Table 4.2. Table 4.2. The list of vertical microinstructions. Opcode Mnemonics Meaning Operations 0000 ADD Add r1:=r1+r AND Logical AND r1:=r1 AND r MOVE Transfer between registers r1:=r COMPL Logical NOT r1:=inv(r2) 0100 LSHIFT Shift left r1:=lshift(r2) 0101 RSHIFT Shift right r1:=rshift(r2) 0110 STMBR Store MBR into a register r1:=mbr 0111 TEST Test register if r1<0 then n:=1, if r1=0 then z:= BEGRD Begin read mar:=r1; rd 1001 BEGWR Begin write mar:=r1; mbr:=r2; wr 1010 CONRD Continue read rd 1011 CONWR Continue write wr 1100 JUMPN Jump if N = 1 if n then goto r 1101 JUMPZ Jump if Z = 1 if z then goto r 1110 JUMP Unconditioned jump goto r Structure of the Control Section The datapath is identical to that of the architecture with horizontal microprogramming. The structure of the control section is modified (Figure 4.6). Most of the control section is the same. The control memory and the microinstruction register MIR contain 12-bit words. The 4:16 decoders DEC R1 and DEC R2 for the R1 and R2 fields are similar to that for the A, B, and C fields of the horizontal microinstructions. The main differences are represented by the circuits denoted by AND, NZ, and DEC OP. The AND circuit is required because the R1 field now controls both the A and C buses. The A bus is loaded during phase 2, but the registers may be loaded from the C bus only when the contents of the LA and LB latches are stable, in phase 3. The logical AND function is performed between the 16 signals decoded by the DEC R1 circuit, the clock signal of phase 4, and a signal from the DEC OP circuit, signal that is equivalent to the former signal ENC. The result is that the 16 signals which enable loading the data into the registers are activated in the same conditions as when horizontal microinstructions were used.

11 Structure of Computer Systems Laboratory No Figure 4.6. Detailed block diagram of the architecture that uses vertical microprogramming. NZ is a 2-bit register used to store the N and Z flags of the ALU. Storing these flags is required because the ALU will perform the operation during a microinstruction, but the status flags will be tested only during the next microinstruction. Since ALU does not contain internal storage, and the status flags are updated after each new operation of the ALU, the value of the flags may be lost if they are not stored. The DEC OP circuit has as inputs the 4 bits of the OP field, and generates 13 distinct signals that control the AND circuit, the microsequencer circuit MS, the NZ circuit, the AMUX multiplexer, the ALU, the shifter SH, the MAR and MBR registers. The DEC OP circuit also generates the RD and WR signals. For each microinstruction, we must determine which of the 13 control signals are active. There are two signals to control the ALU, the shifter and the microsequencer, which are denoted with the indexes 0 and 1. The values of the signals generated by the DEC OP circuit for each microinstruction are presented in Table 4.3. For example, microinstructions ADD, AND, MOVE and COMPL use the add function, the logical AND function, the identical function, and the logical NOT function of the ALU. The ALU function is selected by the ALU 1 and ALU 0 signals. As an example, the BEGRD microinstruction uses the identical function of the ALU, loads the MAR and activates the RD signal. In order to have a compatibility between the two microsequencer circuits used for the two variants of the microarchitecture, the MS 1 and MS 0 signals have to be 00 for the case when there is no jump, 01 for a jump conditioned by the N flag (JUMPN), 10 for a jump conditioned by the Z flag (JUMPZ), and 11 for an unconditioned jump (JUMP).

12 12 Structure of Computer Systems Laboratory No. 4 Table 4.3. The control signals generated by the DEC OP circuit. Opcode Mnemonics ALU 1 ALU 0 SH 1 SH 0 NZ AMUX AND MAR MBR RD WR MS 1 MS ADD AND MOVE COMPL LSHIFT RSHIFT STMBR TEST BEGRD BEGWR CONRD CONWR JUMPN JUMPZ JUMP For writing microprograms using vertical microinstructions, either a notation typical for an assembly language or a language similar to MAL may be used. Note that the MAL instruction of the form alu:=register uses the TEST microinstruction to set the N and Z flags Applications Run the simulator for the architecture that uses horizontal microprogramming (MICRO.EXE). Follow the execution of a sequence of horizontal microinstructions Suppose that the microarchitecture with horizontal microinstructions is part of the didactic computer from Laboratory No. 1. Implement various instructions of the didactic computer using the existing horizontal microinstructions Choose a minimal instruction set of the didactic computer and encode the instructions of this set. Write the microprogram which decodes the instructions from the chosen set, using horizontal microinstructions Extend the instruction set of the didactic computer with a multiply instruction and a divide instruction. Write the microinstruction sequences which implement these instructions Rewrite the sequences that implement the instructions of the didactic computer using vertical microinstructions.