LECTURE - 4 Programming MSP430 using Code Composer Studio(CCS)

Transcription

1 LECTURE - 4 Programming MSP430 using Code Composer Studio(CCS) Atul Lele, Ramakrishna Reddy K, MSP430 Design, Texas Instruments India Pvt Ltd. 2/16/2012 1

2 Outline of today s session What have we learnt in the last session Agenda for this session Programming in Assembly, C, Assembly + C Interrupt processing Digital IO MSP430 Tool chain Lab 1: Building a CCS project for blinking a LED Lab2A: Using polled flags to determine an interrupt event Wrap-Up Q&A 2/16/2012 2

3 What have we learnt in the last session 2/16/2012 3

4 What have we learnt in the last session TI Embedded Processing Portfolio MSP430 Generations MSP430 Roadmap F2xx Key Features F4xx Key Features F5xx Key Features MSP430 Peripherals Overview

5 Programming in Assembly, C, Assembly + C 2/16/2012 5

6 Standard Definitions WDTCTL = 0x5A80; WDTCTL = 0xA580; WDTCTL = 0xA540; WDTCTL = WDTPW + WDTHOLD; // Hold watchdog timer // Hold watchdog timer Standard definitions make code easier to read and debug Peripheral bit definition files are included with all tools

7 Important definitions Emulate = imitate the function of another system e.g., An FPGA loaded with say 8051 VHDL code, behaving like a real 8051 device (at least functionally if not timing accurate) Memory mapped I/O, in which CPU instructions used to access memory are also used to access peripherals Port mapped (or IO mapped) I/O uses a special class of CPU instructions specifically for performing I/O e.g., IN, OUT instructions in 8085

8 Using Assembly in IAR #include <msp430f2013.h> ORG 0xF800 RESET: mov.w #0280h,SP ; Initialise stack pointer SetupWDT mov.w #WDT_MDLY_32,&WDTCTL ; WDT ~30ms interval timer bis.b #WDTIE,&IE1 ; Enable WDT interrupt SetupP1 bis.b #001h,&P1DIR ; P1.0 output Mainloop bis.w #CPUOFF+GIE,SR ; CPU off, enable interrupts nop ; Required only for debugger ; WDT_ISR; Toggle P1.0 ; xor.b #001h,&P1OUT ; Toggle P1.0 reti ; ; ; Interrupt Vectors ; ORG 0FFFEh ; MSP430 RESET Vector DW RESET ; ORG 0FFF4h ; WDT Vector DW WDT_ISR ; END

9 Using Assembly in CCS.cdecls C,LIST, "msp430x20x3.h".text ;program start RESET: mov.w #0280h,SP ; Initialise stack pointer SetupWDT mov.w #WDT_MDLY_32,&WDTCTL ; WDT ~30ms interval timer bis.b #WDTIE,&IE1 ; Enable WDT interrupt SetupP1 bis.b #001h,&P1DIR ; P1.0 output Mainloop bis.w #CPUOFF+GIE,SR ; CPU off, enable interrupts nop ; Required only for debugger ; WDT_ISR; Toggle P1.0 ; xor.b #001h,&P1OUT ; Toggle P1.0 reti ; ; ; Interrupt Vectors ; sect ".int10" ; WDT Vector.short WDT_ISR ;.sect ".reset" ; MSP430 RESET Vector.short RESET ;.end

10 C for MSP430 Using Bit masks if ( (P1IN & BIT1) == 0) { //Actions when P1.1 == 0 } else { //Actions when P1.1!= 0 } Where BIT1 = P1OUT = BIT1 // set P1OUT.1 P1OUT &= ~BIT1 // clear P1OUT.1 TACTL = MC_2 TASSEL_1 TACLR // more than one bit changed at a time

11 Using C (same for IAR and CCS) #include <msp430f2013.h> void main (void) { // WDTCTL = WDTPW WDTTMSEL WDTCNTL ; // WDT ~30ms interval timer WDTCTL = WDT_MDLY_32; // Set Watchdog Timer interval to ~30ms IE1 = WDTIE; // Enable WDT interrupt P1DIR = 0x01; // Set P1.0 to output direction bis_sr_register(lpm0_bits + GIE); // Enter LPM0 w/ interrupt } // Watchdog Timer interrupt service routine #pragma vector=wdt_vector interrupt void watchdog_timer(void) { P1OUT ^= 0x01; // Toggle P1.0 using exclusive-or } BIS_SR(LPM0_bits+GIE) = _low_power_mode_0()

12 Mixing C and Assembly Check first to see whether an intrinsic function is available ( see intrinsics.h ) Ex : swap_bytes( ) calls the swpb instruction Few more : enable_interrupt( ) disable_interrupt( ) Inline assembly, asm( mov.b &P1IN, &dest ) Note double underscore Write a complete subroutine in assembly and call it from C

13 Interrupt Processing 2/16/

14 Reset Conditions RST/NMI configured in the reset mode All I/O pins are switched to input Watchdog timer powers up as active watchdog Other peripheral modules are disabled Status register (SR) is reset Program counter (PC) is loaded with (0FFFEh) Always refer to the user guide for information specific to your device Clock RISC CPU 16-bit JTAG/Debug FLASH... MAB 16 MDB 16 RAM ACLK SMCLK Digital Peripheral... Analog Peripheral

15 Interrupt Processing Item1 Item2 SP Prior to ISR Item1 Item2 PC SR SP ISR hardware - automatically PC pushed SR pushed Interrupt vector moved to PC GIE, CPUOFF, OSCOFF and SCG1 cleared IFG flag cleared on single source flags Item1 Item2 PC SR SP reti - automatically SR popped - original PC popped

16 Interrupt Vectors SOURCE FLAG INTERRUPT ADDRESS PRIORITY Power-up WDTIFG Reset 0FFFEh 15, highest ext. Reset Watchdog NMI NMIIFG (non)-maskable 0FFFCh 14 Osc. Fault Flash violation OFIFG ACCVIFG (non)-maskable (non)-maskable 0FFFAh 13 0FFF8h 12 Comparator_A CAIFG maskable 0FFF6h 11 Watchdog timer WDTIFG maskable 0FFF4h 10 Timer_A CCIFG0 maskable 0FFF2h 9 Timer_A CCIFGx maskable 0FFF0h 8 0FFEEh 7 0FFECh 6 SD16_A(f2013) SD16OVIFG, 0FFEAh 5 SD16IFG USI 0FFE8h 4 I/O Port P2 P2IFGx maskable 0FFE6h 3 I/O Port P1 P1IFGx maskable 0FFE4h 2 0FFE2h 1 0FFE0h 0, lowest Interrupt Vectors FLASH (x) 512B Segments (2) 128B Boot Loader RAM 16-bit Peripherals 8-bit Peripherals

17 Digital IO 2/16/

18 General Purpose Input/Output FG4618 has 10 ports with 8 pins each Each I/O individually configurable Independently configurable Port1 and Port 2 interrupts Simple software configuration P1DIR = BIT0; /* Set P1.0 as output */ P1DIR &= ~BIT1; /* Set P1.1 as input */ P1IES &= ~BIT1; /* Configure a port interrupt */ P1IE = BIT1; P1OUT = BIT0; /* Drive a HI on P1.0 */ bis.b #BIT0,&P1DIR; ;Set P1.0 as output bic.b #BIT1,&P1DIR; ;Set P1.1 as input bic.b #BIT1,&P1IES; ;Configure a port interrupt bis.b #BIT1,&P1IE; bis.b #BIT0,&P1OUT; ;Drive a HI on P1.0

19 Controlling GPIO Ports bis.b #010h,&P1DIR bis.b #010h,&P1SEL bis.b #001h,&P1DIR bis.b #001h,&P1OUT Input Register PxIN Output Register PxOUT Direction Register PxDIR Function Select PxSEL Interrupt Edge PxIES Interrupt Enable PxIE Interrupt Flags PxIFG P1 and P2 only

20 Port Registers Check the Datasheet for number of ports Typically only P1,P2 are interruptible Each interruptible port has a unique interrupt vector PxSEL is used to enable peripheral functionality PxREN is used to pull-up/pull-down based on PxOUT Unused pins can be configured as output, low (0).

21 Port Interrupts Interrupts can occur on: High to low edge Low to high edge Interrupt edge configured using PxIES register Changing the interrupt configuration causes PxIFG to be set On interrupt event; PxIFG must be cleared in software Port interrupt flags can also be polled by checking PxIFG

22 MSP430 Tool chain 2/16/

23 Getting Started with an MSP430 Editor Assembler and/or compiler Linker Stand-alone simulator Debugger, etc.,

24 USB-Based JTAG Interface, UIF Supports ALL MSP430 devices Supports 4-Wire and 2-Wire (Spy-Bi-Wire) JTAG Adjustable output voltage: V, 100mA JTAG fuse blow Fast operation

25 USB-Based ez430 JTAG Interface Simplified version of USB JTAG interface Supports MSP430F20xx devices only 2-Wire (Spy-Bi-Wire) JTAG support only Unrestricted programming and debugging capabilities Fixed output voltage of 3.6V Fast operation Small

26 USB-Based ez430-rf JTAG Interface Simplified version of USB JTAG interface Supports MSP430F22x4 and MSP430F20xx only 2-Wire (Spy-Bi-Wire) JTAG support only Unrestricted programming and debugging capabilities USB Integrated UART Back channel Fast operation Small

27 ez430-chronos: CC430 Dev Tool CC430-based wireless development tool in a watch 915/868/433 MHz versions available Custom LCD driven directly by CC430 Features: 3-axis accelerometer Altimeter Temperature sensor Buzzer USB RF access point Updated ez430 emulator for programming

28 LaunchPad Development Board Built-in emulation Cost = $4.30 Many Do It Yourself (DIY) projects online Check out the Wiki page Kit includes: LaunchPad Development board (MSP-EXP430G2) Mini USB cable 2x MSP430 flash devices 10-pin PCB Connectors (2 male & 2 female) 32kHz crystal Quick Start Guide Easy-to-use Affordable Scalable

29 GRACE Grace Graphical Code Engine Is: Generates MSP430 peripheral initialization code in CCSv4 Goal is for a new user to have running program within 15 minutes Heavy emphasis on ease of use Extend to cover all AEC devices Is not: Graphical application builder

30 CCE is now Code Composer Studio v4 Code Composer Studio v4: A single development platform for all TI processors CCE users will feel at home Enhancements since CCE: Speed Code size improvements Auto-updating License manager Support for all TI MCUs Only $495 for MCU Edition FREE 16KB-limited edition

31 IAR Kickstart IDE 16kB Compiler Assembler/Linker Editor Debugger

32 Third Party Development Resources Rowley CrossWorks Complete IDE solution High code density Simulator Windows, Linux, Mac MSPGCC Tool Chain Free Open Source GNU C Compiler, Assembler/ Linker, GDB Debugger Windows, Linux, Unix et Elprotronic MSP430, CC Chipcon, C2000 Programmers Fastest download speed Production programmers Amber Wireless Drop in wireless modules <1GHZ ez430-rf target boards CC430 Development boards RTOS Options µc/os-ii CMX-Tiny+ embos FreeRTOS IAR PowerPac QP Salvo TinyOS USB Stacks IAR HCC

33 Installing Code Composer Studio 33

34 CCS Install : Step 1/13 34

35 CCS Install : Step 2/13 35

36 CCS Install : Step 3/13 36

37 CCS Install : Step 4/13 37

38 CCS Install : Step 5/13 38

39 CCS Install : Step 6/13 39

40 CCS Install : Step 7/13 40

41 CCS Install : Step 8/13 41

42 CCS Install : Step 9/13 42

43 CCS Install : Step 10/13 43

44 CCS Install : Step 11/13 44

45 CCS Install : Step 12/13 45

46 CCS Install : Step 13/13 46

47 Lab 1: Building a CCS project for blinking a LED 47

48 In the lab we will use 48

49 Code Composer Studio v4 Code Composer Studio v4: A single development platform for all TI processors CCE users will feel at home Enhancements since CCE: Speed Code size improvements Auto-updating License manager Support for all TI MCUs FREE 16KB-limited edition go here! 49

50 MSP430FG461x/F20xx Experimenter s Board 7 Segment LCD EXP Board includes: MSP430FG4618/9 MSP430F2013 Interface to Chipcon radios Buzzer Microphone Bread-board area Serial connection interface Cap-touch pad Switches/ LEDs LED Switches

51 Open CCS Launch CCS v4 Core Edition Select a Workspace Browse to Desktop\MSP430Training\Labs Desktop\MSP430Training\Labs Exit from Welcome Screen when CCS opens 51

52 Create a CCS Project File > New > CCS Project Project Name: Flash_the_LED Project Type: MSP430 Additional Project Settings: <None> 52

53 Create a CCS Project (continued ) Device Variant: MSP430F4XXX, MSP430FG4618 Click Select the target device: MSP430FG

54 Add a File to the CCS Project Right click project and Add Files Navigate to Desktop\MSP430Training\Labs\Lab1 And select Flash_the_LED.c 54

55 Build & Debug a CCS Project Click the BUG to build the code & launch the debugger 55

56 CCS Window C/C++ Perspective Overview 1-click project Debug Independent Debug and C/C++ Project Perspectives Project View List of all Projects Project Outline Shortcut to project parts Console Build Information Code Window Real-time breakpoints, Syntax highlighting Problems View Information, Warnings, Errors 56

57 CCS Window Debug Perspective Overview 1-click project Debug Independent Debug and C/C++ Project Perspectives Target control Start Stop Halt Stepping Stack Trace Highly configurable window layout User preferences Plugin support Real-time, in-system MSP430 information Register access Flash, RAM, Info segment access Disassembly view Program Size Info Code Window Real-time breakpoints, Syntax highlighting 57

58 Is the LED blinking?

59 Lab 1 Check List Open, Use and Explore CCS Play with lab hardware MSP430EXPFG4618 Use the programmer MSP-FET430UIF Establish communication with the MSP430 device Blink an LED 15 mins

60 Lab2A: Using polled flags to determine an interrupt event 60

61 Lab2A Goals Create a new CCS project titled LAB2A (same as LAB1) Lab2A: Using polled flags to determine an interrupt event Use source code lab2_poll.c Configure switch S1 (P1.0) to accept an interrupt Poll P1IFG.0 to determine if a switch press has occurred Toggle LED4 (P5.1) on switch press Measure power when JP3 (near LED4) is open

62 Create a CCS Project File > New > CCS Project Project Name: LAB2A Project Type: MSP430 Additional Project Settings: <None> 62

63 Add a File to the CCS Project Right click project and Add Files Navigate to Desktop\MSP430Training\Labs\Lab2 And select lab2_poll.c 63

64 Complete the Source Code Setup P1.0 for an interrupt on a HI/LOW transition Test P1IFG.BIT0 flag for event Toggle P5.1 Source file : lab2_poll.c

65 Complete the Source Code Setup P1.0 for an interrupt on a HI/LOW transition Test P1IFG.BIT0 flag for event Toggle P5.1 Source file : lab2_poll_solution.c

66 Build & Debug a CCS Project Click the BUG to build the code & launch the debugger 66

67 Current measurement JP3 A LED ON(mA) LED OFF(mA) BATT JP ~0 Current consumed by device when polling A BATT

68 Wrap-Up 2/16/

69 Wrap-Up Discussed the digital IO Interrupt processing in MSP430 MSP430 tool chain Programming MSP430 using Code Composer Studio (CCS) 2/16/

70 References Train the Trainer, courseware prepared by Priya Thanigai, Ramakrishna Reddy K, Texas Instruments, February 2011 MSP430 Microcontroller Basics, John H.Davies, Newnes, 2010 MSP430 Teaching ROM, Pedro Dinis Gaspar, Antnio Esprito Santo, Bruno Ribeiro and Humberto Santos University of Beira Interior, Electromechanical Engineering Department, Portugal, 2009 The 8051 Microcontroller and Embedded Systems Using Assembly and C, Muhammad Ali Mazidi, Janice Gillispie Mazidi, Rolin D.McKinlay, Pearson 2/16/

71 2/16/

72 Program counter bit-0 is always tied to 0

73 Status register - does not have the Parity bit in MSP430

74 What happens upon a call instruction(1)

75 What happens upon a call instruction(2)

76 What happens upon a call instruction(3)

77 Types of non-volatile memory ROM EPROM OTP (One-Time Programmable) Flash NOR flash: slower to write but permits random access e.g., Most microcontrollers for fixed applications NAND flash: Used in bulk storage devices and can be accessed only serially in rows e.g., USB memory stick

78 Crystal accuracy and ppm Refer to the Faculty development document. Note : Apologies I do not recall the source of this