Institute for Applied Information Processing and Communications VLSI Group Professor Horst Cerjak, Martin Feldhofer KU01_assignment
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1 VLSI Design KU Sommersemester 2009 SHA-3 Hash Competition 1
2 Hash Functions are Work Horses in IT Security and Cryptography Web browser Trusted computing, everything is done with SHA-1 Public-key infrastructures E-government Operating system RNG Lotteries 2
3 Hash Functions are Fundamental Primitives Users Systems Protocols Primitives 3
4 Secure? What Properties? Collision resistance Preimage resistance Second preimage resistance 4
5 Collision resistance Preimage resistance Second preimage resistance Near-collision resistance Near-preimage resistance Partial-preimage resistance Pseudorandom generator Pseudorandom function Key derivation function Random oracle Secure? What Properties? 5
6 Popular Hash Functions and their Relatives 6
7 7
8 SHA-3 Contest Hash function contest organized by NIST (similar to AES) 51 candidates meet minimum submission requirements IAIK is co-author of Grøstl IAIK maintains the SHA-3 Zoo Further information 8
9 Assignment Please help us to evaluate the candidates hardware performance Target applications Embedded systems Wireless sensor nodes Battery powered devices Optimization goals Minimize chip area Minimize energy consumption Maximize bytes per clock cycle per gate equivalent 9
10 Goals SHA-3 hash function candidates Exploring Three different algorithms (only 256-bit variants, 128 bits security) Leave padding (is done externally) Estimating Cost of approaches A*t*P (area * clock cycles * power) Implementing Most promising algorithm Full functional standalone standardcell test chip Bus interface Data path Control logic Selected algorithm Hardware-oriented high-level model (Java, C++, C) Specification Optimization goal Circuit with best A*t*P Also of interest Low-power optimization Low-area optimization Economic impact Simple architecture Keep the things easy Useful IO interface IP module Amba APB? 10
11 Requirements Hardware architecture Optimization goal: area*throughput*power Cost estimation Target technology: Austriamicrosystems c35b µm CMOS For all three algorithms High-level model 1. True high-level model 2. Model reflecting proposed architecture Hardware implementation Synchronous design Synchronous clock Asynchronous power-on reset Synthesizable HDL Verilog or VHDL Simulation using TCL TCL scripts No HDL test benches Testdata files Test chip Standard-cell layout for c35b4 process Power simulation using Synopsys NanoSim Design document Introduction including motivation Short description of algorithms Hardware estimates Area, time, power consumption Hardware implementation General considerations Architecture and modules Hardware results Area, time, power consumption Picture of layout Comparison of estimates and results Conclusions Literature KU Journal IngenieurInnen-tagebuch 11
12 Schedule Wed March 4 th 2009 Wed April 1 st 2009 Wed April 29 th 2009 Fri June 12 th 2009 Assignment presentation Designflow presentation Intermediate presentation Submission Deadline (including colloquium) Deadlines Registration <= 6 th March 2009 (TUGonline + group via list) Intermediate <= 29 th April 2009 ( ) Final << 12 th June 2009 ( + Abgabegespräch ) 12
13 Deliverables Intermediate High-level model Model reflecting architecture (for algorithm with best estimate) Design document v1.0 Not more than 10 pages Introduction including motivation Short description of three algorithms Hardware estimates (for three algorithms) Area, time, power consumption Hardware implementation Proposed architecture (for algorithm with best estimate) Architectural options (speed vs. area vs. power) Literature Submission Mail to Subject [VLSI09_gg] 13
14 Deliverables Final Project files Cleaned and zipped project directory Design document v2.0 Fully blown design document (~ 15 pages) In addition to document v1.0: Hardware results (area, time (incl. critical path), power consumption 1. Synthesis results 2. Results from power simulation 3. Picture of layout with Pads (from Virtouso) Comparison of estimates and results Conclusions Submission Mail to Subject [VLSI09_gg] Propose a date for colloquium (Abgabespräch) 14
15 High-level model s 0,0 s 0,c 0,1 s 0,2 s 0,3 s 1,0 s 1,1 1,c s 1,2 s 1,3 MixColumn s' 0,0 s' s' 0,c 0,1 s' 0,2 s' 0,3 s' 1,0 s' 1,1 1,c s' 1,2 s' 1,3 void MixColumn(word8 a[4][4]) { word8 b[4][4]; int i, j; s 2,0 s 2,1 2,c s 3,0 s 3,1 3,c s 2,2 s 3,2 s 2,3 s 3,3 s' 2,0 s' 2,1 s' 2,2 s' 2,c 2,3 s' 3,0 s' s' 3,1 s' 3,2 s' 3,3 3,c } for(j = 0; j < 4; j++) for(i = 0; i < 4; i++) b[i][j] = mul(2,a[i][j]) ^ mul(3,a[(i + 1) % 4][j]) ^ a[(i + 2) % 4][j] ^ a[(i + 3) % 4][j]; for(i = 0; i < 4; i++) for(j = 0; j < 4; j++) a[i][j] = b[i][j]; 15
16 Example High-Level Model: Refined Model Elliptic- Curve Cryptography (Java) 16
17 Hardware Estimates Datapath will determine chip size Control usually < 15% Largest standard cells (here c35b4 process): Flip-flop (e.g µm) Full-adder (e.g µm) Multiplexer (e.g µm) Determine datapath size Estimated chip size = = (# flipflop *350 + # fulladder *275 + # mux *150 + etc.) + 20% overhead Estimated maximum clock frequency Depends on critical path Longest combinational path Sum of cell delays 17
18 Hardware Implementation Implementation of proposed architecture RTL description Using Verilog / VHDL Bit-accurate, cycle-accurate Verified by simulation Synthesis Place-and-Route Backend verification Layout Extraction Post-layout simulation Power simulation Logo Cadence High L Model HDL Model Synthesis Placement Routing 18
19 Layout Graz, SS
20 Groups and Accounts Groups Groups of 3 students Register on printed form Group members get listed On VLSI web including address Anyone without a group? Computer accounts 1 account per group Username vlsi09_07 for group 7 Password see list (please change) Without account Without regular backup (!) Computer rooms IAIK F1.01 Across Seminarraum Linux workstations Remote access Dual1.student.iaik.tugraz.at Dual7.student.iaik.tugraz.at Via SSH sopteron.student.iaik.tugraz.at FreeNX sopteron.student.iaik.tugraz.at File transfer thalys.student.iaik.tugraz.at 20
21 Contact Web VLSI Teaching /teaching/master_courses/vlsi_ design/practicals/ IAIK StudentNet Newsgroup lv.vlsi-design news://news.tugraz.at/ tu-graz.lv.vlsi-design Martin Feldhofer Tel IAIK, 1. Stock, Raum F2.18 Contact hours: always roughly 7:00 16:00 Just drop in! 21
22 Read literature What next? Run software implementations of algorithms High(est)-level model -Java/C++/C Make first estimates Play with IAIK designflow 22
23 Additional Links Austriamicrosystems, 0.35 µm CMOS Libraries (C35), [- > asic.austriamicrosystems.com] or StudentNet: [thalys.student.iaik.tugraz.at] Graz, SS
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