1-Operand instruction types 1 INC/ DEC/ NOT/NEG R/M. 2 PUSH/ POP R16/M16/SR/F 2 x ( ) = 74 opcodes 3 MUL/ IMUL/ DIV/ DIV R/M

Size: px

Start display at page:

Download "1-Operand instruction types 1 INC/ DEC/ NOT/NEG R/M. 2 PUSH/ POP R16/M16/SR/F 2 x ( ) = 74 opcodes 3 MUL/ IMUL/ DIV/ DIV R/M"

Sophia Edwards
6 years ago
Views:

2 Increment R16 1-Operand instruction types 1 INC/ DEC/ NOT/NEG R/M 4 x (16+48) = 256 opcodes 2 PUSH/ POP R16/M16/SR/F 2 x ( ) = 74 opcodes 3 MUL/ IMUL/ DIV/ DIV R/M 4 x (16+48) = 256 opcodes INC BX 8 opcodes Ex. 1 BX 1234H 1235H Ex. 2 BX FFFFH 0000H Increment R8 INC DH 8 opcodes Ex. 1 DH 12H 13H Ex. 2 DH FFH 00H Increment M8 INC byteptr [BX] 24 opcodes BX 2000H DS:2000H FFH 00H DS:2001H 12H 12H NOTE:- In this instruction there is a single operand, [BX]. It is not clear whether it is byte or word operand. Byteptr assembler directive announces to the assembler that it is a byte operation. Increment M16 INC wordptr [BX] 24 opcodes BX 2000H DS:2000H FFH 00H DS:2001H 12H 13H NOTE:- In this instruction there is a single operand, [BX]. It is not clear whether it is byte or word operand. wordptr assembler directive announces to the assembler that it is a word operation.

3 Decrement R16 DEC BX 8 opcodes Ex. 1 BX 1234H 1233H Ex. 2 BX 0000H FFFFH Decrement R8 DEC DH 8 opcodes Ex. 1 DH 12H 11H Ex. 2 DH 00H FFH Decrement M8 DEC byteptr [BX] 24 opcodes BX 2000H DS:2000H 00H FFH DS:2001H 12H 12H NOTE:-In this instruction there is a single operand, [BX]. It is not clear whether it is byte or word operand. Byteptr assembler directive announces to the assembler that it is a byte operation. Decrement M16 DEC wordptr [BX] 24 opcodes BX 2000H DS:2000H 00H FFH DS:2001H 12H 11H NOTE:- In this instruction there is a single operand, [BX]. It is not clear whether it is byte or word operand. wordptr assembler directive announces to the assembler that it is a word operation. Perform 1 s complement of R16 NOT BX 8 opcodes BX 1234H EDCBH NOT operation performs 1 s complement. Easy way: Subtract each hex digit from F Perform 1 s complement of R8 NOT DH 8 opcodes DH 12H EDH Perform 1 s complement of M8 NOT byteptr [BX] 24 opcodes BX 2000H DS:2000H 23H DCH DS:2001H 12H 12H

4 NOTE:- In this instruction there is a single operand, [BX]. It is not clear whether it is byte or word operand. Byteptr assembler directive announces to the assembler that it is a byte operation. Perform 1 s complement of M16 NOT wordptr [BX] 24 opcodes BX 2000H DS:2000H 34H CBH DS:2001H 12H EDH NOTE:- In this instruction there is a single operand, [BX]. It is not clear whether it is byte or word operand. wordptr assembler directive announces to the assembler that it is a word operation. Perform 2 s complement of R16 NEG BX 8 opcodes BX 1234H EDCCH NEG operation performs 2 s complement. Easy way: Subtract each hex digit from F and add 1 Perform 2 s complement of R8 NEG DH 8 opcodes DH 12H EEH Perform 2 s complement of M8 NEG byteptr [BX] 24 opcodes BX 2000H DS:2000H 23H DDH DS:2001H 12H 12H NOTE:- In this instruction there is a single operand, [BX]. It is not clear whether it is byte or word operand. Byteptr assembler directive announces to the assembler that it is a byte operation. Perform 2 s complement of M16 NEG wordptr [BX] 24 opcodes BX 2000H DS:2000H 34H CBH DS:2001H 12H EDH

5 NOTE:- In this instruction there is a single operand, [BX]. It is not clear whether it is byte or word operand. wordptr assembler directive announces to the assembler that it is a word operation. PUSH R16 Ex. PUSH CX CX 1234H SP 5678H 5676H Empty Empty SS: 5676H 1122H Full 1234H Full SS:5678H 3344H 3344H Suppose SP content is 5678H. It means locations 5678, 567A, 567C in stack segment are full. Locations 5676, 5674, are empty. Information pushed to location 5676 and SP value changes to 5676H. Push operation is always on 16 bit data. PUSH M16 Ex. PUSH [BX] BX 1234H SP 3366H 3364H DS:1234H 5678H Empty Empty SP: 5676H 1122H Full 5678H Full SP: 5678H 3344H 3344H PUSH SR Ex. PUSH CS CS 1234H SP 5678H 5676H Empty Empty SS: 5676H 1122H Full 1234H Full SS: 5678H 3344H 3344H PUSH Flags Ex. PUSHF Flags 1234H SP 5678H 5676H Empty Empty SS: 5676H 1122H Full 1234H Full SS: 5678H 3344H 3344H

6 POP R16 Ex. POP CX CX 1234H 1122H SP 5678H 567AH Empty Full SS: 5678H 1122H Empty 1122H SS: 567AH 3344H Full 3344H NOTE:- Suppose SP content is 5678H. It means locations 5678, 567A, 567C in stack segment are full. Locations 5676, 5674, are empty. Information poped from location 5678 and SP value changes to 567AH. Pop operation is always on 16 bit data. POP M16 Ex. POP [BX] BX 1234H SP 3366H 3368H DS:1234H 5678H 1122H Empty Full SS: 3366H 1122H Empty 1122H SS: 3368H 3344H Full 3344H POP SR Ex. POP CS CS 1234H 1122H SP 5678H 567AH Empty Full SS: 5678H 1122H Empty 1122H SS: 567AH 3344H Full 3344H POP Flags Ex. POPF Flags 1234H 1122H SP 5678H 567AH Empty Full SS: 5678H 1122H Empty 1122H SS: 567AH 3344H Full 3344H

7 Unsigned Multiply R8 with AL and store product in AX MUL CH CH FEH FEH AL 02H FCH 01FCH = 508 AH 34H 01H Unsigned Multiply R16 with AX and store product in DX AX MUL CX Signed Multiply R8 with AL and store product in AX CX 00FEH 00FEH AX 0002H 01FCH 01FCH = 508 DX 1234H 0000H IMUL CH FEH = -02 CH FEH AL 02H FCH FFFCH = -04 AH 34H FFH NOTE:- IMUL CH instruction multiplies AL and CH treating them as signed numbers. The 16-bit product is stored in AX. Unsigned Division of AX by R8 and store quotient in AL and remainder in AH DIV CH CH F0H AL 25H 01H Quotient AH 01H 35H Remainder NOTE:- DIV CH instruction divides AX by CH treating them as unsigned numbers. The 8-bit quotient is stored in AL and the 8-bit remainder stored in AH. Unsigned Division of DX AX by R16 and store quotient in AX and remainder in DX DIV CX CX 00F0H AX 0125H 0001H Quotient DX 0000H 0035H Remainder NOTE:- DIV CX instruction divides DX AX by CX treating them as unsigned numbers. The 16-bit quotient is stored in AX and the 16-bit remainder stored in DX.

8 Signed Division of AX by R8 and store quotient in AL and remainder in AH IDIV CH F0H = -10H CH F0H EE = -12H AL 25H EEH Quotient AH 01H 05H Remainder NOTE:-IDIV CH instruction divides AX by CH treating them as signed numbers. The 8- bit quotient is stored in AL and the 8-bit remainder stored in AH.

9 INTR INTA RST 5.5 RST 6.5 RST 7.5 TRAP SID SOD Interrupt Control Serial I/O 8-bit internal data bus Accumulator Temp. Reg. IR MUX W Z Flags B D C E ALU Instruction Decoder & m/c cycle encoding H L Stack Pointer Program Counter Inc/Dec Address Latch X 0 Timing and Control Address Buffer Data/adr Buffer X 1 CLK GEN Control Status DMA Reset Clk out RD WR ALE S 0 S 1 IO/M HOLD HLDA RESET OUT A15 A8 Address Bus AD0 AD7 Address/Data Bus READY RESET IN

10 8086 Instruction set Abbreviations used R8= AL/BL/CL/DL/ AH/BH/CH/DH R16=AX/BX/CX/DX/ SI/DI/BP/SP SR=CS/DS/ES/SS d16=16-bit data a8=8-bit I/O port address M8=contents of byte memory M16=contents of word memory R=R8/R16 AR=SI/DI/BX/BP d8=8-bit data M=M8/M16 Conventions used: MOV R M for MOV R, M and MOV M, R PUSH/POP R16 for PUSH R16 and POP R16 ROR R/M, 1/CL for ROR R,1 ROR M,1 ROR R,CL ROR M, CL 8086 Instruction set types Instructions are normally discussed under: Data Transfer instructions Ex. MOV BX, CX Arithmetic instructions Ex. ADD BX, CX Logical group of instructions Ex. AND BX, CX Stack group Ex. PUSH DX I/O group Ex. IN AL, 30H Branch group Ex. JNC LOCN String instructions Ex. MOVS Interrupt instructions Ex. INT 21H Data Transfer group, Arithmetic group, Logical group, Stack group, and I/O group of instructions explained first. They occupy several chapters in books.

11 Here, I explain them under: 2-operand instructions Ex. ADD BX, CX 1-operand instructions Ex. PUSH SI 0-operand instructions: Ex. DAA Branch group, String instructions, and Interrupt instructions are explained later. 2-Operand instructions 2-Operand instructions involving R and R/M MOV/XCHG ADD/ADC/SUB/SBB AND/OR/XOR/TEST/CMP R R/M Data transfer Arithmetic Logical 11 instructions x 2 10 = opcodes MOV instruction already discussed- see Instruction template In data transfer instructions flags are not affected. Exchange Instruction Before After XCHG DX, [BX] DX 1234H ABCDH BX 1000H DS:1000H ABCDH 1234H DS:1002H Add instruction Unlike in 8085, result of add/subtract can be in any register or memory location ADD [BX], DX DX 1234H BX 1000H In 3234H, 34H has DS:1000H 2000H 3234H three 1 s. So P flag =0 DS:1002H ADC DH,[SI] DH 30H 81H Add with Carry Carry flag 1 0 SI 2000H 81H DS:2000H 50H B(Two 1 s) DS:2001H 60H New flag values: Ac=0, S=1, Z=0, V=1, P=1

12 SUB DH, CL DH 30H 0BH Subtract (without borrow) CL 25H 0BH = B(Three 1 s) New flag values: Ac=1, S=0, Z=0, V=0, P=0, Cy=0 SBB DH, CL DH 20H FAH Subtract (with borrow) Cy flag 1 1 CL 25H FAH = (Six 1 s) 2 s complement of FAH= = +06 So, FAH = -06 New flag values: Ac=1, S=1, Z=0, V=0, P=1, Cy=1 Discussion about Overflow (V) flag V 23H (+ve) 43H (+ve) + 46H (+ve) + 54H (+ve) = 69H (+ve) = 97H (-ve) V= 0, Cy = 0 V = 1, Cy = 0 Correct answer Wrong answer Overflow used with signed numbers only Carry flag used with unsigned numbers only 83H (-ve) F2H (-ve) + 94H (-ve) + F3H (-ve) = 17H (+ve) = E5H (-ve) V= 1, Cy = 1 V = 0, Cy = 1 Wrong answer Correct answer 94H (-ve) F6H (-ve) - 83H (-ve) - 43H (+ve) = 11H (+ve) = B3H (-ve) V= 0, Cy = 0 V = 0, Cy = 0 Correct answer Correct answer

13 AND instruction 94H (-ve) 66H (+ve) - 23H (+ve) - 83H (-ve) = 71H (+ve) = E3H (-ve) V= 1, Cy = 0 V = 1, Cy = 1 Wrong answer Wrong answer AND BH, CL BH 56H 06H Subtract (with borrow) AND 1 1 0FH= B CL 0FH 06H= B Use: Selectively reset to 0 some bits of the destination Bits that are ANDed with 0 s are reset to 0 Bits that are ANDed with 1 s are not changed OR instruction OR BH, CL BH 56H 5FH 56H= B OR 0FH= B CL 0FH 5FH= B Use: Selectively set to 1 some bits of the destination Bits that are ORed with 1 s are set to 1 Bits that are ORed with 0 s are not changed Ex-OR instruction XOR BH, CL BH 56H 59H 56H= B XOR 0FH= B CL 0FH 59H= B Use: Selectively complement some bits of the destination. Bits that are XORed with 1 s are complemented Bits that are XORed with 0 s are not changed TEST instruction TEST BH, CL BH 56H 56H 56H= B AND 0FH= B CL 0FH 0FH 06H= B Only flages are affected Temp 45H 06H

14 TEST basically performs AND operation. Result of AND is not stored in destination. It is stored in Temp register. Temp is not accessible to programmer. There is no instruction like MOV Temp, 67H Compare Instruction CMP BH, CL 56H= B 0FH= B CL 0FH BH 56H 56H Only flags are affected Temp 45H 47H CMP basically performs Subtract operation. Result of CMP is not stored in destination. It is stored in Temp register. Temp is not accessible to programmer. 2-Operand Instructions involving immediate data MOV ADD/ADC/SUB/SBB AND/OR/XOR/TEST/CMP 8 byte registers + 8 word registers+ 24 byte memory + 24 word memory = 64 opcodes 10 instructions x 64 = 640 opcodes R/M, d8/d16 Move Immediate data to a Register/ Memory location Before After MOV DX, ABCDH DX 1234H ABCDH Before After MOV BH, 12H BH 56H 12H Add Immediate data to a Register/ Memory location Before ADD [BX], 12H BX 1000H After DS:1000H 20H 32H DS:1001H

15 Before ADD [BX], 1234H BX 1000H After DS:1000H 2000H 3234H DS:1002H Add with Carry Immediate data to a Register/ Memory location ADC DH, 32H DH 30H 63H Add with Carry Carry flag H= It has four 1 s New flag values: Ac=0, S=0, Z=0, V=0, P=1 Subtract Immediate data from a Register/ Memory location SUB DH, 40H DH 30H F0H Subtract (without borrow) F0H= B(Four 1 s) New flag values: Ac=0, S=1, Z=0, V=0, P=1, Cy=1 Subtract with borrow Immediate data from a Register/ Memory location SBB DH, 25H DH 20H 06H Subtract (with borrow) Cy flag H= B(Two 1 s) New flag values: Ac=1, S=0, Z=0, V=0, P=1, Cy=1 AND Immediate data with a Register/ Memory location AND BH, 0FH BH 56H 06H 56H = B AND 0FH = B Cy flag H = B(Two 1 s) Use: Selectively reset to 0 some bits of the destination Bits that are ANDed with 0 s are reset to 0 Bits that are ANDed with 1 s are not changed

16 Introduction to Microprocessor Notes ebook Publisher : VTU elearning Author : Type the URL : Get this ebook

Arithmetic Instructions

Segment 3C Arithmetic Instructions This topic covers the following instructions: Addition (ADD, INC, ADC) Subtraction (SUB, DEC, SBB,CMP) Multiplication (MUL, IMUL) Division (DIV, IDIV) BCD Arithmetic