Transparent-Test Methodologies for Random Access Memories Without/With ECC

Transcription

1 1888 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 10, OCTOBER 2007 [5] A. Osman, M. Osman, N. Dogan, and M. Imam, An extended tanh law MOSFET model for high temperature circuit simulation, J. Solid-State Circuits, vol. 30, no. 2, pp , Feb [6] J. Daga, E. Ottaviano, and D. Auvergne, Temperature effect on delay for low voltage applications, in Proc. DATE, 1998, pp [7] A. Shousha and M. Aboulwafa, A generalized tanh law MOSFET model and its applications to CMOS inverters, J. Solid-State Circuits, vol. 28, no. 2, pp , Feb [8] T. Sakurai and A. Newton, Alpha-power law MOSFET model and its application to CMOS inverter delay and other formulas, J. Solid-State Circuits, vol. 25, no. 2, pp , Apr [9] Y. Taur and T. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, [10] T. Chan, W. Lee, and H. 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Nassif, Full chip leakage estimation considering power supply and temperature variations, in Proc. ISLPED, 2003, pp [23] J. Abraham, Integrating complex I/O in an SOC, Chip Design Mag., Transparent-Test Methodologies for Random Access Memories Without/With ECC Jin-Fu Li Abstract This paper presents a systematic procedure for transforming a bit-oriented March test into a transparent word-oriented March test. The test-time complexity of the transparent word-oriented March tests converted by the proposed method is only (P + 5 log 2 B +2)N for an N B-bit Random Access Memory, and the test-time complexity of the corresponding signature-prediction test is QN. Here, P and Q denote the number of total Read/Write and Read test operations of the original bit-oriented March test. A transparent-test methodology for memories with error-correction code (ECC) is also proposed. This methodology can test and locate faulty cells, and no signature prediction is needed. The test-time complexity of the proposed transparent-test methodology for memories with ECC is only (P + 5 log 2 B +2)N. Index Terms Error-correction code (ECC), March test, random-access memory (RAM), reliability, soft errors, transparent test. I. INTRODUCTION In a complex system-on-a-chip (SOC) design, memory cores usually represent a significant portion of the chip area. It is also the densest part of the chip. Memory-core reliability, thus, can greatly affect SOC reliability. Error-correction code (ECC) is one of the widely used methods for enhancing memory reliability. Periodic transparent testing is also an important method for enhancing memory reliability. It also can enhance the function of ECCs. For example, ECC has two weaknesses fault-accumulation effect and in-ability to detect functional faults. Integrating transparent testing with ECCs can solve the mentioned weaknesses associated with ECC. Concept of transparent testing, which leaves the original contents of the circuit under test unchanged after the testing is completed if no faults are present. One major advantage of transparent testing is that it can ensure the reliability of stored data throughout its lifetime. Many transparent-test schemes have been reported in [1] [13]. In the study in [1] and [2], a systematic approach for transforming a March test into a transparent March test was presented. The transformation rules consist of two phases generation of a transparent March test and generation of a signature-prediction test. In the study in [3], a transparent-test methodology was presented. The test methodology covers a class of faults, including both pattern sensitive and dynamic faults. It can also be extended for cache and dual-port random access memories (RAMs). In the study in [4] [7], the method from [1] is applied to detect pattern-sensitive faults and single V-coupling faults (CFs). Later, a symmetric transparent-test methodology was proposed in the study in [8]. Due to the symmetric characteristics, the final signature of the signature analyzer will be zero if no faults exist in the memory under test, such that, the signature-prediction test is not needed. Automatic generation of symmetric transparent March tests was also proposed in the study in [13]. Some short transparent tests /$ IEEE Manuscript received August 31, 2006; revised December 3, This work was supported in part by the National Science Council, Taiwan, R.O.C., under Contract NSC E and in part by MOEA, Taiwan, R.O.C., under Contract 96-EC-17-A-01-S This paper was recommended by Associate Editor K. Chakrabarty. The author is with the Department of Electrical Engineering, National Central University, Jhongli 320, Taiwan, R.O.C. Digital Object Identifier /TCAD

2 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 10, OCTOBER for bit-oriented RAMs were reported in the study in [9]. A simulation package was also developed for the test algorithms generation and simulation. In [10], a parallel transparent-test scheme was presented. Two transparent-test schemes without the aliasing problem were reported in the study in [11] and [12]. In [11], a transparent-test approach using the dynamic power-supply current (DPSC) was presented. Instead of generating a signature, DPSC transparent testing uses a current sensor to detect the RAM faults. A transparent online memory test (TOMT), which was reported in the study in [12], was developed for online testing of word-oriented memories with parity or Hamming protection. TOMT introduces the concept of concurrent error detection and correction to eliminate the requirement of signature generation and to avoid the interference of normal system operation. So far, however, all the transparent tests for word-oriented memories are not time-efficient. For example, the transparent-test scheme, which was reported in the study in [1] and [2], performs bit-oriented operations on all the bits of each word. Another example: TOMT also executes bitwise manipulations in wordoriented memory testing. Therefore, short transparent tests for wordoriented memories need to be developed. Moreover, shorter testing times can reduce the probability of interference of normal system operations, since transparent tests are typically executed while systems are idle. This paper presents two transparent-test schemes for RAMs without/with ECC. The proposed method transforms a bit-oriented March into a word-oriented March including two separated March tests, one is for interword CFs and the other is for intraword CFs. Then, only the March for intraword CFs needs various data backgrounds. This can reduce the test-time complexity. Compared with existing approaches, both transparent-test schemes are very time-efficient. II. PROPOSED TRANSPARENT-TEST METHODOLOGY FOR RAM WITHOUT ECC A. Transparent March Tests The notation used in an algorithm is first described. D denotes the initial content of a cell or a word for bit-oriented or word-oriented memories, respectively; D a is the data D a, where denotes a bitwise XOR operation, where D and a have the same data width; ( ) represents the ascending (descending) address sequence; and denotes either an ascending or descending address sequence. In addition, wx denotes a write-x operation on an addressed memory cell or word, while rx denotes a read operation on an addressed memory cell or word; and X is the expected data. In a nontransparent March test, X is used to describe specific data for a Write operation. In a transparent March test, X is replaced with D a, representing the data of the Write/Read test operations. Algorithm 1 (TWM_TA) describes the proposed transparent wordoriented March transformation procedure. For a given bit-oriented March test (March), TWM_TA first replaces w0 or w1 of the original March test with w0 or w1, where0 and 1 denote the all-0 and all-1 data backgrounds (also called solid data backgrounds). In addition, r0 or r1 of the original March test is replaced with r0 or r1, respectively. A new March test with solid data backgrounds is obtained, which is called SBMarch. Subsequently, TWM_TA transforms the SBMarch into a transparent SBMarch (TSMarch). The TWM_TA first removes the initialization March element if it is useless for fault activation. Then, a Read operation is added at the beginning of the March element in which the first operation is Write 1. In addition, r0 and r1 are replaced with rd a0 and rdā0,wherea 0 denotes an all-0 data background. Similarly, w0 and w1 are replaced with wd a0 and wdā0. Thus, we can obtain the transparent SBMarch TSMarch. Algorithm 1TWM_TA Require: March a given bit-oriented March test SBMarch: March with solid data backgrounds (all-0 or all-1) TSMarch: the corresponding transparent test of SBMarch ATMarch: added transparent March test TWMarch: transparent word-oriented March test if March = { } then Abort while March { } do for all Test Operations of March do Replace w0 or w1 with w0 or w1, respectively Replace r0 or r1 with r0 or r1, respectively SBMarch is obtained for all Test Operations of SBMarch do Remove the initialization March element if it is useless for fault activation Add a Read operation at the beginning of the March element in which the first test operation is a Write one Replace all r0 or r1 operations with rd a0 or rdā0, respectively Replace all w0 or w1 operations with wd a0 or wdā0, respectively TSMarch is obtained if The last Write operation of the TSMarch is wdā0 then ATMarch = { (rdā0,to 1,TO 2,...,TO log2 B, wdā0 )}, where TO i =(wdāi,wd ai,rd ai,wdāi,rdāi ). else ATMarch = { (rd a0,to 1,TO 2,...,TO log2 B, wd a0 )}, where TO i =(wd ai,wdāi,rdāi,wd ai,rd ai ). Return TWMarch = {TSMarch; ATMarch} Since the Write operations of the TSMarch only write the original data or the inverted original data into the RAM, most of intraword CFs cannot be activated. To cover intraword CFs, different data backgrounds should be applied in addition to the solid data backgrounds. Therefore, an additional transparent March is added after the TSMarch. If the data for the last Write operation of the TSMarch are equal to the inverse of the initial data, i.e., the last Write operation is wdā0, then add an additional transparent test ATMarch = { (rdā0,to 1,TO 2,...,TO log2 B, wdā0 )}, where TO i = (wdāi,wd ai,rd ai,wdāi,rdāi ). On the contrary, if the expected data for the last Write operation is equal to the initial data, i.e., the last Write operation is wd a0, then add an additional transparent test ATMarch = { (rd a0,to 1,TO 2,...,TO log2 B,wD a0 )}, where TO i =(wd ai,wdāi,rdāi,wd ai,rd ai ). For a memory with B-bit words, a i is a B-bit binary data that can be expressed as a i = B 1 x j=0 j2 j for i =1, 2,..., log 2 B. In the previous expression, if the value j/2 i 1 is even, then the value x j is one, otherwise, it is zero. For example, if a memory with 8-b words is tested, then three data patterns are needed for the ATMarch, i.e., i = {1, 2, 3}. Assume that the content of the memory under test is the same as the initial content while the TSMarch is completed. According to the description above, the ATMarch with a 1, a 2,anda 3 must be executed, and a 1 = { } since j/2 0 = {7, 6, 5, 4, 3, 2, 1, 0}; a 2 = { } since j/2 1 = {3, 3, 2, 2, 1, 1, 0, 0}; and a 3 = { } since j/2 2 = {1, 1, 1, 1, 0, 0, 0, 0}. Thus, ATMarch = { (rd a0,wd a1,wdā1,rdā1,wd a1,rd a1,wd a2,wdā2,rdā2, wd a2,rd a2,wd a3,wdā3,rdā3,wd a3,rd a3,wd a0 )}. Assume that a memory with one 8-b word is tested, and the content of the word is D = {d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 }, while the TSMarch is completed, where d i denotes arbitrary data. Table I shows the fault-free status

3 1890 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 10, OCTOBER 2007 TABLE I FAULT-FREE STATUS OF AN 8-b WORD WHEN ATMARCH IS EXECUTED Fig. 1. Example of response-evaluation hardware for the ATMarch. of the word corresponding to each test operation while ATMarch is executed. Finally, the converted transparent word-oriented March (TWMarch) can be obtained by concatenating TSMarch with ATMarch. An example is given to explain the proposed transparent March test scheme further. Consider a bit-oriented March U [14]: { (w0); (r0, w1, r1, w0); (r0, w1); (r1, w0, r0, w1); (r1, w0)}. The March U is first transformed into a test with solid backgrounds, called SBMarch U. Then, SBMarch U is { (w0); (r0, w1, r1, w0); (r0, w1); (r1,w0,r0,w1); (r1, w0)}. Assume that a memory with 8-b words is tested. According to the transformation rules described in Algorithm 1, TSMarch U will be { (rd a0,wdā0,rdā0,wd a0 ); (rd a0,wdā0 ); (rdā0,wd a0, rd a0,wdā0 ); (rdā0,wd a0 )}, where a 0 = { }. After TSMarch is executed, the content of each word is equal to the original content of the word. Therefore, the added ATMarch is { (rd a0,wd a1,wdā1,rdā1,wd a1,rd a1,wd a2,wdā2,rdā2, wd a2,rd a2,wd a3,wdā3,rdā3,wd a3,rd a3,wd a0 )}, where a 1 = { }, a 2 = { }, anda 3 = { }. The test-time complexity of the transformed transparent word-oriented March U is 29N for testing a memory with 8-b words. B. Signature Prediction and Response Evaluation When a transparent test is used to test a RAM, the golden signature is obtained by only executing the Read operations of the transparent test. This read result is regarded as a reference result. These Read test operations are called a signature-prediction test. Once the transparent test is completed, the read result is compared with the reference result to determine whether the memory under test is fault-free. Consider a transparent word-oriented March test converted by Algorithm 1. The converted transparent test consists of TSMarch and ATMarch. The TSMarch can detect interword CFs covered by the original bit-oriented March test. To cover all the intraword CFs, including undetected faults, the ATMarch is used. Since the ATMarch is responsible for covering intraword CFs, an intraword CF in a word can be activated and detected by the Read/Write operations in ATMarch while ATMarch addresses the word. In comparison with the detection of interword CFs, an interword CF is activated and detected at different words or by different March elements. As Algorithm 1 depicts, the first Read operation of ATMarch reads the original data of the memory. Therefore, the Read data of the subsequent Read operations can be evaluated by comparing it with the Read data of the first Read operation. Therefore, ATMarch does not need a prediction test. In summary, only TSMarch needs a signature-prediction test. The signature-prediction test can be obtained by removing the Write operations of TSMarch. The response checking of ATMarch is accomplished by considering the read data of the first Read operation as Fig. 2. Conceptual diagram of the proposed transparent-test methodology for a memory with ECC. golden data. Then, the read data of the subsequent Read operations are compared with that golden data. Since the Read operations within a March element are completed in each addressed word, the read data of the first Read can be stored in a register temporarily and then compared with the data of the subsequent Read operations. An example is illustrated to further explain the response-checking scheme. Consider the transparent March U illustrated in the last paragraph of Section II-A. The signature-prediction algorithm is obtained by removing the Write operations of TSMarch U, and it is as follows: { (rd a0,rdā0 ); (rd a0 ); (rdā0,rd a0 ); (rdā0 )}, where a 0 = { }. Subsequently, the response checking for the ATMarch is described. The first Read operation rd a0 reads the data D a0, and the data are stored in a register. While the second Read operation rdā1 performs a Read operation and the Read data Dā1 are compared with D a0 ā 1,whereā 1 determines which bits of the register output should be inverted. In a similar way, the Read data of the subsequent Read operations are compared with D a0 a i (or ā i ). Fig. 1 depicts an example of response-evaluation hardware for the ATMarch. For more details, if the fourth Read operation (rdā2 ) is performed, the Read data are compared with D a0 ā 2. Assuming that the original data of a word are (d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ) before the ATMarch is performed. The data read by the first Read operation are D a0 =(d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ), and it is stored in the Register as shown in Fig. 1. Then, the data read by the rdā2 operation is compared with D a0 ā 2 =(d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ) ( ) = ( d 7 d6 d 5 d 4 d3 d2 d 1 d 0 )=Dā2. Since the ATMarch does not need the signature-prediction algorithm, the required time for the signature prediction of the proposed transparent-test methodology can drastically be reduced. Again, consider the converted transparent March U. As described above, only four March elements with six Read test operations are needed for the signature prediction. Thus, the test-time complexity is 6N for an N B-bit RAM. Compared with the transparent-test scheme reported in the study in [2], the test-time complexity for the signature prediction of the transparent March U is 6N (log 2 B +1).

4 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 10, OCTOBER Fig. 3. (a) Initial content of a 3 4-b RAM. (b) Content of the RAM while the second bit of W 0 has a stuck-at-zero fault. (c) Content of the RAM while transparent test is completed. III. PROPOSED TRANSPARENT-TEST METHODOLOGY FOR RAM WITH ECC Adding ECCs in each word of a RAM is one widely used approach to prevent these soft errors. Unfortunately, the ECC approach has two major weaknesses [12]. First, the effect of latent bit-error accumulation may occur at rarely accessed words. Second, the ECC cannot detect functional faults. Subsequently, we explain why ECC approaches have these two weaknesses in more detail. First, the ECC protects only these words within the memory that are accessed regularly. The rarely accessed words remain practically unprotected due to the accumulation of latent bit errors. Once the number of accumulated error bits in a word is greater than the protection capability of the applied ECC, the system operation will be affected while it reads the word. For example, ECCs with the capability of double-bit and singlebit error corrections are adopted. Then, the applied ECC will fail if a word has two accumulated errors. Second, the ECC only accounts for the integrity of stored data, but it cannot check memory functionality. To check if a memory has functional faults, a test must alter the content of the memory to activate and detect a latent fault. On the other hand, if only error-detecting codes are used for the memories, errordetection latency, which is defined as the time between the occurrence of an error and its detection, becomes yet another issue [15]. Error detection of a word is only possible while the word is read. For highreliability applications, such as in telecommunication switching, it is not acceptable to detect erroneous data at that very moment while the data are explicitly needed [16]. Errors should be detected as early as possible so that data can be recovered before being requested by the system. Therefore, we see that if periodic transparent testing can be integrated with the ECC, all the memory words can regularly be accessed and tested. Therefore, the effects of fault accumulation and error-detection latency can be minimized. Subsequently, the proposed transparent-test methodology for the memory with ECC is introduced. For brevity, we assume that the ECC is fault-free for the proposed transparent-test scheme. However, the transparent-test scheme can also work even when the ECC is faulty, if a specific approach is used to design the ECC, e.g., the approach reported in the study in [17]. Transformation rules for converting a given bit-oriented March test into a transparent word-oriented March test for the memory with ECC are the same as Algorithm 1. However, the proposed transparent-test methodology for the memory with ECC checks test responses using ECC results while a Read is executed. Thus, the signature-prediction phase is not needed. Detail of the Read/Write test operations of the converted transparent March tests for the memory with ECC are described as follows. Read Read the data D at data output (DO); check if Code_Gen(D) =C. Write Write the data ˆD a i. Here, Code_Gen(D) and C represent the ECC generated by the code-generation circuit with read data D and the stored ECC of D, respectively. In addition, ˆD denotes the corrected data on the output of the correction circuit. Fig. 2 depicts the concept of the proposed transparent-test methodology for a RAM with ECC. In the transparent-test mode (i.e., Test =1), the input of the code-generation circuit obtains the data D from DO. That is, while the transparent built-in self-test (BIST) executes a Read operation on a word, the ECC of the read data D is generated by the code-generation circuit. Then, the generated ECC is compared with the original ECC (C) of the word. If the comparison results in a mismatch, a fault is detected. Otherwise, no fault is detected. While the transparent BIST executes a Write operation, the written data are generated by performing the bitwise exclusive-or operation on the data from the output of the correction circuit, i.e., ˆD, and the corresponding data background a i determines those bits of the ˆD that are inverted. Therefore, even when the last Read operation detects a fault in the addressed word, the subsequent Write operation is able to write the corrected data into the addressed word. This can really achieve the goal of restoring the original content of the memory under test. Please note: it is valid only if the number of faulty bits of a word is less than the error-correction capability of the applied ECC. However, the data of the Write operation of the transparent test for the memory without ECC are obtained on the bitwise exclusive-or operation on the data of the previous Read operation and the data background a i. Thus, the transparent test for the memory without ECC successively inverts and reinverts the contents of the memory under test. This cannot restore the original content of the memory under test if the memory has suffered hard faults or soft faults during the testing process. An example is illustrated to explain the proposed transparent-test methodology for the memory with ECC in more detail. Consider a 3 4-b memory with Hamming ECC. The original content of the memory is shown in Fig. 3(a). In addition, assume that the MATS+ { (w0); (r0,w1); (r1,w0)} [18] test algorithm is used to test the memory. The Hamming code (h 2 h 1 h 0 ) of each word is achieved by h 2 = d 0 + d 1 + d 3, h 1 = d 1 + d 2 + d 3 and h 0 = d 0 + d 1 + d 2, where + is modulo-2 addition [19]. For simplicity, only the TSMarch of MATS+ is used for explanation. According to Algorithm 1, the bit-oriented MATS+ can be transformed into a transparent word-oriented March test TSMarch = { (rd a0,wdā0 ); (rdā0,wd a0 )}, wherea 0 = (0000). Let the second bit (d 1 ) of the first word (W 0 ) have a stuckat-zero fault. The Read operation of the first March element reads the content of the memory. Then, the Write operation of that same March element writes the complement of the read data into the memory under test. Therefore, the content of the memory under test is as shown in Fig. 3(b), while the first March element is completed. Subsequently, the Read operation of the second March element reads the data from W 2 to W 0. While W 0 is read, the Code_Gen(0010) = (111) and the Hamming ECC of W 0 is 100 (i.e., C =100). Since Code_Gen(D) C, the transparent BIST detects a fault in W 0. Then, the successive Write operation writes the data of the complement of corrected data (0110) into W 0. The final contents of the memory are now the same as its initial contents, as shown in Fig. 3(c). However, if the transparent test for the memory without ECC is used to test the memory, the content of the first word will be (1101) since the data of the last Write operation on W 0 is the complement of (0010). Note that the

5 1892 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 10, OCTOBER 2007 prerequisite that enables the capability of restoring the original content is that the number of faulty bits in a word may not exceed the correction capability of the applied ECC. Since the transparent-test method is to be used throughout the lifetime of a memory device, the number of faulty bits in a word usually is small. Therefore, the proposed transparent-test methodology for the memory with ECC is practical. Another feature of the proposed transparent-test methodology is the ability to detect fault location. Once a faulty word is detected, the location of the faulty bit can be determined from the result of Code_Gen(D) C [19]. Again, the fault-location capability is related to the applied ECC. The widely used Hamming code is used to show this. Assume that a 4-b word with data (d 3 d 2 d 1 d 0 ). If a faulty bit exists in the word, the faulty data bit is expressed as d i. The response checking is done by Code_Gen(D) C. Let the first bit of the word be the faulty bit, then the Code_Gen(D) for the word can be expressed as h 2 = d 0 + d 1 + d 3, h 1 = d 1 + d 2 + d 3,andh 0 = d 0 + d 1 + d 2. Therefore, the comparison result U = Code_Gen(D) C can be expressed as follows: u 2 = h 2 + h 2 =(d 0 + d 1 + d 3 )+(d 0 + d 1 + d 3 )=1 u 1 = h 1 + h 1 =(d 1 + d 2 + d 3 )+(d 1 + d 2 + d 3 )=0 u 0 = h 0 + h 0 =(d 0 + d 1 + d 2 )+(d 0 + d 1 + d 2 )=1. Thus, the comparison result U =(u 2 u 1 u 0 ) = (101) indicates that the first bit is faulty. In a similar manner, we can show that if the second, third, or the fourth bit is the faulty bit, the comparison result U is (111), (011), and (110), respectively. IV. ANALYSIS AND COMPARISON A. Time-ComplexityAnalysis and Comparison Consider an N B-bit memory and a bit-oriented March test with P Read/Write operations in which there are Q Read operations. Without loss of generality, we assume that the bit-oriented March does not have an initialization Write operation; the first operation in each March element is Read; and the last Write operation can restore the original content. In addition, we assume that B is power of two. As Algorithm 1 shows, the test-time complexity of the transformed transparent wordoriented March test (TCM) with respect to the bit-oriented March test can be calculated as follows: TCM =(P +5log 2 B +2)N.ThePN is for the TSMarch and (5 log 2 B +2)N is for the ATMarch. Since the signature prediction only is needed for the TSMarch, the test-time complexity of the corresponding signature-prediction test (TCP) for TSMarch is as follows: TCP = QN. Different transparent-test schemes have been reported [2], [4], [6], [8], [12], [20]. In [4], the proposed approach is for the testing of pattern-sensitive faults. In [6], the proposed approach is for the testing of single V-CFs and it adopts the transformation rules reported in the study in [2]. In [8], a symmetric transparent-test method is reported. However, only bit-oriented symmetric transparent March tests are discussed. In [20], an online and offline BIST architecture and selfadjusting signature-analysis scheme are reported. No transparent-test algorithms are presented. Thus, we compare the test-time complexity of the proposed transparent March tests with those transparent March tests reported in the study in [2] and [12], since the two works reported transformation rules and proposed transparent-test algorithms. These two works also discuss word-oriented transparent tests. The transparent-test scheme reported in the study in [2] transforms the bit-oriented March tests into transparent word-oriented March tests that execute the transformation in each bit of a word. Therefore, the TCM and TCP of the transparent word-oriented March test converted with the scheme reported in the study in [2] can be calculated as TABLE II COMPARISON OF DIFFERENT TRANSPARENT-TEST SCHEMES TCM = P (log 2 B +1)N and TCP = Q(log 2 B +1)N. TheTCM of the TOMT reported in the study in [12] is (4 + 8B)N. The TOMT is a transparent-test integrating ECC, so it does not need the signature-prediction test, i.e., TCP =0. The proposed transparent March test methodology for the memory with ECC does not also need the signature-prediction phase. Therefore, the test-time complexity of the proposed transparent March tests for the memory with ECC is (P +5log 2 B +2)N. Table II summarizes the comparison of TCM and TCP for each of the four transparent-test schemes discussed above. Here, TT without and TT with denote the proposed transparenttest methods for the memory without ECC and with ECC, respectively. Scheme 1 and TT without are used for memory without ECC. As shown in Table II, the total test-time complexity of Scheme 1 and TT without is (P + Q)log 2 BN +(P + Q)N and (P + Q)N + (5 log 2 B +2)N, respectively. Therefore, if (P + Q)log 2 BN (5 log 2 B +2)N, the test-time complexity of Scheme 1 is greater than TT without. This is true for most used March tests. In addition, the TT without has less test-time complexity compared with Scheme 2 [12] for most cases. For example, if March C is transformed into a transparent word-oriented March C for testing an N 32-b memory, then the test-time complexity (TCP + TCM) of Scheme 1 [2], Scheme 2 [12], TT without,andtt with is 84N, 260N, 41N,and36N, respectively. That is, the test-time complexity of TT without (TT with ) is only about 48.9% (42.9%) or 15.8% (13.8%) of that test-time complexity compared with the transparent word-oriented test converted by Scheme 1 or Scheme 2, respectively. Less testing time for transparent-test schemes is one important feature of this method, since the transparent test is done during system s idle time. If the testing time is greater than the idle time, the test process is interrupted or disturbed. Investigating the proposed transparent-test schemes further, they have another advantage in that the converted, transparent tests can be divided into separated portions, i.e., TSMarch and ATMarch as depicted in Algorithm 1. Thus, TSMarch and ATMarch can be used to test the memory in two different idle time slots. This further minimizes the probability of an interruption. The test length of TSMarch approaches that of the corresponding bit-oriented March test. In addition, the signatureprediction test is only needed for TSMarch. This reduces the time of signature prediction. Signature prediction is not needed for ATMarch, so the test length of ATMarch is (5 log 2 B +2)N. B. Comparison of Different Transparent-Test Schemes Previous works [2], [8], [12], [20] are compared with the proposed test methodologies. Table III summarizes the comparison results, where FL, FM, and SP represent fault location, fault masking, and signature prediction, respectively. As Table III shows, Scheme 2, Scheme 3, and TT with all are targeted for use with the memory with ECC. Scheme 3, in particular, is designed for DRAMs, since it hides the transparent testing in these memory-types refresh cycles. Scheme 2 and TT with can locate faulty cells while they detect a fault. Note that the proposed TT without has also partial fault-location capability, since the data of the first Read operation in ATMarch is compared with the data of the subsequent Read operations immediately while a word is accessed. Therefore, if the March element of ATMarch detects a fault, the position(s) of the faulty cell(s) can

6 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 10, OCTOBER TABLE III COMPARISON OF DIFFERENT TRANSPARENT-TEST SCHEMES be known from the comparison results (i.e., results of bitwise XOR operation on the read results). Only Scheme 2 and TT with do not have the problem of aliasing, since the other schemes use a signature analyzer to evaluate the test responses. Signature-prediction tests are needed for Scheme 1 and TT without.thett without only needs the signature-prediction test for the TSMarch. According to the discussions above, we see that the proposed transparent-test schemes TT without and TT with have the following features: low testing time, high fault-location capability, and low-cost signature-prediction test. But the proposed transparent test TT with has one limitation the fault-detecting capability is related to the correction capability of the applied ECC. The proposed TT with is still practical for conducting transparent testing. Since the transparent test is used for periodic testing of memory during its lifetime, the probability of that the number of faulty bits in a word larger than that of the error-correction capability of the applied ECC is low. V. C ONCLUSION Transparent testing is one efficient approach for enhancing the reliability of memory throughout the device lifetime. This paper has presented two transparent-test methodologies for memory, both without and with ECC. Analysis results show that the two transparenttest schemes have much lower test-time complexity compared with existing approaches. REFERENCES [1] M. Nicolaidis, Transparent BIST for RAMs, in Proc. ITC, 1992, pp [2] M. Nicolaidis, Theory of transparent BIST for RAMs, IEEE Trans. Comput., vol. 45, no. 10, pp , Oct [3] J. Sosnowski, In system transparent autodiagnostics of RAMs, in Proc. ITC, 1993, pp [4] V. Yarmolik and M. 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Franklin, Testing check bits at no cost in RAMs with on-chip ECC, Proc. Inst. Electr. Eng., E, vol. 140, no. 6, pp , Nov [18] R. Nair, Comments on An optimal algorithm for testing stuck-at faults in random access memories, IEEE Trans. Comput., vol. C-28, no. 3, pp , Mar [19] B. W. Johnson, Design and Analysis of Fault Tolerant Digital Systems. Reading, MA: Addison-Wesley, [20] S. Hellebrand, H. Wunderlich, A. Ivaniuk, Y. Klimets, and V. N. Yarmolik, Efficient online and offline testing of embedded DRAMs, IEEE Trans. Comput., vol. 51, no. 7, pp , Jul Hierarchical Verification of Galois Field Circuits Debdeep Mukhopadhyay, Gaurav Sengar, and Dipanwita Roy Chowdhury Abstract This paper proposes a hierarchical method for the formal hardware verification of Galois field architecture circuits. The reduced ordered functional decision diagram has been explored. The proposed method has been found to lead to significant gains in time and space, depending on the resources that are available. The theoretical claims that were made have been supported by experiments. Index Terms Composite field, formal verification, functional decision diagrams (DDs), Galois fields, hierarchical, multipliers. I. INTRODUCTION Over the last thirty years, Galois fields [1] have gained widespread technical applications, such as algebraic codes, cryptographic schemes, digital signal processing, random number generators, and very large scale integration testing. Because of the large number of applications of communication systems, Galois field arithmetic circuits have become increasingly important. The high complexity of the arithmetic operations that are performed in these algorithms makes formal verification [2] of such circuits of utmost necessity. However, not much research has been reported on the verification of Galois field arithmetic operations. In the works [3] [5], a decision diagram (DD) named ordered functional diagram had been introduced and further Manuscript received June 19, 2006; revised November 27, This paper was recommended by Associate Editor V. Bertacco. D. Mukhopadhyay is with the Department of Computer Science and Engineering, Indian Institute of Technology, Madras , India ( debdeep@cse.iitm.ernet.in). G. Sengar and D. R. Chowdhury are with the Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur , India ( gaurav@cse.iitkgp.ernet.in; drc@cse.iitkgp.ernet.in.). Digital Object Identifier /TCAD /$ IEEE