ECE 5745 Complex Digital ASIC Design Topic 1: Hardware Description Languages

Transcription

1 ECE 5745 Complex Digital ASIC Design Topic 1: Hardware Description Languages Christopher Batten School of Electrical and Computer Engineering Cornell University

2 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Course Structure Prereq Computer Architecture Part 2 Digital CMOS Circuits Part 1 ASIC Design Overview P M P M Part 3 CAD Algorithms ECE 5745 T01: Hardware Description Languages 2 / 55

3 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Part 1: ASIC Design Overview P M P M Topic 1 Hardware Description Languages Topic 4 Full-Custom Design Methodology Topic 6 Closing the Gap Topic 5 Automated Design Methodologies Topic 8 Testing and Verification Topic 3 CMOS Circuits Topic 2 CMOS Devices Topic 7 Clocking, Power Distribution, Packaging, and I/O ECE 5745 T01: Hardware Description Languages 3 / 55

4 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Agenda Evolution of Hardware Description Languages Hardware Description Languages Across Stack High- RTL with SystemVerilog Guarded-Atomic Actions with Bluespec System- Modeling with SystemC ECE 5745 T01: Hardware Description Languages 4 / 55

5 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Originally designers used manual translation and breadboards for verification Algorithm while b = b ( * a a > 0 ) a = a - 1 Register Transfer Gate Layout Manual Manual Manual Verification via Breadboard ECE 5745 T01: Hardware Description Languages 5 / 55

6 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Hardware description languages enabled gate-level verification via simulation Algorithm while b = b ( * a a > 0 ) a = a - 1 Register Transfer Gate Layout Manual Manual Manual Verification via Breadboard Simulation ECE 5745 T01: Hardware Description Languages 6 / 55

7 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Designers began to use HDLs for higher-level verification and design exploration Algorithm while b = b ( * a a > 0 ) a = a - 1 Register Transfer Gate Layout Manual Manual Manual Verification via Simulation Verification via Breadboard Simulation ECE 5745 T01: Hardware Description Languages 7 / 55

8 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling High-level algorithmic models act as a precise and executable specification Algorithm while b = b ( * a a > 0 ) a = a - 1 Register Transfer Gate Layout Manual Manual Manual Verification via Simulation Verification via Simulation Verification via Breadboard Simulation ECE 5745 T01: Hardware Description Languages 8 / 55

9 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Once designs were written in HDLs tools could be used for automatic translation Algorithm while b = b ( * a a > 0 ) a = a - 1 Register Transfer Gate Layout Automatic HL Synthesis Manual Automatic RTL Synthesis Manual Automatic Place & Manual Route Verification via Simulation Verification via Simulation Verification via Breadboard Simulation ECE 5745 T01: Hardware Description Languages 9 / 55

10 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Hardware Verification Languages A separate or embedded language that is meant purely for verification as opposed to simulation or synthesis Includes high-level programming features to simplify writing test benches such as object-oriented constructs and random stimulus generation Includes special language constructs for writing complex assertions Example HVLs: e, OpenVera, PSL, SystemVerilog Verification Subset Example SystemVerilog assertions Assert that the read enable and write enable signals are never both true: assert property (!(read en && write en)); Assert that priority register in round-robin arbiter is one-hot: assert property (@(posedge clk) $onehot(priority)) Assert that acknowledge signal is true cycle after the request signal is true: assert property (@(posedge clk) req -> ##[1] ack); ECE 5745 T01: Hardware Description Languages 10 / 55

11 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Agenda Evolution of Hardware Description Languages Hardware Description Languages Across Stack High- RTL with SystemVerilog Guarded-Atomic Actions with Bluespec System- Modeling with SystemC ECE 5745 T01: Hardware Description Languages 11 / 55

12 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling HDLs Across The Computer Engineering Stack Layout Circuit Gate Register Transfer Guarded Atomic Actions System Algorithm P M P M while (a>0) b = b * a a = a - 1 GDSII Modeling for Simulation MATLAB/C++ Lower- More Control Less Productive Higher- Less Control More Productive Modeling for Synthesis ECE 5745 T01: Hardware Description Languages 12 / 55

13 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Circuit- Modeling with Spice Layout Circuit Gate Register Transfer Guarded Atomic Actions System Algorithm P M P M while (a>0) b = b * a a = a - 1 * CMOS NAND gate MP CMOSP W=28.0U L=2.0U AS=252P AD=252P MP CMOSP W=28.0U L=2.0U AS=252P AD=252P MN CMOSN W=10.0U L=2.0U AS=90P AD=90P MN CMOSN W=10.0U L=2.0U AS=90P AD=90P * Input stimulus VINA 2 0 PULSE( ns 5ns 5ns 100n 200ns) VINB 1 0 PULSE( ns 5ns 5ns 200n 400ns) VDD 3 0 DC 5.0 ECE 5745 T01: Hardware Description Languages 13 / 55

14 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Gate- Modeling with Verilog Layout Circuit Gate Register Transfer Guarded Atomic Actions System Algorithm Gate-level Verilog uses structural Verilog to connect primitive gates P M P M while (a>0) b = b * a a = a - 1 module mux4( input a, b, c, d, input [1:0] sel, output out ); wire [1:0] sel_b; not not0( sel_b[0], sel[0] ); not not1( sel_b[1], sel[1] ); wire n0, n1, n2, n3; and and0( n0, c, sel[1] ); and and1( n1, a, sel_b[1] ); and and2( n2, d, sel[1] ); and and3( n3, b, sel_b[1] ); wire x0, x1; nor nor0( x0, n0, n1 ); nor nor1( x1, n2, n3 ); wire y0, y1; or or0( y0, x0, sel[0] ); or or1( y1, x1, sel_b[0] ); nand nand0( out, y0, y1 ); b d a c sel[1] sel[0] endmodule out ECE 4750 Computer Architecture Verilog Basics 25 ECE 5745 T01: Hardware Description Languages 14 / 55

15 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Low- RTL Modeling with Verilog Layout Circuit Gate Register Transfer Guarded Atomic Actions System Algorithm P M P M while (a>0) b = b * a a = a - 1 // Combinational Logic: Operand Muxes wire [63:0] a_mux_out = ( a_mux_sel == op_load )? { 32 b0, unsigned_a } : ( a_mux_sel == op_next )? a_shift_out : 64 bx; wire [31:0] b_mux_out = ( b_mux_sel == op_load )? unsigned_b : ( b_mux_sel == op_next )? b_shift_out : 32 bx; reg [4:0] counter_reg; reg sign_reg; reg [63:0] a_reg; reg [31:0] b_reg; reg [63:0] result_reg; // Sequential State ( posedge clk ) begin if ( sign_en ) begin sign_reg <= sign_next; end if ( result_en ) begin result_reg <= result_mux_out; end counter_reg a_reg b_reg end <= counter_mux_out; <= a_mux_out; <= b_mux_out; ECE 5745 T01: Hardware Description Languages 15 / 55

16 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Simulation vs. Synthesis Mismatch Layout Circuit Gate Register Transfer Guarded Atomic Actions System Algorithm P M P M while (a>0) b = b * a a = a - 1 // Mux with assign statement wire [3:0] out = ( sel == 0 )? a : b; What happens if the sel signal contains an X? // Mux with always block reg [3:0] out; begin if ( sel == 0 ) out = a; else out = b; end ECE 5745 T01: Hardware Description Languages 16 / 55

17 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Higher- HDLs Layout Circuit Gate Register Transfer Guarded Atomic Actions System Algorithm P M P M while (a>0) b = b * a a = a - 1 How can we raise the level of abstraction to increase hardware design productivity? High- Register-Transfer- Modeling with SystemVerilog Guarded Atomic Actions with Bluespec System- Modeling with SystemC ECE 5745 T01: Hardware Description Languages 17 / 55

18 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Agenda Evolution of Hardware Description Languages Hardware Description Languages Across Stack High- RTL with SystemVerilog Guarded-Atomic Actions with Bluespec System- Modeling with SystemC ECE 5745 T01: Hardware Description Languages 18 / 55

19 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling SystemVerilog: Struct and Union Types 8 24 JUMP addr // Declare JumpInstr structure typedef struct packed { logic [7:0] opcode; logic [23:0] addr } JumpInstr; // Instantiate JumpInstr structure JumpInstr instr; instr.opcode = c_opcode_jump; instr.addr = addr; JumpInstr instr = { opcode: c_opcode_jump, addr: addr }; ADD rd rt rs // Declare AddInstr structure typedef struct packed { logic [7:0] opcode; logic [4:0] rd; logic [4:0] rt; logic [4:0] rs; logic [8:0] null; } AddInstr; // Declare Instr union typedef union packed { JumpInstr jump; AddInstr add; } Instr; // Instantiate Instr union Instr instr; instr.jump.opcode = c_opcode_jump; instr.jump.addr = addr; ECE 5745 T01: Hardware Description Languages 19 / 55

20 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling SystemVerilog: Tagged Union Types 8 24 JUMP addr // Declare Instr w/ common opcode typedef struct packed { logic [23:0] addr } JumpInstrFields; typedef struct packed { logic [4:0] rd; logic [4:0] rt; logic [4:0] rs; logic [8:0] null; } AddInstrFields; typedef union packed { JumpInstrFields jump; AddInstrFields add; } InstrFields; typedef struct packed { logic [7:0] opcode; InstrFields fields; } Instr; ADD rd rt rs // Declared Instr tagged union typedef union tagged packed { JumpInstrFields jump; AddInstrFields add; } Instr; // Instantiate Instr tagged union Instr instr = tagged jump { addr: addr }; // Pattern matching case ( instr ) matches tagged add: cs={ sel_a, y }; tagged jump: cs={ sel_b, n }; endcase ECE 5745 T01: Hardware Description Languages 20 / 55

21 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling SystemVerilog: Typed Ports and Type Parameters // Structs, unions, tagged unions // can be used as ports module InstrDecodeTable ( input Instr instr, output ControlSigs cs ) // Type parameter allows more // expressive polymorphism module Queue #( parameter type ItemType )( input clk, reset // Use structure selectors // to access instruction // and control signal fields input output input enq_val, enq_rdy, ItemType enq_item, endmodule ) output deq_val, input deq_rdy output ItemType deq_bits, // Use \$bits for size of item endmodule // Instantiate polymorphic queue Queue#(Instr) queue(... ) ECE 5745 T01: Hardware Description Languages 21 / 55

22 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling SystemVerilog: Port Bundle Interfaces // Declare valrdy interface interface ValRdyIfc; logic val; logic rdy; logic [31:0] msg; modport send_ifc( output val, input rdy, output msg ); modport recv_ifc( input val, output rdy, input msg ); endinterface // Instantiate and use interface // Using an interface module Producer ( input clk, reset, ValRdyIfc.send_ifc send_ifc ) //... posedge clk ) begin send_ifc.val =... send_ifc.msg =... end endmodule ValRdyIfc channel; Producer producer(channel); Consumer consumer(channel); ECE 5745 T01: Hardware Description Languages 22 / 55

23 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling SystemVerilog: Method Interfaces // Declare valrdy method interface interface ValRdyIfc; logic val; logic rdy; logic [31:0] msg; //... function send ( input logic [31:0] msg ); //... endfunction function is_send_done ( output logic done ); //... endfunction endinterface // Using an method interface module Producer ( input clk, reset, ValRdyIfc.send_ifc send_ifc ) //... logic done; posedge clk ) begin send_ifc.send( msg ); send_ifc.is_send_done( done ); if ( done )... end endmodule ECE 5745 T01: Hardware Description Languages 23 / 55

24 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling SystemVerilog: Interfaces Master Ifc Bus Fabric Ifc Ifc Slave Slave ECE 5745 T01: Hardware Description Languages 24 / 55

25 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Agenda Evolution of Hardware Description Languages Hardware Description Languages Across Stack High- RTL with SystemVerilog Guarded-Atomic Actions with Bluespec System- Modeling with SystemC ECE 5745 T01: Hardware Description Languages 25 / 55

26 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Designers Usually Use Weak Interfaces Example: Commercially available FIFO IP block data_in data_out push_req_n full pop_req_n clk empty rstn These constraints are spread over many pages of the documentation... Adapted from [Arvind 11] ECE 5745 T01: Hardware Description Languages 26 / 55

27 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Expressing Hardware with Guarded Atomic Actions in Bluespec Guarded rules Hardware expressed as collection of rules that execute atomically and in a well-defined serialized sequence Allows thinking of pieces of the design in isolation Compiler manages scheduling of rules to increase performance Guarded method interfaces Formalizes composition Compiler manages connectivity (muxing and control logic) Powerful type and static elaboration facilities Significant amount of compile-time static checking Permits parameterization of designs at all levels ECE 5745 T01: Hardware Description Languages 27 / 55

28 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Guarded Atomic Action Execution Model Semantics Actions execute in a serialized order Actions execute in isolation Repeatedly Select a rule to execute (highly non-deterministic) Compute the new state values Update the state Implementation concerns But doesn t executing one rule at a time mean our implementation will be very slow? Can we schedule multiple rules concurrently without violating one-rule-at-a-time semantics? Work through extra notes... ECE 5745 T01: Hardware Description Languages 28 / 55

29 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling State and Rules Organized into Modules module interface All state is explicit (no inferred latches or flip-flops) Behavior is expressed in terms of guarded rules within each module that atomically update state internal to that module Rules can manipulate state in other modules only via their guarded method interfaces Adapted from [Arvind 11] ECE 5745 T01: Hardware Description Languages 29 / 55

30 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling GCD Using Euclid s Algorithm def gcd( x, y ): while True: if x > y: x,y = y,x elif y!= 0: y = y - x else: return x x y op swap sub swap sub swap sub sub return x ECE 5745 T01: Hardware Description Languages 30 / 55

31 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling GCD Implementation in Bluespec module mkgcd (I_GCD); Explicit Reg#(Int#(32)) x <- mkregu; State Reg#(Int#(32)) y <- mkreg(0); Internal Behavior rule swap ((x > y) && (y!= 0)); x <= y; y <= x; endrule rule sub ((x <= y) && (y!= 0)); y <= y x; endrule x swap y sub External Interface method Action start(int#(32) a, Int#(32) b) if (y==0); x <= a; y <= b; endmethod method Int#(32) result() if (y==0); return x; endmethod endmodule Adapted from [Arvind 11] ECE 5745 T01: Hardware Description Languages 31 / 55

32 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling GCD Alternative Implementation Combined Rule module mkgcd (I_GCD); Reg#(Int#(32)) x <- mkregu; Reg#(Int#(32)) y <- mkreg(0); rule swapsub ((x > y) && x <= y; y <= x - y; endrule (y!= 0)); rule sub ((x <= y) && (y!= 0)); y <= y x; endrule x y op swapsub swapsub swapsub sub return x method Action start(int#(32) a, Int#(32) b) if (y==0); x <= a; y <= b; endmethod method Int#(32) result() if (y==0); return x; endmethod endmodule Adapted from [Arvind 11] ECE 5745 T01: Hardware Description Languages 32 / 55

33 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Generated GCD Hardware: Interface Int#(32) y == 0 implicit conditions y == 0 Int#(32) enab rdy Int#(32) rdy start result GCD module Module can easily be made polymorphic as in SystemVerilog Many different implementations can provide the same interface Adapted from [Arvind 11] ECE 5745 T01: Hardware Description Languages 33 / 55

34 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Generated GCD Hardware: Rules x y en rdy start x_en x y_en y >!(=0) sub next state values x rdy result predicates swap? subtract? rule swap ((x>y)&&(y!=0)); x <= y; y <= x; endrule rule subtract ((x<=y)&&(y!=0)); y <= y x; endrule x_en = y_en = swap? swap? OR subtract? Adapted from [Arvind 11] ECE 5745 T01: Hardware Description Languages 34 / 55

35 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Generated GCD Hardware: Rules and Methods x y en rdy start start_en x_en x start_en y_en y >!(=0) sub x rdy result swap? subtract? x_en = swap? OR start_en y_en = swap? OR subtract? rdy = (y==0) OR start_en Adapted from [Arvind 11] ECE 5745 T01: Hardware Description Languages 35 / 55

36 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling A Systematic Approch to GAA Synthesis A rule may be decomposed into two parts π(s) and δ(s) such that s next = if π(s) then δ(s) else s π(s) is the condition (predicate) of the rule, a.k.a. the CAN_FIRE signal of the rule. π is a conjunction of explicit and implicit conditions δ(s) is the state transformation function, i.e., computes the next-state values from the current state values Adapted from [Arvind 11] ECE 5745 T01: Hardware Description Languages 36 / 55

37 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Compiling a Rule rule r (f.first() >0) ; x <=x +1 ; f.deq (); endrule enable current state f x π δ f x next state values π = enabling condition δ =action signals & values Adapted from [Arvind 11] ECE 5745 T01: Hardware Description Languages 37 / 55

38 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Combining State Updates (strawman) π s from the rules that update R π 1 π n OR latch enable δ s from the rules that update R δ 1,R δ n,r OR next state value R What if more than one rule is enabled? Adapted from [Arvind 11] ECE 5745 T01: Hardware Description Languages 38 / 55

39 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Combining State Updates π s from all the rules π 1 π n Scheduler: Priority Encoder φ 1 φ n OR one-rule-at-atime scheduler is conservative latch enable δ s from the rules that update R δ 1,R δ n,r OR next state value R Scheduler ensures that at most one φ i is true Adapted from [Arvind 11] ECE 5745 T01: Hardware Description Languages 39 / 55

40 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Scheduling and Control Logic Modules (Current state) Rules CAN_FIRE π 1 WILL_FIRE φ 1 Modules (Next state) π 1 π n Scheduler φ n δ 1 cond action π n δ n δ 1 δ n Muxing Compiler synthesizes a scheduler such that at any given time φ s for only non-conflicting rules are true Adapted from [Arvind 11] ECE 5745 T01: Hardware Description Languages 40 / 55

41 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Agenda Evolution of Hardware Description Languages Hardware Description Languages Across Stack High- RTL with SystemVerilog Guarded-Atomic Actions with Bluespec System- Modeling with SystemC ECE 5745 T01: Hardware Description Languages 41 / 55

42 CA 92697, USA Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling System- Modeling Communication Separate computation/storage from communication - e e - s - Approximatetimed Cycletimed D C F E A. Specification model B. Component-assembly model C. Bus-arbitration model D. Bus-functional model E. Cycle-accurate computation model F. Implementation model Cycletimed Untimed A B Untimed Approximatetimed Computation Figure 1: System modeling graph Adapted from [Cai 03] ECE 5745 T01: Hardware Description Languages 42 / 55

43 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Specification Model B1 v1 = a*a; Describes system functionality without any implementation details B2B3 B2 v2 = v1 + b*b; v2 v1 B3 v3= v1- b*b; v3 Computation modeled as abstract concurrent processes Communication modeled with standard software variables B4 v4 = v2 + v3; c = sequ(v4); Figure 2: The example of specification model Adapted from [Cai 03] ECE 5745 T01: Hardware Description Languages 43 / 55

44 c = sequ(v4); Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling TLM: Component-Assembly Model igure 2: The example of specification model PE1 B1 PE2 v1 = a*a; cv12 cv11 PE3 B3 v3= v1- b*b; v3 Approximately estimate execution time of PEs using first-order models Explicitly capture process-to-pe mapping Use dedicated point-to-point channels to interconnect computation and storage PEs B2 v2 = v1 + b*b; cv2 B4 v4 = v2 + v3; c = sequ(v4); No modeling of bus or protocol details re 3: The example of component-assembly el Adapted from [Cai 03] ECE 5745 T01: Hardware Description Languages 44 / 55

45 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling TLM: Bus-Arbitration Model PE1 B1 PE2 v1 = a*a; B2 v2 = v1 + b*b; PE4 (Arbiter) 3 cv12 cv2 1 2 cv11 1. Master interface 2. Slave interface 3. Arbiter interface PE3 B3 v3= v1- b*b; v3 B4 v4 = v2 + v3; c = sequ(v4); Figure 4: The example of bus-arbitration model to timed functional model defined in [12]. In comparison to specification model, component-assembly model explicitly specifies the allocated PEs in the system architecture and process-to-pe mapping decision. The example of component-assembly model is displayed in Figure 3. PE1, Approximately estimate address[15:0] execution time of PEs data[31:0] using first-order models ready ack Explicitly capture channels, but CLK also address[15:0] data[31:0] performance with ready first-order arbitration ack (5, 15) (5, 2 (10, 20) channel-to-bus mapping Still communicate through abstract estimate bus models Lowerbound = Upperbound = (a)time Diag (b)cycle accurate Figure 5: Time/cycle accu Adapted from [Cai 03] ECE 5745 T01: Hardware Description Languages 45 / 55 PE4

46 ready Evolution of HDLs ack HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling PE1 B1 PE2 (b)cycle accurate time diagram TLM: Bus-Functional Model Figure 5: Time/cycle accurate diagram v1 = a*a; B2 v2 = v1 + b*b; PE4 (Arbiter) 3 address[15:0] address[15:0] data[31:0] data[31:0] 1 ready 2 ack ready ack IProtocolSlav 1. Master interface 2. Slave interface 3. Arbiter interface e PE3 B3 v3= v1- b*b; v3 B4 v4 = v2 + v3; c = sequ(v4); Approximately estimate execution time of PEs using first-order models Cycle-accurate RTL model of bus protocol Figure 6: The example of bus-functional model In bus-functional model, the message-passing channels are replaced by protocol channels. A protocol channel is time/cycleaccurate and pin-accurate. Inside a protocol channel, wires of the bus are represented by instantiating corresponding variables/signals. Data is transferred following the time/cycle Adapted from [Cai 03] ECE 5745 T01: Hardware Description Languages 46 / 55

47 Cycle-accurate approximate cycle-accurate abstract bus channel pin-acc computation model Implementation model cycle-accurate cycle-accurate wire pin-acc Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling PE1 B1 PE2 v1 = a*a; B2 v2 = v1 + b*b; TLM: Cycle-Accurate Computation Model PE4 (Arbiter) 3 cv12 cv2 1 2 cv11 1. Master interface 2. Slave interface 3. Arbiter interface 4. Wrapper Table 1: Characteristics of different abstraction models 4 PE3 Figure 7: The example of cycle-accurate computation model model. In this model, computation components (PEs) are pin accurate and execute cycle-accurately. The custom hardware components are modeled at register-transfer level, and general-purpose processors and DSPs are modeled in terms of cycle-accurate instruction set architecture. To enable communication between cycle-accurate PEs and abstract level interfaces of abstract bus channels, wrappers which S0 S1 S2 S3 S4 Cycle-accurate RTL PE4 PE1 interrupt interrupt model of (some) PEs req MOV r1, 10 MUL r1, r1, r1... S0 Still communicate S1 through abstract S2 channels, S3 but also interrupt req Adapters interface lower-level RTL interface to higher-level bus-arbitration model estimate bus performance with first-order arbitration models PE3 S0 S1 S2 S3 S4 PE2 MLA... r1, r... Figure 8: The example of implem 4. SYSTEM DESIGN Adapted from WITH [Cai 03] T ECE 5745 T01: Hardware Description Languages 47 / Design Flow

48 ccurate wire pin-accurate Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling fferent abstraction models Register-Transfer- Model interrupt req PE1 MOV r1, 10 MUL r1, r1, r1... interrupt req PE2 MLA... r1, r2, r2, r1... Cycle-accurate RTL models of both computation/storage and communication MCNTR MADDR MDATA PE4 PE3 S0 S1 S2 S3 interrupt S0 S1 S2 S3 S4 Figure 8: The example of implementation model Adapted from [Cai 03] ECE 5745 T01: Hardware Description Languages 48 / 55

49 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling SystemC Framework Methodology-Specific Libraries Master/Slave Lib, Verification Lib, Static Dataflow Primitive Channels Signal, Mutex, Semaphore, FIFO Core Language Modules Ports Processes Interfaces Channels Data Types 4-Valued Logic Types 4-Valued Logic Vectors Bits and Bit Vectors Fixed-Point Types C++ User-Defined Types Event-Driven Simulation Kernel C++ Language Standard ECE 5745 T01: Hardware Description Languages 49 / 55

50 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling SystemC Modules, Processes, Channels Separate computation from communication Computation: implemented with Processes in Modules Communication: implemented in Channels Interface method calls Collection of a fixed set of communication Methods is called an Interface Channels implement one or more Interfaces Modules can be connected via their Ports to those Channels which implement the corresponding Interface Adapted from [Moondanos 04] ECE 5745 T01: Hardware Description Languages 50 / 55

51 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling SystemC Producer-Consumer Example struct Producer : public { // Ports sc_out<bool> clk; sc_out<int> value; sc_module } }; SC_HAS_PROCESS(Producer); Producer( sc_module_name name ) : sc_module(name) { // Declares compute as a thread SC_THREAD(compute); } void compute() { for ( int i = 0; i < 10; ++i ) { clk.write(false); // toggle clk wait( 5, SC_NS ); // wait for 5 nanoseconds clk.write(true); // toggle clk value.write(i); // write value to channel wait( 5, SC_NS ); // wait for 5 nanoseconds } ECE 5745 T01: Hardware Description Languages 51 / 55

52 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling SystemC Producer-Consumer Example struct Consumer : public sc_module { // Ports sc_in<bool> clk; sc_in<int> value; SC_HAS_PROCESS(Consumer); Consumer( sc_module_name name ) : sc_module(name) { // Declares receive() as a process triggered // on clk value changes SC_METHOD(receive); sensitive << clk; } void receive() { // If clk is changing from false to true if ( clk.posedge() ) std::cout << Received: << value.read() << std::endl; } }; ECE 5745 T01: Hardware Description Languages 52 / 55

53 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling SystemC System Adapted from [Moondanos 04] ECE 5745 T01: Hardware Description Languages 53 / 55

54 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Take-Away Points Layout Circuit Gate Register Transfer Guarded Atomic Actions System Algorithm P M P M while (a>0) b = b * a a = a - 1 Hardware description languages involve a four-way tension Low-level languages offer more control but less productivity High-level languages offer less control but more productivity Simulation features for modeling function and test harnesses Synthesis features for modeling actual hardware Hardware description languages are (slowly) moving towards including higher abstractions to improve productivity such as Types, Interfaces (SystemVerilog) Guarded Atomic Rules, Guarded Method Interfaces (Bluespec) Transaction- Modeling (SystemC) ECE 5745 T01: Hardware Description Languages 54 / 55

55 Evolution of HDLs HDLs Across Stack High- RTL Guarded-Atomic Actions System- Modeling Acknowledgments [Arvind 11] Arvind, Introduction to Bluespec, MIT Complex Digital Systems, Lecture, [Cai 03] L. Cai and D. Gajski, Transaction Modeling: An Overview, Int l Conf. on Hardware/Software Codesign and System Synthesis, Oct [Moondanos 04] J. Moondanos, SystemC Tutorial, UC Berkeley EE 249 Embedded System Design, Guest Lecture, ECE 5745 T01: Hardware Description Languages 55 / 55