Fundamental Design Concepts. Fundamental Concepts. Modeling Domains. Basic Definitions. New terminology and overloaded use of common words

Transcription

1 Fundamental Design Concepts Fundamental Concepts Basic Definitions study now revisit later New terminology and overloaded use of common words Modeling Domains Structural Domain a domain in which a component is described in terms of an interconnection of more primitive components. Behavioral Domain a domain in which a component is described in terms of its I/O response. 1

2 Structural description Behavioral Description entity TWO_CONSECUTIVE is port(clk,r,x: in BIT;Z: out BIT); end TWO_CONSECUTIVE; architecture DATAFLOW of TWO_CONSECUTIVE is signal Y1,Y0: BIT; STATE: block((clk = 1 and not CLK STABLE) or R = 0 ) Y1 <= guarded 0 when R = 0 else X; Y0 <= guarded 0 when R = 0 else 1 ; end block STATE; Z <= Y0 and ((not Y1 and not X) or (Y1 and X)); end DATAFLOW; entity MULT_B0 is port ( IN0 : in STD_LOGIC_VECTOR(7 downto 0) ; DSP OUTPUT : out STD_LOGIC_VECTOR(7 downto 0) ) ; Multiplier end 1 MULT_B0 ; 1 architecture behavior of MULT_B0 is constant 2 RoundProdWidth_M_M1_1_1: INTEGER := 8 ; 2 main: process(in0) variable Input2_M_M1_1_1: SIGNED(7 DOWNTO 0) ; 3 variable RoundProd_M_M1_1_1: SIGNED(RoundProdWidth_M_M1_1_1-1 DOWNTO 0); 3 Input2_M_M1_1_1 := const2fxp(0, 12, 1, 8); RoundProd_M_M1_1_1 := fxp_round(signed(in0) * Input2_M_M1_1_1, 0, RoundProdWidth_M_M1_1_1); OUTPUT <= STD_LOGIC_VECTOR(fxp_saturate(RoundProd_M_M1_1_1, 1, 8)); 4 end process main; 4 end behavior ; Synthesized DSP Multiplier 2

3 Abstraction Hierarchy Abstraction Hierarchy a set of interrelated representation levels that allow a system to represented in varying amounts of detail Helps designer maintain perspective SILICON LEVEL Structural: Behavioral: None Vi Structural: G G S CIRCUIT LEVEL S D D V+ P N Vout Behavioral: Differential Eq. Spice HDL-AMS Inverter 3

4 S Structural: Q Behavioral: Boolean Eq. R Q S Q GATE LEVEL R Q REGISTER LEVEL Structural: REG Select CLK A MUX CLK B REG INC Behavioral: Data Flow HDL Structural: Microprocessor CHIP LEVEL 8 RAM Parallel Port USART 8 8 Interrupt Controller Behavioral: Algorithmic HDL 4

5 SYSTEM LEVEL Structural: IMU A/B Computer RADAR C/D Behavioral: Abstract HDL, Performances Specs Hardware Description Language Hardware Description Language a high level programming language with special constructs for modeling hardware. Special constructs for modeling: Delay Concurrency Interconnection Interaction Behavioral Descriptions Procedural code Non-structural Models cannot be decomposed Source language type for current VHDL and Verilog synthesis tools Two classes of behavioral modeling: Algorithmic Data Flow 5

6 Algorithmic Descriptions A behavioral description in which the procedure definition the I/O response is not meant to imply any particular physical implementation Used to verify an algorithm or architecture Abstract, thus retargetable Timed (gross) or untimed Some people call algorithmic descriptions behavioral Language Characteristics of Algorithmic Descriptions Abstract representation of states and signals, e.g. enumerative types and integers Use conventional programming control constructs, e.g. if, case, and loop Data flow not explicitly represented architecture ALGORITHMIC of EE TWO_CONSECUTIVE 4514 is type STATE is (S0,S1,S2); signal Q: STATE := S0; process(r,x,clk,q) if (R EVENT and R = 0 ) then --reset event Q <= S0; elsif (CLK EVENT and CLK = 1 ) then --clock event if X = 0 then 2 Q <= S1; else Algorithmic Description 3 Q <= S2; end if; end if; 3 4 if Q EVENT or X EVENT then --output function if (Q=S1 and X= 0 ) or (Q=S2 and X= 1 ) then Z <= 1 ; else Z <= 0 ; end if; end if; 4 end process; end ALGORITHMIC; 6

7 Data Flow Description A behavioral description in which the data dependencies in the description match those in a real implementation Descriptions represent the result of state machine and K map design Data paths explicitly represented Language Characteristics of Data Flow Descriptions Low level representation of states and interconnect (BIT, STD_LOGIC) Uses signal assignment statements representing combinational logic and registering Some people call data flow RTL entity TWO_CONSECUTIVE is port(clk,r,x: in BIT;Z: out BIT); end 1 TWO_CONSECUTIVE; 1 architecture DATAFLOW of TWO_CONSECUTIVE is 2 signal Y1,Y0: BIT; 2 STATE: block((clk = 1 and not CLK STABLE) or R = 0 ) Y1 <= guarded 0 when R = 0 else X; Y0 <= guarded 0 when R = 0 else 1 ; 3 end block STATE; 3 Z <= Y0 and ((not Y1 and not X) or (Y1 and X)); end 4 DATAFLOW; 4 Data Flow Description 7

8 Synthesis Dictionary: to put something together Digital CAD:Synthesis the process of transforming one representation in the design hierarchy to another Level I is used as a guide for level I+1 Synthesis Transformations Industrial Synthesis Behavioral (Algorihmic): Algorithmic behavioral to gate structural being developed Logic Synthesis: Data flow(rtl) to gate structural established practice Layout Synthesis: Gate structural to layout established practice 8

9 Design A series of transformations from one representation of a system to another, until a representation exists that can be fabricated. A series of synthesis steps Design productivity must grow faster than chip complexity Automation of these steps is the goal of digital CAD Design Decomposition Complexity manager Divide and conquer Component problems are easier to solve Allows for concurrent activity HDL must support decomposition Full Tree Design 9

10 Partial Tree Design Structural Modeling Top Down Design Begin at the top. Partition according to some objective criterion. No appriori" knowledge of available lower level components. Advantage: optimized partition. Disadvantage: unique level components. Bottom Up Design Begin at the top. Partition to take advantage of available lower level components. Lower level components were designed first. Advantage: use available components. Disadvantage: partitioning is non-optimal. 10

11 Design Window: a range of levels of abstraction over which a designer works. Two Important Windows: VLSI Chip Designer s: chip register gate silicon(?) System Designer s: system chip register(?) gate(?) Design Windows Design Space There exists no algorithm for the design of complicated systems The designer moves around in a space The co-ordinates of the space are optimization criterion: speed, chip area, cost, power, pinout etc. Motion in the space involves tradeoffs A Three Dimensional Design Space a design 11

12 Workstation Cost/Speed Trade-off Cost ($) (C2,S2) C1 S1 $ 5K 50 MIPS (C3,S3) C2 S2 C3 $ 30K 500 MIPS $ 10K (C1,S1) S3 280 MIPS Speed (MIPS) Speed/Area Tradeoff 12