VFSim: Concurrent Fault Simulation at Register Transfer Level

Transcription

1 Mar. 2005, Vol.20, No.2, pp J. Comput. Sci. & Technol. VFSim: Concurrent Fault Simulation at Register Transfer Level Li Shen Institute of Computing Technology, Chinese Academy of Sciences, Beijing , P.R. China Received February 2, 2004; revised January 20, Abstract VLSI testing is being pushed to the high-level based technology. In this paper a Verilog Register transfer level Model (VRM) for integrated circuits is proposed. The model provides a text format file, which is convenient and more practical for developing succeeding Register Transfer Level (RTL) test tools, such as fault simulation, test pattern generation and so forth. Based on the VRM, an RTL concurrent fault simulation approach is presented. After RTL fault models and super faults defined, the concurrent fault simulation algorithm is given. The corresponding RTL concurrent fault simulator, VFSim, was implemented. The initial experiments show that the RTL fault simulator is efficient for VLSI circuits. Keywords high-level testing, Verilog, RTL, circuit modeling, fault model, concurrent fault simulation. 1 Introduction Integrated circuit (IC) design has been pushed to the high-level techniques using hardware description language (HDL) description and high-level synthesis (HLS). IC testing is also going to its high-level as well. In general, the high-level testing can be roughly divided into two classes. One is the algorithm behavioral level testing, or simply called behavioral level testing. Another is the RTL behavioral level testing or called RTL testing. The difference is that the RTL behaviors can be used to describe the hardware structure and clock system more clearly and efficiently. In fact, most IC chip designs start from register transfer level. So here high-level testing means at RTL level. For the gate level testing, it needs gate level circuit models. The circuit modeling is quite straightforward. That is the interconnections of primitive elements of the circuit. Similarly, the RTL testing needs RTL circuit models. However, for HDL described RTL circuits, the circuit modeling can be more complex. Depending on what kind of testing approach to be used, one can construct different models. The behavioral testing essentially belongs to software testing. It can use the language model itself. Fallah et al. proposed a simulation vector generation approach using a combination of integer linear programming and Boolean satisfiability [1]. Based on genetic algorithms, Corno et al. reported a series of works on the high-level test generation [2]. For the RTL testing, in fact, it started as early as two decades ago. Those works are natural extensions of the gatelevel techniques, and mainly focus on data-flow intensive descriptions. Levendel and Menon proposed a directed graph of functional elements for an extended D- algorithm [3]. Murray and Hayes used pre-computed test sets of modules for test generation [4]. Roy and Abraham presented a hierarchical test generation [5]. However, this kind of circuit models is not easy for practical usage. Another approach adopts some techniques from the high-level synthesis. Ferrandi et al. used BDD models for each bit. But it will encounter an efficiency problem due to the size of BDDs for large circuits [6]. Bhatia and Jha used the control-data flow graph (CDFG) model for behavioral synthesis of testable circuits. It generates module test sets only as a byproduct of synthesis [7]. Ghosh and Fujita proposed a good approach using the assignment decision diagram (ADD) model for generating RTL tests. But it is a flatting model and may be complex for large circuits [8]. For high-level testing, it needs a good model such that the model is easy to be converted and extended from HDL descriptions; the model should be unified for multiple usages such as fault simulation, test generation, testability measure, etc; for various algorithms, it is easy to perform forward and backward tracing on the model, and easy to define fault models. In this paper, we try to construct such a model and apply it to the fault simulation first. Currently, Verilog HDL is widely used for IC chip design in industry. We propose a new model, the Verilog RTL Model (VRM) for circuits described in Verilog HDL. The purpose of VRM is that based on the VRM, one can develop more practical and efficient EDA tools, such as RTL fault simulation, RTL test generation and so on. Of course the idea of the model can also be used for VHDL and other HDLs. A VRM tool has been developed based on the ICRUSE Verilog Compilation System (Verilog 0.6.1) [9], which is one of the GNU free software. As an end module of the ICARUS Verilog system, the VRM tool extracts the internal data during source compiling and generates the VRM circuit model, then outputs the text format file of the model, which Regular Paper This work was supported by the National High-Technology Development 863 Program of China under Grant No.2001AA This paper is based on two preliminary papers presented at the IEEE 4th Workshop on RTL and High Level Testing, (WRTLT 03).

2 176 J. Comput. Sci. & Technol., Mar. 2005, Vol.20, No.2 can be used by succeeding tools. The fault simulator is an important tool for evaluating the test set quality or fault coverage of circuit under test. Fault oriented test generation algorithms also need the fault simulation. However, for the RTL fault simulation, few works appeared in literature up to now. Corno et al. reported a serial fault simulation strategy only by injecting RTL faults into a logic simulator [10]. There are three typical fault simulations in the gate levels, i.e., parallel, deductive and concurrent [11]. In fact, the most efficient approach is the parallel simulation, like PROOFS [12] and HOPE [13]. However, at the RTL, the logic value dealt with will be for word, instead of bit. So the concurrent simulation may be the unique choice. Based on the VRM model, we propose an RTL concurrent fault simulation approach. The corresponding fault simulator, VFSim, has been implemented first time. In this paper, we use two sets of benchmark circuits, POLITO-ITC 99 benchmarks of Politecnico di Torino [14], which are rewritten in Verilog, and CMUDSP benchmarks of CMU [15]. In the rest of paper, first, the VRM model is presented in Section 2. Then, based on VRM, the RTL fault models are defined in Section 3, the RTL logic simulation is briefly discussed in Section 4, the RTL concurrent fault simulation is given in Section 5, and the experimental results are shown in Section 6. Finally, the conclusion is in Section 7. 2 Verilog RTL Model 2.1 Verilog HDL Subset The ICARUS Verilog [9] is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. However, for chip design at RTL, one mainly adopts the Verilog behavioral description. The structural description and data flow description can be restricted in a small scope. Thus, VRM only supports a subset of Verilog HDL by now. Usually, Verilog HDL circuit descriptions adopt three kinds of modeling methods [16] Structure Modeling There are three kinds of instantiation statements, gate, UDP and module. The structure modeling is mainly used at gate level. In current, VRM only supports the module statement for establishing description hierarchy Data Flow Modeling The continuous assignment, assign canbeusedto describe combinational logic circuits. In fact, almost practical chips are sequential, and the behavioral description can also be used for combinational circuits. Therefore, currently VRM does not support the assign for describing combinational logic, except for net connections, such as bus description, signal concatenation, etc Behavior Modeling Chip RTL descriptions mainly use the behavior modeling. Here, we only consider the chip functional description, but test bench. So the initial statement is not needed. Furthermore, in general, the EDA synthesis tool has some restrictions on elements of Verilog from the synthesisability consideration, such as not supporting integer variable, loop statements and so forth. Finally, since most of test tools are not for delay faults, so VRM does not deal with the delay description. Now, we give the subset of the Verilog language elements supported by VRM as follows. (i) Module declaration module name ( ports ); {module item} endmodule (ii) Module item Declarations: input, output, inout, wire, wor, wand, reg, function, parameter Statements: always,assign,module instantiation (iii) Statements in the always and function Blocking assignment: = Non-blocking assignment: <= Edge trigger event Condition: if Case: case, casex, casez (iv) Data type Net: wire, wor, wand Register: reg (v) Expression Operand and operator: all elements 2.2 VRM Model Structure VRM is a hierarchical directed graph model. The top level is the circuit graph (CKT), which consists of circuit nodes (k-node). The k-node can be variable, process (always), function and so on. It represents an interconnect network of multiple parallel processes. The next level is the Control Flow Graph (CFG), which represents the program flow of a process and function. The CFG nodes (c-node) are statements. Finally, the bottom level is the Data Flow Graph (DFG), which is the expression of a statement with a tree-like structure. The DFG nodes (d-node) represent operands and operators of an expression. (i) k-nodes: Primary input/output nodes: PI, PO, and PIO. Internal input/output node: IIO. Net nodes: WIRE, WOR, and WAND. The net node may have two kinds of fanins, single fanin with the

3 Li Shen: Concurrent Fault Simulation at Register Transfer Level 177 same node width, and n bit-fanins to be concatenated, where n is the node width. Variable reg nodes: VR for register, VM for memory, and VF for input parameter and internal variable of a function. Event node: E for edge trigger event. Each fanin of E must be the bit signal, and its value is the edge {positive edge, negative edge, any edge}. However, the node value is logic value {0, 1} Process node: P for always statement. The process node is associated with its CFG. The execution of process is triggered by its fanin node E. The fanouts of P point to VR and VM assigned in the process. Function node: F for function statement. The function node is also associated with its CFG and has its node value, i.e., function output value. The fanins of F are input parameters of a function. The function is called in a DFG. Node F may have fanouts pointing to internal variables VF assigned in the function. Tri-state bit nodes: BIO for bufif0 gate, and BI1 for bufif1 gate. There are two fanins, data bit and control bit. Bit nexus nodes: NEX for tri-state type net, and NEXL for OR/AND type net. The nexus node connects multiple drivers, which are bit signals. LPM (Library of Parameterized Modules) element node: Only one is defined by now, that is the RAM for memory read-out. Its fanins are VM and address variable. (ii) c-nodes: Statement nodes: assignment AB, and AN, and control IF, CS, CX, and CZ. The statement node is associated with the corresponding DFG and has its entry(s) and exit(s). For IF/CS/CX/CZ, the number of exits equals the number of branches plus one more exit, which points to its terminal node. Terminal node of statement branches: TM. (iii) d-nodes Input nodes from k-nodes: VI for variables, MI for memory, and FI for function value. The input node is associated with the corresponding k-node. VI has no fanin, MI has an address d-node as fanin, and FI has function input parameters as fanins and calls the function to be executed. Output nodes to k-nodes: VO for variables, SO for out bit selection of variable, and MO for memory. The output node is also associated with the corresponding k-node and has the right-value of the expression as fanin. Furthermore, SO and MO has one more fanin, out variable pin and address respectively. Operator nodes: there are 10 unary operators, 23 binary operators and 1 ternary operator. The operator node has its operand d-node(s) as fanin(s). Other nodes: CI for constant, CC for concatenation, SL for partial bits selection of variable, SLB for bit selection of variable, and CBI for branch index of case statement. 2.3 VRM Model Generation VRM, as an end module, is embedded into the ICARUS Verilog Compilation System. While kernel modules of the ICARUS Verilog, as front modules, read and parse Verilog source codes (.v) of the circuit, and generate an internal netlist, then perform elaboration and optimization, and generate a final netlist for various end modules to generate final output codes. Thus, the VRM module extracts data from the final netlist and generates VRM model of the circuit. 2.4 VRM Model Output File The VRM output is a text format file (.vrm). The file consists of three kinds of blocks corresponding to three levels of the model as follows. (i) CKT block: include k-node statements of CKT. # CKT; <knode_id>(<attribute_list>); <knode_id>(<attribute_list>) = <fanin_list>; (ii) CFG block: include c-node statements of CFG of the k-node P or F. # <knode_id>; <cnode_id>(<attribute_list>) = <fanin>: <fanout_list>; <cnode_id> = <fanin_list> : <fanout>: <branch_fanout_cnode>; (iii) DFG block: include d-node statements of DFG of the c-node (except for TM) # <cnode_id>; <dnode_id>(<attribute_list>); <dnode_id>(<attribute_list>) = <fanin_list>; 2.5 Features of VRM VRM is a hierarchical behavioral model instead of flatting one. The top level CKT reserves the modularization structure of design described in HDL. It represents an interconnect network of multiple parallel processes. Each process is further modeled as a CFG and its DFGs to describe the control flow and data flow respectively. Thus VRM is simple and easy to be converted and extended from the HDL descriptions based on general HDL compilation systems. VRM can also be extended to support the assign for describing combinational logic. Note that during HDL compilation, the assign should be compiled to behavioral structure, instead of gate level structure like compilation systems usually do. In the second level CFG, for control c-nodes IF/CS/CX/CZ, we add one more exit that directly points to the corresponding terminal node. This is useful for forward and backward tracing on the CFG. For example, one can directly find the branch fanout reconvergence point from the corresponding branch fanout point, and vice versa. Finally, VRM is with clock accuracy and can be applied to most of test tools.

4 178 J. Comput. Sci. & Technol., Mar. 2005, Vol.20, No.2 its terminal c-node TM directly. Fig.3. CFG-0 of P-8. Fig.1. Verilog HDL circuit. Fig.4. DFG-3 of CS An Example The Verilog source of a simple circuit is shown in Fig.1. According to its VRM output file, the part of model graphs is given in Figs.2 4. The control expression of CASE statement is shown in Fig.4. Here, CBI Fig.2. CKT. (case branch index) is a virtual d-node. It translates the case match result to a branch index to be used in CFG of the k-node P. Note that for IF and CASE statements, VRM gives one more null-operation branch pointing to 3 RTL Fault Models Evaluation of test quality should conform to the physical implementation of a circuit, that is defects instead of faults. This is true for both gate level and high-level testing. The stuck-at-0/1 fault models at gate level have been widely used and accepted. When use software testing like approaches, it may focus on the code coverage. The high-level fault models can be defined as statement, branch, and path faults. On the other hand, from the hardware point of view, one can define variable bit stuck-at fault, condition (control) stuck-at fault [3,6],and general function fault [3] as RTL fault models. However, it is difficult to find the correlation between high-level fault models and gate level fault models. Since an HDL described circuit can be synthesized to different gate level implementations depending on what kind of synthesis tool and synthesis library to be used [17]. So the question is whether we can define RTL fault models such that the RTL fault coverage figure of a circuit can be statistically mapped to the gate level one. It seems possible, for example, recently Thaker proposed a stratified sampling technique used in RTL fault simu-

5 Li Shen: Concurrent Fault Simulation at Register Transfer Level 179 lation to estimate the gate level fault coverage of given test patterns [18]. For the VRM circuit model, we can define fault models in natural way, which are richer comparing to the above fault models. These are stuck-at bit faults of d- node and k-node, except for process node P and function node F that are associated with its CFG. Furthermore, c-nodes in CFG do not need fault models at all, since each c-node (except for terminal node TM) is associated with a DFG, in which its d-node faults might be enough to represent assignment or condition faults including the left-value variable faults and internal node faults of the expression. So it is possible to obtain a good mapping between two level fault models. In this paper, we mainly focus on the RTL fault simulation, but not the mapping between RTL and gate level fault models. Therefore, for simplicity, we only define restricted RTL single fault models as follows. 3.1 k-node Fault Models k-nodes mainly represent variables. Considering the fault equivalence, we only define node output bit stuckat-0/1 faults for PI, PIO/IIO-input-port, VR, and VM (memory cell). VF (input parameter and internal variable of F) faults can be implied by d-nodes of F. k-node E is used for triggering process P. In general, the E fault is easy to be reflected in the process. So faults of E and its predecessor are not defined. 3.2 d-node Fault Models Except for constant CI, output node VO and virtual node CBI, we only define d-node output bit stuck-at- 0/1 faults. For the general function faults, such as add operation itself, are not considered yet. Furthermore, like gate-level fault model, several fault collapsing rules are defined for reducing the fault set. For example, a DFG of left-shift 3 bits is shown in Fig.5, we may use the following rules: part [7 : 3] after shifting are defined. Part [2 : 0] must be 000, which may define s-a-1 faults only or do not care. In that case, we define total faults for the part of VI, [4 : 0] only in Fig.5, since VI has only one fanout. Furthermore, in HDL descriptions, a function module can be called multiple times by process module. However, the function can be synthesized to one hardware copy if it is called in different statement branches, or multiple copies if appeared in the same branch. Therefore, when we define faults for the function module (DFGs), one copy of fault models for the former and multiple copies are needed for the latter. In the benchmarks [14,15], only b05 of POLITO is in the latter case. For simplicity, we only define one copy of fault models for the function, though a single fault will become a multiple one in this case. 4 RTL Logic Simulation 4.1 Table Driven Simulator There are two kinds of gate level logic simulators, compiler driven and table driven [11]. For compiler driven simulators, it produces a sequence of machine executable instructions, and for table driven simulators, it produces a series of tables describing the circuit to be simulated. The same thing is for the RTL logic simulation. For example, in the ICARUS Verilog, VVM and VVP modules belong to the compiler driven simulator. In this paper, based on the VRM model, a table driven logic simulator is proposed. 4.2 Logic Simulation Like gate level simulation, the table-driven eventdirected simulation is adopted. For simplicity, here we only consider single clock, synchronous sequential circuits. Furthermore, as mentioned above, VRM does not deal with the delay, so it can use the 0-delay simulation model. The simulator has to construct three sets of tables (data structure) for circuits described by the 3-level VRM model. Since the data structure is more complex, it needs to detail the circuit levelizing and event scheduling as follows Circuit Levelizing Fig.5. Fault collapsing. d-node VI (input value): if it has only one fanout to d-node BLS, fault models are defined only for the partial bits corresponding to the remaining part [4 : 0] after shifting. Otherwise, faults may be defined for all bits. d-node BLS (left-shift): if its data input node has only one fanout, BLS output fault models will not be defined. Otherwise, only the output faults of remaining For the DFG model, like gate level combination circuits, the levelization of d-nodes is trivial. The CFG model represents the execution sequence of program. Therefore no levelization is needed. The CKT model may include multiple processes (always statements) executed in parallel. In fact, during simulation, the computer executes processes in serial. In order to save CPU time, the ordering of processes execution is needed. In that case, the process k-node P may be further classified. They are P triggered by the positive/negative edge of clock only, PA by the any edge

6 180 J. Comput. Sci. & Technol., Mar. 2005, Vol.20, No.2 of a signal, and PH by both. Then the k-node E can also be extended to E, EA, EH, and VR to VR, VRA, VRH respectively. Note that in fact, PA represents a combinational circuit. So, only clocked VR and VRH represent the real status variables of circuit. For processes P triggered by clocks, it does not care of their execution order. However, for processes PA and PH, their execution order is important. If the correct order is made, all processes PA and PH can be executed by one pass only to save CPU time, otherwise the iteration may not be avoided. For the CKT model, all k-nodes need to be levelized. The levelizing algorithm is similar with the one in the gate level [11]. But two things have to be mentioned. First, let us see the worst case in Fig.6, assume that variables VRA-1 and VRA-2 are in the same level n, and PA may access WIRE. In order to execute PA correctly, the level of PA must be greater than the level of WIRE. So it is required that the level increase of EA be 3, instead of 1 for other k-nodes. Fig.6. Levelizing. Second, we had the assumption of synchronous sequential, that means no asynchronous sequential in the combinational part. However, looking at connections between fanins and fanouts of k-nodes PA, there may exist some loops. In fact, they are not real loops from signal point of view. For example, in Fig.7, this is a part of CKT model for the CMU-DSP benchmark, data alu.v. VRA-183, VRA-205 and VRA-185, VRA-207 are leftvalue variables of assignment expressions in PA-214 and PA-218 respectively. There are k-node connection loops, but not signal loops. In fact, the value of VRA-183 and VRA-205 depends on VRA-185 and VRA-207 respectively, and not vice versa. So, during levelizing, we can cut connections 3 and 4 at fanins of EA-595 to remove the loops. Then the deadlock will not happen. For the CKT model levelizing, the levelization algorithm is started from level 0 k-nodes, PI, PIO, IIO, VR and VM. It defines that all PO is set as level max-1 and all P (not PH) triggered by clock only is set as level max. During levelizing, when meet loops, cut them, then it is continued until all k-nodes are levelized Event Scheduling For event directed simulation, event scheduling is the key procedure. In the DFG model, an event is a change in value of a d-node. The event scheduling is very simple. However, it is more complex in the CKT model. First, we define various events as follows. Input value/edge event. It is initiated from PI and PIO-input-port. Status value/edge event. It is initiated from VR, VM and VH. Clock edge event. Here the positive edge is assumed. Internal value/edge event. It is generated from other k-nodes. The typical simulation timing is that each clock cycle has two simulation phases, input and clock. The display time can be located between the input and clock time. In the input phase, the simulation starts from input events and propagates events to other k-nodes except for PO, PIO/IIO-output-port and P. Then calculate all k-nodes PO and PIO/IIO-output-port. If there are k-nodes PIO and IIO, the above procedure may be iterated, but no oscillation will happen due to the assumption of synchronous sequential. For the clock phase, first, all k-nodes P and PH are executed due to the clock event. Then, the simulation starts from status events and propagates events to other k-nodes except for PO, PIO/IIO-output-port and P. Fig.7. Loop cutting. Fig.8. Bi-direction k-nodes. In the CKT model, the bi-direction k-node PIO/IIO can be illustrated in Fig.8. These k-nodes have two values defined as, input-port-value at the fanout of node and out-port-value at the first fanin of node. The outport-value comes from the bus (other k-nodes). For

7 Li Shen: Concurrent Fault Simulation at Register Transfer Level 181 PIO, the input-port-value is the primary input of circuit. For IIO, the input-port-value can be the bus value or primary input value from PIO, depending on the bus impedance. The above PIO/IIO calculation means that pass the bus value to PIO/IIO-output-port, then pass it to input-port and try to initiate the new input event of PIO/IIO for re-simulating Node Calculation Each k/d-node value consists of two 64-bit computer words, v 0 and v 1, which represent the signal values with its possible width from 1 to 64. A four-valued logic (0, 1,X, and Z) is adopted. Two bits in (v 0,v 1 ) respectively are used to code four values of each bit, 0 is coded as (1, 0), 1 as (0, 1), X as (0, 0), and Z as (1, 1). For signal edges, we use four-valued edge encode (0, 1,X,and Z), 0/1 for negative/positive edge respectively, Z for any edge, and X for no edge. The node value evaluations in four-value logic should comply with the rules given in the IEEE-1364 standard [16]. Each assignment variable in processes or functions has two values, old value before assigning and new value after assigning. During evaluating an expression, if the variable is a blocking assignment variable and was assigned previously, then it takes its new value, otherwise old value is used. 5 RTL Concurrent Fault Simulation 5.1 Super Fault List The concurrent fault simulation is a one-pass process [11]. It can simulate all active faults simultaneously for each test input. The key problem is how to deal with the super fault list at RTL. First, we introduce the fault list that consists of a linked list of all remaining undetected faults. Each fault is associated with a linked list of faulty status. Since the k-node EA, EH needs to evaluate any edge of a nonclock signal, each faulty state should be saved as two values, old and new. The fault index is defined in Fig.9. Note that for k-node faults, the field mem address is used for memory node VM. d-node fault: 0 dfg index d-node indexd pin number s-a-0/1 k-node fault: 1 k-node index mem address pin number s-a-0/1 Fig.9. Fault index. The super fault list (SFL) consists of a linked list of super faults associated with a k-node or d-node. Each entry in SFL includes fault index, node faulty input values (or edges), and node faulty output value (or edge). All entries in SFL are ordered by the fault index for serially scanning. 5.2 Fault Simulation After the good simulation, then we can select all excited faults for concurrent fault simulating. Here, the fault injection means to convert the selected fault into a super fault, add it to the SFL of its corresponding node, and initiate a list event. In general, the fault grouping is not needed, since the virtual memory of current computers is enough for managing all SFLs. Note that during good simulation for process, a particular path is executed. These DFGs in the path are called as active. Therefore, when selecting a d-node fault, only those d- nodes in active DFGs need to be checked. During good simulation, the simulation event can be input value/edge, status value/edge, clock edge and internal signal value/edge. For the concurrent fault simulation, due to SFLs, the event will be the logic list event [11], and the node evaluation is SFL related, which includes SFL setting, computing and event initiating. If an SFL event is propagated to primary output node PO/PIO, then the corresponding fault is detected. 5.3 Process Execution in Fault Simulation Usually, gate level circuits use the flatting model. We have been familiar with the table driven fault simulator. However, with the VRM model, there exists the control (program) flow in process and function node clearly. The fault simulation will be a little different. So we need to detail the process execution during fault simulation. For CKT and DFG models, like the gate level, the fault simulation or event propagation is simple. Let us discuss the CFG level. Fig.10 gives a CFG of process (function), where c-node A is the assignment statement, B is control statement, and T is terminal. Assume that for a particular fault, the good path is c-nodes 1, 2, 3, 4, 12, 13, and the faulty path is 1, 2, 5, 6, 7, 8, 10, 11, 12, 13. We define, gf branch: all possible good and faulty branches between B and its T; f branch: all possible faulty branches between B and its T; g path: all possible good paths started from the succeeding node of B; f path: all possible faulty paths started from the succeeding node of B. In Fig.11, for the above fault, there is a gf branch of c-nodes 2,...,12 between 2 and 12, which includes agpath from 3 and f path from 5, and an f branch of c-nodes 6,...,10 between 6 and 10, which includes an f path from 7 only. The process or function fault simulation is to execute the CFG with all selected faults simultaneously. The following procedure is started for any given g path or f path.

8 182 J. Comput. Sci. & Technol., Mar. 2005, Vol.20, No.2 Step 1. During execution, each control node B should be checked if the gf branch or f branch exists due to a fault. Step 2. Along the g path of that B in Step 1, simulate all possible faults simultaneously, which do not cause any faulty branch. It means that the g path is not changed due to the faults. Step 3. In the g path, when first meeting a control node B, which has faulty branches due to some faults (called as branch fault), it is needed to simulate all corresponding f paths to only propagate these branch faults one by one. In fact, Step 3 must be a serial fault simulation in order to avoid the appearance of multiple faults. In that case, an LIFO stack is needed to manage all possible branch super faults to be simulated correctly. Fig.10. CFG of a process. Procedure 1: Process Execution with Faults 5.4 Fault Simulation Algorithm of VFSim As mentioned in Section 4, the simulation includes two phases for each clock cycle. Now the kernel algorithm of fault simulator, VFSsim, is given as follows. Table 1. Node Counts of Benchmark Circuits polito KN CFG CN DFG DN PI PO PIO IIO WIRE WOR VR VM P VF F RAM BI1 NEX NEXL E b b b b b b b b b b b b b b , b , b ,484 1,265 4, b ,886 3,301 12, b , b , b ,304 1,099 4, cmudsp KN CFG CN DFG DN PI PO PIO IIO WIRE WOR VR VM P VF F RAM BI1 NEX NEXL E rf M rf N rf R bus switch , pcu , agu ,675 2,179 6, data alu ,081 4,673 34, dsp core 1, ,705 7,589 42, Note: For the cmudsp benchmarks, the circuit dsp core consists of the other seven circuit modules.

9 Li Shen: Concurrent Fault Simulation at Register Transfer Level 183 Algorithm 1: Concurrent Fault Simulation (1) Input phase 1. Read next input, and update circuit status values of VR, VRH, and VM. 2. Good simulation for CKT, in which processes to be executed are PA and PH only. 3. If there are k-nodes PIO/IIO, do the following iteration until no any simulation event. Pass PIO/IIO-output-port value to its input-port. Good simulation for CKT, and executing PA and PH only. 4. Fault selection and injection to generate initial SFLs. 5. Fault simulations corresponding to Steps (1)-2 and (1) Check PO and PIO-output-port to drop detected faults. 7. If there are k-nodes VRH, save their faulty status values for each undetected fault. 8. Delete all SFLs. 9. Delete detected faults from the fault list. (2) Clock phase 1. Good simulation for processes P. 2. Fault selection and injection to generate initial SFLs. 3. Fault simulation corresponding to Step (2) Save circuit faulty status values for each fault. 5. Delete all SFLs. If the VRM has no process PA and PH, then the fault simulation algorithm can be reduced as follows. Algorithm 2: Reduced Concurrent Fault Simulation 1. Read next input, and update circuit status values of VR and VM. 2. Good simulation for CKT. 3. If there are k-nodes PIO/IIO, do the following iteration until no any simulation event. Pass PIO/IIO-output-port value to its input-port. Good simulation for CKT. 4. Good simulation for processes P. 5. Fault selection and injection to generate initial SFLs. 6. Fault simulations corresponding to Steps 2, 3, and Check PO and PIO-output-port to drop detected faults. 8. Delete all SFLs. 9. Delete detected faults from the fault list. 6 Experimental Results The concurrent fault simulator, VFSim, is implemented in C++ on Red Hat Linux. We use a personal computer, which includes an AMD Athlon X1600+ CPU and 256MB memory. Two sets of benchmark circuits, POLITO-ITC 99 [14] (rewritten in Verilog) and CMUDSP [15] are used for experiments. The VRM models of circuits are generated by use of the VRM tool. To compare our RTL fault simulation result with the gate-level result, we use the gate-level HOPE simulator, which accepts ISCAS89 netlist format circuit files (.bench) [13]. Therefore, first, Verilog RTL files (.v) have to be synthesized to Verilog gate-level netlist files by use of a restricted synthesis library, then converted to.bench files. Experiment 1: VRM models The left part of Table 1 gives total numbers of k- nodes, CFGs, c-nodes, DFGs and d-nodes in VRMs. The right part of Table 1 gives various k-node counts. In Table 2, numbers of variable, process and function k-nodes are given. For function k-nodes F, it also gives the number of function copies, i.e., total number of calls for a function. Table 2. VR, P, F Node Counts VR P F C/A/H C/A/H F/F-cp b01 3/0/0 1/0/0 0/0 b02 2/0/0 1/0/0 0/0 b03 15/0/0 1/0/0 0/0 b04 14/0/0 1/0/0 0/0 b05 8/14/0 1/2/0 1/5 b06 5/0/0 1/0/0 0/0 b07 7/0/0 1/0/0 1/2 b08 9/0/0 1/0/0 1/1 b09 5/0/0 1/0/0 0/0 b10 11/0/0 1/0/0 0/0 b11 5/0/0 1/0/0 0/0 b12 19/0/0 4/0/0 0/0 b13 24/0/0 5/0/0 0/0 b14 25/0/0 1/0/0 0/0 b15 33/0/0 3/0/0 0/0 b17 105/14/0 11/4/0 0/0 b18 260/47/0 24/9/0 0/0 b20 50/5/0 2/1/0 0/0 b21 50/5/0 2/1/0 0/0 b22 75/6/0 3/1/0 0/0 rf M 0/3/0 1/1/0 0/0 rf N 0/3/0 1/1/0 0/0 rf R 0/3/0 1/1/0 0/0 bus 2/20/0 2/5/0 0/0 pcu 24/57/1 12/10/1 0/0 agu 23/107/0 14/16/0 2/222 alu 14/139/4 6/6/0 10/2,734 dsp 63/323/5 34/37/1 12/2,956 C: VR & P, A: VRA & PA, H: VRH & PH F-cp: function copies Experiment 2: Fault models Columns 2 4 of Table 3 give numbers of single faults defined by Section 3, i.e., total k-node faults and total d-node faults respectively, where d-node faults are collapsed and with one function copy only. The others are un-collapsed d-node faults of VMR and collapsed gatelevel faults in HOPE [13]. Experiment 3: Fault selection Giving an ATPG test sequence, we record the number of DFGs executed (activated) in good and fault simulation respectively for each test. Therefore, in Table 4,

10 184 J. Comput. Sci. & Technol., Mar. 2005, Vol.20, No.2 the second column gives the total number of DFGs of VRM. The next two columns are maximum numbers of DFGs executed in good and fault simulation respectively for a test. We see that during good simulation, only small part of DFGs is activated for each test. It means that the number of selected faults for each test can only be a small rate of total faults. The last column shows the maximum faults selected for a test. So the total size of node SFLs will not be too large. This will be a good feature for implementing an efficient VLSI concurrent fault simulation at RTL. Table 3. Fault Counts Total = KN+ DN DN HOPE b b b b ,524 b05 1, ,518 1,842 2,164 b b ,168 b b b b ,472 1,320 b12 1, ,338 1,610 3,254 b b14 26,256 1,052 25,204 29,690 13,478 b15 12,617 1,110 11,507 15,746 25,678 b17 39,661 3,712 35,949 48,666 72,394 b18 135,174 10, , ,452 b20 53,488 2,210 51,278 60,254 35,508 b21 53,488 2,210 51,278 60,254 34,976 b22 80,174 3,260 76,914 90,376 53,394 rf M rf N rf R bus , pcu ,258 6, agu 59,562 2,818 56,744 64,922 alu 728,912 2, , ,688 dsp 805,222 8, ,614 1,006,644 DN: collapsed faults DN : un-collapsed faults HOPE: gate level faults Experiment 4: Fault coverage We use two types of test sequences for simulation. The first type is ATPG tests obtained by some ATPGs, where the test sets in [19] are used for POLITO circuits b01 b15, and one test set in [14] for b20, and for b21 and b22 as well. The second type is random tests with the same length for the first type. Note that the reset signal is not a random, it is 1 for the first and third test only. Table 5 gives fault coverage data obtained from both RTL VFSim and gate level HOPE simulator. We see that the RTL fault simulation result reflects the gate-level result in a sense. Table 4. Fault Selection DFGs Faults G sim F sim Total Max act Max act Max Sel b b b b b b b b b b b b b b ,609 b ,528 b ,759 b ,774 b22 1, ,179 Table 5. Fault Coverage Test F.C.(random) F.C.(ATPG test) length VFSim HOPE VFSim HOPE b b b b b b b b b b b b12 1, b13 1, b14 1, b15 1, b17 10, b20 11, b21 11, b22 11, rf M rf N rf R bus 1, pcu 1, agu 10, Experiment 5: CPU time In Table 6, the second column shows CPU time data

11 Li Shen: Concurrent Fault Simulation at Register Transfer Level 185 Table 6. CPU Time (s) HOPE VFsim Total* Total G sim F sim F sel FS sav SF del F del b b b b b b b b b b b b b b b b20 1, , b21 1, , b22 1, , Total : for SFL size =1 G sim: good simulation F sel: fault selection SF del: SFLs delete Total: for SFL size = max F sim: fault simulation FS sav: faulty status save F del: detected faults delete obtained from the gate level HOPE simulator. The third column actually represents the serial fault simulation of VFSim, which is only one fault selected for simulation each time. The fourth column is for the concurrent fault simulation of VFSim. Obviously, the concurrent fault simulation is much faster than the serial simulation. We also see that comparing to the gate-level simulation, the RTL simulation will potentially take less CPU time. Furthermore, the rest columns show the CPU time distribution for the concurrent fault simulation. The pure good/fault simulation times are reasonable. However, for large circuits, the fault selection time may have a big rate. 7 Conclusions One big challenge for high-level testing is how to construct a suitable circuit model and acceptable fault models. In this paper, we propose an RTL circuit model, VRM, for Verilog described circuits and a VRM based concurrent fault simulation approach. The RTL concurrent fault simulator, VFSim, was implemented for the first time. Though the RTL fault models in the paper have not been perfect yet, the initial experimental result is encouraging. The VRM is easy to be established and extended, suitable for performing various algorithms, and more practical for developing test tools such as fault simulation, test generation, testability measure and so on. The RTL concurrent fault simulation approach is feasible. Since the active part of a Verilog program for each test input is a small rate, the number of selected faults for injection to simulate and the size of total super fault lists will not be too large. So one can implement efficient fault simulators for VLSI, which even needs less overhead comparing to the gate-level one. For the VFSim, the RTL fault simulation result (fault coverage) reflects the gate-level result in a sense. Our future work includes the VRM extension, and acceptable RTL fault models which can map gate-level ones in statistical sense. In addition, based on the VRM, we are also working on test generation and testability measure. Acknowledgment The author wish to thank Mr. Feng Gao and Tao Xiong of the Microaurora Company for synthesizing Verilog RTL benchmark circuits, and Dr. Zhi-Gang Yin of Institute of Computing Technology, Chinese Academy of Sciences, for providing the ATPG test sets of benchmark circuits. References [1] Fallah F, Ashar P, Devadas S. Simulation vector generation from HDL descriptions for observability-enhanced statement coverage. In Proc. Design Automation Conf., June 1999, pp [2] F Corno, M Sonza Reorda, G Squillero. RT-level ITC 99 benchmarks and first ATPR results. IEEE Design & Test of Computer, July-August 2000, pp [3] Levendel Y H, Menon P R. Test generation for computer hardware description language. IEEE Trans. Computers, July

12 186 J. Comput. Sci. & Technol., Mar. 2005, Vol.20, No , C-31(7): [4] Murray B T, Hayes J P. Hierarchical test generation using precomputed tests for modules. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, June 1990, 9(6): [5] Roy K, Abraham J A. High-level test generation using data flow descriptions. In Proc. Eur. Conf. Design Automation, Mar. 1990, pp [6] Ferrandi F, Fummi F, Sciuto D. Implicit test generation for behavioral VHDL model. In Proc. Int. Test Conference, Oct. 1998, pp [7] Bhatia S, Jha N K. Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits. IEEE Trans. VLSI Systems, Dec. 1998, 6(4): [8] Ghosh I, Fujita M. Automatic test generation for functional register-transfer level circuits using assignment decision diagrams. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, March 2001, 20(3): [9] Williams S. The ICARUS Verilog compilation system. [10] F Corno, G Cumani, M Sonza Reorda, G Squillero. RTlevel fault simulation techniques based on simulation command scripts. In XV Conf. Design of Circuits and Integrated Systems, Le Corum, Montpellier, Nov , 2000, pp [11] Breuer M A, Friedman A D. Diagnosis & Reliable Design of Digital Systems. Computer Science Press, USA, [12] Niermann M, Cheng W T, Patel J H. PROOFS: A fast, memory-efficient sequential circuit fault simulator. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Feb. 1992, 11(2): [13] Lee H K, Ha D S. HOPE: An efficient parallel fault simulator for synchronous sequential circuits. IEEE Trans. Computer- Aided Design of Integrated Circuits and Systems, Feb. 1996, 15(9): [14] Reorda M S, Corno F, Squillero G. ITC 99 benchmarks. [15] CMU Lower Power Group. CMU-DSP Benchmarks. lowpower/benchmarks.html [16] Bhasker J. A Verilog HDL Primer (Second Edition). Star Galaxy Publishing, USA, [17] Yinghua Min. Why RTL ATPG. Journal of Computer Science and Technology, 2002, 17(2): [18] Thaker P A, Agrawal V D, Zaghloul M E. A test evaluation technique for vlsi circuits using register-transfer level fault modeling. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Aug. 2003, 22(8): [19] Yin Z, Min Y, Li X. An approach to RTL fault extraction and test generation. In Proc. 10th Asian Test Symposium, 2001, pp Li Shen was born in He graduated from the Department of Electrical Engineering, Zhejiang University, China, in Since then, he joined the staff of Institute of Computing Technology, Chinese Academy of Sciences, Beijing, where he is currently a professor. He is now an IEEE senior member. He has been engaged in research and design of digital circuits and computers for many years. From Oct to Sept. 1984, he was a visiting scholar at Thomas J. Watson School of Engineering, Applied Science and Technology, State University of New York at Binghamton. From Oct to Nov. 1991, he worked at Integrix Inc., Newbury Park, California, for several cooperative projects on workstation development and ASIC design. His research interests include soft computing, ASIC design, design for testability and fault testing.