1 ( pipeline 89 + single cycle 20 + multicycle 44 = 153 points) 100 min.

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1 ee57_mt_sp23.fm Spring 23 EE57 Instructor: Gandhi Puvvada Midterm Exam (2%) Date: /5/23, Friday Time: 9:5M - :5M in THH2 Name: Total points: 2 Perfect score: 22 / 2 ( pipeline 89 + single cycle 2 + multicycle = 53 points) min. Pipelining (Modified Lab 7 part 3 (further modified from Spring 2 Midterm)): In the Spring 2 midterm exam, we had two DD units in the EX2 stage and also a branch if zero instruction executing from the ID stage. There was no FU_BR or forwarding muxes in ID stage and we solved W dependency problems of the instruction by simply stalling the in ID stage. Given on the next page is the block diagram of the Spring 2 question for your reference. 5 Your friend says that an addition of FU_BR and a forwarding mux in ID stage could have avoided some of the stalls incurred by the in the Spring 2 design. True / False Explain: Here, we added a MEM stage after the EX2 stage and added four new instructions, one load word instruction and three store word instructions as shown below. The in instruction as well as the in the load word and store word instructions are the lower -bit field of the 32-bit instruction. It is obvious that the memory instructions use direct addressing mode. It is also obvious that the MEM stage shall be after the EX2 stage as SWP (store word plus ) and SWP8 (store word plus 8) need the addition operation in the EX2 stage. Which of the instructions never provide help? (circle all right answers) None SW $X, SWP $X, SWP8 $X, Which of the instructions never receive help? (circle all right answers) None SW $X, SWP $X, SWP8 $X, Instruction Operation Which of the following junior instructions is/are dependent on LW $2 78? (circle it/them) NOP; $R, $X; ($R) <= ($X) $X, ; (PC) <= if ($X) = DD $R, $X; ($R) <= ($X) + DD8 $R, $X; ($R) <= ($X) + 8 LW $R, ; ($R) <= M[] SW $X, ; M[] <= ($X) None, $, $2; $2, $; $2, 23; DD $, $2; DD8 $, $2; LW $2 888; SW $2 888; SWP $2 888; SWP8 $2 888; Which of the following junior instructions is/are dependent on SW $2 78? (circle it/them) None, $, $2; $2, $; $2, 23; DD $, $2; DD8 $, $2; LW $2 888; SW $2 888; SWP $2 888; SWP8 $2 888; SWP $X, ; M[] <= ($X) + SWP8 $X, ; M[] <= ($X) + 8 pril, 23 :3 am EE57 Midterm Exam - Spring 23 Page - / ny dependency requiring stalling or forwarding in each of the two pairs of instructions? In Pair# Yes / No. In Pair#2 Yes / No. Pair#: Senior: LW $2 78; Pair#2: Senior: SW $ 238; Junior: SW $3 78; Junior: LW $7 238; C Copyright 23 Gandhi Puvvada

2 pril, 23 :3 am EE57 Midterm Exam - Spring 23 Page - 2 / Spring 2 Q#2 Block Diagram -- Just for reference PCSource PC + IF I-MEM IF_Flush X DD8 DD ID Comp Station in ID Stage ID_XMEX2 HDU_BR Branch Reg. File X ID_ ID_ ID_DD ID_DD8 R-Write STLL_BR _ZERO XMEX2 DD8 DD EX2_XMEX2 X_Mux FORW FU DD + R_Mux SKIP EX2 DD + EX2_ EX2_DD EX2_DD8 EX2_ R2_Mux SKIP2 EX2_Write Write WB WB_ WB_Write WB_ ee57_mt_sp23.fm C Copyright 23 Gandhi Puvvada Comp Station in ID Stage ID_X Matched with EX2_ ID_XMEX2 P=Q P Q ID_X EX2_. Complete all missing connections to D Q CLR 2. Complete the STLL_DD8 logic in EX2 and STLL_BR logic in ID stage. 3. Complete all four enable () controls on the pipeline registers (including PC).. Draw the logic to produce PCSource, IF_Flush, FORW, SKIP, SKIP2 on this page itsef. Modified LB 7 Part 3 Block Diagram STLL_DD8 Q#2

3 ee57_mt_sp23.fm 2 WB EX2 FU_M FU_2 XMEX2 XMEX2 HDU FORW_M DD DD FORW_2B FORW_2 XMMEM XMMEM _ZERO STLL_ID MemtoReg MEM_MemtoReg MemWrite MemRead MR MW MD R2_Mux PC X IF + Write WB_ R_Mux X_Mux WB_Write SKIP2 SKIP FORW_2 WB_ PCSource Modified LB 7 Part 3 Block Diagram ID I-MEM Q# + D Q CLR Branch WB_ WB_ Din Dout IFRF Reg. File IF_Flush + STLL_2 Comp Station in ID Stage ID_XMEX2= ID_X Matched with EX2_ F_Mux ID_XMEX2 ID_XMMEM P=Q P=Q P Q P Q ID_X EX2_ ID_X MEM_ FB_Mux X WB_Write R-Write ID_ FB_Sel F_Sel FU_BR Control signals Other than Control signals Other than ID_ XB_Mux Memory FORW_2B Memory MEM_RegWrite Control signals Other than ID_Bubble Notes:. Complete the 3 items marked as here on this page. These are 5 (enables) for the 5 registers, 5 forwarding paths for the 5 forwarding muxes, PCSource, IF_Flush, and ID_Bubble..Produce the 8 items marked as on the next few pages. Complete this pril, 23 :3 am EE57 Midterm Exam - Spring 23 Page - 3 / C Copyright 23 Gandhi Puvvada

4 ee57_mt_sp23.fm Given on the previous page is an incomplete design of the 5-stage pipeline. Browse through the same and also browse through the associated parts of the question below before starting answering. Use signal names with stage name as prefix in your design. For example the signal ID_XMMEM (meaning ID_X matched with the MEM_), when carried to the EX2 stage (through the ID/EX2 stage register) bears the name EX2_XMMEM. The one-hot coded opcode provides the following control signals:,, DD, DD8, LW, SW, SWP, SWP8. When SW goes into EX2, it is called EX2_SW. 8. Consider the sequence of dependent instructions on the side. LW itself LW $2 888; // in WB stage is not dependent on its seniors. Is it possible to execute this sequence $3, $2; // in MEM stage without stalls? Yes / No. If "No" how many stall are incurred $, $3; // in EX2 stage $ 23; // in ID stage and where and when? If "Yes" how the is receiving help when his seniors themselves need to receive help? Why the VLSI engineer is concerned about a series of mux delays cascaded in our design and calls it a "snake path"? ID EX2 MEM WB LW.2 Complete 3 items of the design on page 5. Complete items of the design below..2. HDU in ID stage contains stall logic to handle W dependencies of all instructions including which can not be solved through forwarding. HDU STLL_ID.2.2 FU_BR in ID stage to produce the two select signals for the two forwarding muxes in the ID stage. These muxes are properly ordered to implement priority in forwarding. FU_BR F_Sel FB_Sel.2.3 EX2_STLL_Logic EX2_STLL_Logic D Q CLR STLL_2 pril, 23 :3 am EE57 Midterm Exam - Spring 23 Page - / C Copyright 23 Gandhi Puvvada

ee57_mt_sp23.fm 8.2. EX2_other_Logic: The two forwarding muxes are properly ordered to implement priority in forwarding. EX2_other_Logic FORW_2 FORW_2B SKIP SKIP2.2.5 MEM stage Forwarding unit FU_M: Circle the instructions which can wait as late as MEM stage to receive forwarding help:,, DD, DD8, LW, SW, SWP, SWP8 FU_M FORW_M.

5 ee57_mt_sp23.fm 8.2. EX2_other_Logic: The two forwarding muxes are properly ordered to implement priority in forwarding. EX2_other_Logic FORW_2 FORW_2B SKIP SKIP2.2.5 MEM stage Forwarding unit FU_M: Circle the instructions which can wait as late as MEM stage to receive forwarding help:,, DD, DD8, LW, SW, SWP, SWP8 FU_M FORW_M.2. MEM_other_Logic: MEM_other_Logic MemRead MemWrite MEM_MemtoReg MEM_RegWrite 2.3 Complete the following "Single Cycle CPU" kind of a design for the 5-stage pipeline. Complete the control unit on the next page. PCSource PC_ PC? + I-MEM Branch X DD DD8 LW SW SWP SWP8 CU Show the design of this Control unit separately Reg. File X R-Write RegWrite _ZERO BranchCond DD + R_Mux SKIP DD + R2_Mux SKIP2 Din MD Dout MR MW MemRead MemWrite MemtoReg Single Cycle CPU pril, 23 :3 am EE57 Midterm Exam - Spring 23 Page - 5 / C Copyright 23 Gandhi Puvvada

ee57_mt_sp23.fm.3. Design the control unit for the single cycle CPU here. 8 BranchCond SKIP SKIP2 MemRed MemWrit MemtoReg RegWrite. Now let us try to build a multi-cycle version for the design.

This multi-cycle datapath is similar to the st edition design except that here the LU is built using dynamic logic (like in the 2nd edition). There is an LUOut register like in the 2nd edition.

6 ee57_mt_sp23.fm.3. Design the control unit for the single cycle CPU here. 8 BranchCond SKIP SKIP2 MemRed MemWrit MemtoReg RegWrite. Now let us try to build a multi-cycle version for the design. It is proposed that, we go for a single LU, which can add a selected constant, ( for PC and for DD or DD8). DD8 uses the LU twice to add two times. This multi-cycle datapath is similar to the st edition design except that here the LU is built using dynamic logic (like in the 2nd edition). There is an LUOut register like in the 2nd edition. You need to carefully decide when to take (tap) data from the upstream of the LUOut register and when to take (tap) data from the downstream of the LUOut register. We have an IR register (Instruction Register) to hold the instruction at the end of the first state(s). IR is needed as PC is incremented using the LU in the very first state. The memory has an output register MDR. We need to support a NOP instruction here besides,, DD, DD8, LW, SW, SWP, and SWP8... Complete the datapath and the state diagram for control unit on the next two pages. To some extent, our state diagram resembles the 2nd edition state diagram reproduced below for your reference. We are doing a MOORE kind of state diagram and may be wasting a few clocks. Just for reference pril, 23 :3 am EE57 Midterm Exam - Spring 23 Page - / C Copyright 23 Gandhi Puvvada

ee57_mt_sp23.fm 8 The LUOut register (requires / doesn t require) a write control.

File +B X B R-Write RegWrite IRWrite PCWriteCond PCWrite PCSource PC_ I-MEM -bit LU PCSource PCWrite

X_Mux MD Din Dout R_Mux LUOut MDR Source[] C_Mux Source[] ONE/FOUR Multi Cycle CPU Data Path IRWrite SKIP CU

7 ee57_mt_sp23.fm 8 The LUOut register (requires / doesn t require) a write control. The MDR register (requires / doesn t require) a write control. Reason for this is PC X Reg. File +B X B R-Write RegWrite IRWrite PCWriteCond PCWrite PCSource PC_ I-MEM -bit LU PCSource PCWrite PCWriteCond Incremented PC In_Mux Branch _ZERO M_Mux CU ONE/FOUR Source[:] SKIP MemRead MemWrite MemReg IR X_Mux MD Din Dout R_Mux LUOut MDR Source[] C_Mux Source[] ONE/FOUR Multi Cycle CPU Data Path IRWrite SKIP CU MemtoReg MR MW MemWrite MemRead DD DD8 LW SW SWP SWP8 Complete the connections marked as pril, 23 :3 am EE57 Midterm Exam - Spring 23 Page - 7 / C Copyright 23 Gandhi Puvvada

pril, 23 :3 am EE57 Midterm Exam - Spring 23 Page - 8 / S Instruction Fetch PC Incrementation PCSource= Source[:]= ONE/FOUR = S2 LW Mem Read NOP = DD DD8 LW SW SWP SWP8 LW S SW Perform simple SW S

8 pril, 23 :3 am EE57 Midterm Exam - Spring 23 Page - 8 / S Instruction Fetch PC Incrementation PCSource= Source[:]= ONE/FOUR = S2 LW Mem Read NOP = DD DD8 LW SW SWP SWP8 LW S SW Perform simple SW S Instruction Decode Register Fetch No RTL needed. No signal list SW D SWP8 DD8 S5 dd st four SWP DD SWP8 DD8 S dd 2nd four Multi Cycle CPU State Diagram S9 Branch execution 2 ee57_mt_sp23.fm C Copyright 23 Gandhi Puvvada S3 S8 SWP8 DD8 LW Writeback Perform SW Plus R-Type completion Completion S7 S

9 ee57_mt_sp23.fm 2 ( 3 points) 2 min. Cache mapping techniques: Fill-in all missing information in the table below based on information provided. In all four cases, it is the same amount of cache differently organized. byte addressable Processor -bit Data -bit address ddr Space Size 2 GBytes Cache Size use this info.! Block Size KB Words ( Bytes) Mapping Technique Direct Fully ssociative Set ssociative 2 Blocks/Set Set ssociative 8 Blocks/Set TG FIELD use this info.! BLOCK OR SET FIELD (as appropriate) WO FIELD use this info.! BYTE FIELD 2- (BE7-BE) 2- (BE7-BE) 2- (BE7-BE) 2- (BE7-BE) TG M(s) and their size(s) and comparators to compare TG(s) and their size. In the case of Direct Mapping above, we use (state a number) TG M(s) of size together with (state a number) comparator(s) each of -bit wide. In the case of Set ssociative Mapping with 2 Blocks/Set above, we use (state a number) TG M(s) of size together with (state a number) comparator(s) each of -bit wide. In the case of Set ssociative Mapping with 8 Blocks/Set above, we use (state a number) TG M(s) of size together with (state a number) comparator(s) each of -bit wide. The Fully ssociative Mapping is prohibitively expensive because you would need state a number) comparator(s) each of -bit wide. In the first case of direct mapping, the main memory shall be organized in a -way lowerorder interleaving to facilitate efficient The main memory organization is (same/different) in the above cache organizations, because In general, a set can potentially have a set-associativity equal to any number (not necessarily a power of 2). The 2-way set-associative design was implemented and substantial silicon area was left out. The VLSI team estimated that they can increase the cache size to 5 time the original size easily. We the architects did not want to change the number of sets or the Block size. What else is there to change? What is the impact on TG Ms (size and number) and Data M segregations? I pril, 23 :3 am EE57 Midterm Exam - Spring 23 Page - 9 / C Copyright 23 Gandhi Puvvada

ee57_mt_sp23.fm 3 ( 8 points) 3 min. Virtual Memory: 9 7 3. PTBR stands for. It is initiated by (hardware / operating system) and is utilized by (MMU / CCU) (i.e. memory management unit or cache control unit) to look up (TLB / Page Table / Cache Tag M).

indexing the B-level tables, next bits (S) indexing the C-level tables, and the last bits (T) indexing the D-level tables. 3.2.

How many tables of what size are built by OS 7 5 5 by this time? -level: B-level: C-level: D-level: 3.2.

3.2.3 Similarly, complete 8 distinct VPNs of your choice in TBLE-III such that the most number of,b,c tables are built by OS.

10 ee57_mt_sp23.fm 3 ( 8 points) 3 min. Virtual Memory: PTBR stands for. It is initiated by (hardware / operating system) and is utilized by (MMU / CCU) (i.e. memory management unit or cache control unit) to look up (TLB / Page Table / Cache Tag M). 3.2 Page Table: Number of,b,c,d Tables built by the OS: PQRST on the side represents a 2-bit (5-digit hex) VPN in a -level page table with upper bits (P) indexing the -level table, next 8 bits (QR) indexing the B-level tables, next bits (S) indexing the C-level tables, and the last bits (T) indexing the D-level tables Suppose the first 8 distinct virtual pages accessed by the application program had the VPNs as stated in TBLE-I (in sorted order). How many tables of what size are built by OS by this time? -level: B-level: C-level: D-level: Complete 8 distinct VPNs of your choice in TBLE-II such that the least number of,b,c,d tables are built by OS. This least set consists of of -Table(s), of B-Table(s), of C-Table(s), of D-Table(s) Similarly, complete 8 distinct VPNs of your choice in TBLE-III such that the most number of,b,c tables are built by OS. This most set consists of of -Table(s), of B-Table(s), of C-Table(s), of D-Table(s). 3.3 The advantage of (VIPT / PIPT) over (VIPT / PIPT) comes from the fact that 3. Memory addresses: In a 32-bit virtual address system using KB pages, state any two consecutive 32-bit word addresses (in hex) which do not fall in the same virtual page. I am evicting a page containing the byte with virtual address h. What is its virtual page number (in hex)?. What is the range of byte addresses residing in that page (lowest virtual byte address to highest virtual byte address). pril, 23 :3 am EE57 Midterm Exam - Spring 23 Page - / TBLE-I TBLE-II TBLE-III P Q R S T P Q R S T P Q R S T C Copyright 23 Gandhi Puvvada

5 Since we use write-back only for virtual memory, we need to maintain a dirty bit associated with (the entire TLB /the entire Page Table / each entry of the page table / each entry of the TLB / each

11 ee57_mt_sp23.fm The physical page frame number in the main memory is 2 (just 2). What is the range of byte addresses residing in that page (lowest physical byte address to highest physical byte address). _ 3.5 Since we use write-back only for virtual memory, we need to maintain a dirty bit associated with (the entire TLB /the entire Page Table / each entry of the page table / each entry of the TLB / each entry in both TLB and Page Table). 3. Fully associative mapping may not be prohibitively expensive in the case of a (TLB / L2 cache) because The next few weeks are very important as we will be covering a lot of material in weeks. Please, please do attend every lecture and discussion. nd use our office hours. Thanks. -- The EE57 Teaching Team pril, 23 :3 am EE57 Midterm Exam - Spring 23 Page - / C Copyright 23 Gandhi Puvvada

1 ( 23 points) 15 min.

1 ( 23 points) 15 min. ee57_mt_sp2.fm Spring 2 EE57 Instructor: Gandhi Puvvada Midterm Exam (2%) Date: //2, Friday Time: :M - 2:2PM in THH2 Name: Total points: 28 Perfect score: 9 / 28 ( 23 points) 5 min. Pipelining 5 5 3. I.F.R.F