Chapter 6: Datapath and Control. Principles of Computer Architecture. Principles of Computer Architecture by M. Murdocca and V.

Size: px

Start display at page:

Download "Chapter 6: Datapath and Control. Principles of Computer Architecture. Principles of Computer Architecture by M. Murdocca and V."

Ronald Barnett
5 years ago
Views:

1 6- Principles of Computer Architecture Miles Murdocca and Vincent Heuring 999 M. Murdocca and V. Heuring

2 6-2 Chapter Contents 6. Basics of the Microarchitecture 6.2 A Microarchitecture for the ARC 6.3 Hardwired Control 6.4 Case Study: The VHDL Hardware Description Language 999 M. Murdocca and V. Heuring

3 6-3 The Fetch-Execute Cycle The steps that the control unit carries out in executing a program are: () Fetch the next instruction to be executed from memory. (2) Decode the opcode. (3) Read operand(s) from main memory, if any. (4) Execute the instruction and store results. (5) Go to step. 999 M. Murdocca and V. Heuring

4 6-4 High Level View of Microarchitecture The microarchitecture consists of the control unit and the programmer-visible registers, functional units such as the ALU, and any additional registers that may be required by the control unit. Registers Control Unit ALU Datapath (Data Section) Control Section SYSTEM BUS 999 M. Murdocca and V. Heuring

5 6-5 ARC Instruction Subset Memory Logic Arithmetic Control Mnemonic ld st sethi andcc orcc orncc srl addcc call jmpl be bneg bcs bvs ba Meaning Load a register from memory Store a register into memory Load the 22 most significant bits of a register Bitwise logical AND Bitwise logical OR Bitwise logical NOR Shift right (logical) Add Call subroutine Jump and link (return from subroutine call) Branch if equal Branch if negative Branch on carry Branch on overflow Branch always 999 M. Murdocca and V. Heuring

6 6-6 ARC Instruction Formats op SETHI Format rd op2 imm22 Branch Format cond op2 disp22 CALL format disp3 i Arithmetic Formats Memory Formats rd op3 rs rs2 rd op3 rs simm rd op3 rs rs2 rd op3 rs simm3 op Format op2 Inst. op3 (op=) op3 (op=) cond branch SETHI/Branch CALL Arithmetic Memory branch sethi addcc andcc orcc orncc srl jmpl ld st be bcs bneg bvs ba PSR n z v c 999 M. Murdocca and V. Heuring

7 Data From Main Memory Address To Main Memory 6-7 C bus %r %r A bus B bus 38 a A Decoder a %r2 3 %r3 ARC Datapath %r4 c 4 C 37 Decoder c 37 5 %r5 6 6 %r6 7 %r7 8 %r8 CLOCK 9 %r9 UNIT %r b B Decoder b 37 6 From Control Unit 3 %r3 C Bus MUX to-32 MUX 3 %r3 32 %pc 33%temp 34%temp 35%temp2 36%temp3 32 MUX Control Line (From Control Unit) %ir 24 To Control Unit F F ALU F 2 F 3 From Control Unit Data To Main Memory 4 n, z, v, c Set Condition Codes (SCC) 999 M. Murdocca and V. Heuring

8 6-8 ARC ALU Operations F 3 F 2 F F Operation Changes Condition Codes ANDCC (A, B) ORCC (A, B) NORCC (A, B) ADDCC (A, B) SRL (A, B) AND (A, B) OR (A, B) NOR (A, B) ADD (A, B) LSHIFT2 (A) LSHIFT (A) SIMM3 (A) SEXT3 (A) INC (A) INCPC (A) RSHIFT5 (A) yes yes yes yes no no no no no no no no no no no no 999 M. Murdocca and V. Heuring

9 6-9 Block b 3 a 3 b 3 a 3 b a b a F :3 Diagram of ALU ALU LUT 3 ALU LUT 3... ALU LUT carry ALU LUT b -4 z 3 z 3 z z BARREL SHIFTER Direction of Shift Shift Amount (SA) 5 Barrel Shifter Control LUT... F 3 F 2 V c 3 c 3 C N Z c c SCC: Set Condition Codes 999 M. Murdocca and V. Heuring

10 6- Gate-Level Layout of Barrel Shifter Bit 3 Bit 3 Bit Bit Bit 29 Bit Bit 3 Bit 2 Shift Right SA... Bit 29 Bit 2 Shift Right SA... c 3 c 3 c c 999 M. Murdocca and V. Heuring

11 6-999 M. Murdocca and V. Heuring Truth Table for (Most of the) ALU LUTs F 3 F 2 F F Carry In... a i b i z i Carry Out... ANDCC ORCC

12 6-2 Design of Register %r Data inputs from C Bus C 3 C 3 C CLK D Q D Q... D Q Write select (from c bit of C Decoder) A bus enable (from a bit of A Decoder) B bus enable (from b bit of B Decoder) A 3 A 3 A B 3 B 3 B Data outputs to A Bus Data outputs to B Bus 999 M. Murdocca and V. Heuring

13 6-3 Outputs to Control Unit from Register %ir C 3 Data inputs from C Bus C Instruction Register %ir Instruction fields op rd op2 rs rs2 op3 bit M. Murdocca and V. Heuring

14 A bus B bus C bus Select 6-4 Data Section (Datapath) Control Section To A Decoder Microarchitecture of the ARC To C Decoder 6 C MUX MIR C field, rd 6 5 Scratchpad %i %ir rd rs2 r rs ops 6 A MUX Select MIR, rs A field 5 6 To B Decoder 6 B MUX MIR, rs2 B field 5 6 Select Control Store Address Incrementer (CSAI) Next Decode Jump CS Address MUX 248 word 4 bit Control Store 4 8 = Next = Jump = Inst. Dec. Microcode Instruction Register (MIR) A B C M M M U U U RW A X B X C X D R ALU COND JUMP ADDR CLOCK UNIT IR[3] 32 IR[3,3,9-24] to-32 MUX C Bus MUX F F 3 ALU F 2 4 F n, z, v, c %psr Control branch logic (CBL) Set Condition Codes Data In RD WR MAIN MEMORY Address 2 32 byte address space Data Out Acknowledge (ACK) 999 M. Murdocca and V. Heuring

15 6-5 Microword Format A A M U X B B M U X C C M U RW X D R ALU COND JUMP ADDR 999 M. Murdocca and V. Heuring

16 6-6 Settings for the COND Field of the Microword C 2 C C Operation Use NEXT ADDR Use JUMP ADDR if n = Use JUMP ADDR if z = Use JUMP ADDR if v = Use JUMP ADDR if c = Use JUMP ADDR if IR[3] = Use JUMP ADDR DECODE 999 M. Murdocca and V. Heuring

17 6-7 DECODE Format for Microinstruction Address op op3 IR bits op2 999 M. Murdocca and V. Heuring

18 6-8 Timing Relationships for the Registers Master sections settle. Settling time for slave sections of registers. Perform ALU functions. n, z, v,and c flags become stable. Clock Master sections of registers loaded on rising edge Slave sections of registers loaded on falling edge 999 M. Murdocca and V. Heuring

19 6-9 Address Operation Statements Comment : R[ir] AND(R[pc],R[pc]); READ; / Read an ARC instruction from main memory : DECODE; / 256-way jump according to opcode // / sethi 52: R[rd] LSHIFT(ir); GOTO 247; / Copy imm22 field to target register // / call 28: R[5] AND(R[pc],R[pc]); / Save %pc in %r5 28: R[temp] ADD(R[ir],R[ir]); / Shift disp3 field left 282: R[temp] ADD(R[temp],R[temp]); / Shift again 283: R[pc] ADD(R[pc],R[temp]); / Jump to subroutine GOTO ; // / addcc Partial ARC Microprogram 6: IF R[IR[3]] THEN GOTO 62; 63: R[rd] ADDCC(R[rs],R[temp]); / Perform ADDCC on register/simm3 / Is second source operand immediate? 6: R[rd] ADDCC(R[rs],R[rs2]); GOTO 247; / Perform ADDCC on register sources / sources GOTO 247; // / andcc 62: R[temp] SEXT3(R[ir]); 64: IF R[IR[3]] THEN GOTO 66; / Get sign extended simm3 field / Is second source operand immediate? 65: R[rd] ANDCC(R[rs],R[rs2]); / Perform ANDCC on register sources GOTO 247; 66: R[temp] SIMM3(R[ir]); / Get simm3 field 67: R[rd] ANDCC(R[rs],R[temp]); / Perform ANDCC on register/simm3 GOTO 247; / sources // / orcc 68: IF R[IR[3]] THEN GOTO 6; / Is second source operand immediate? 69: R[rd] ORCC(R[rs],R[rs2]); / Perform ORCC on register sources GOTO 247; 6: R[temp] SIMM3(R[ir]); / Get simm3 field 6: R[rd] ORCC(R[rs],R[temp]); / Perform ORCC on register/simm3 sources GOTO 247; // / orncc 624: IF R[IR[3]] THEN GOTO 626; / Is second source operand immediate? 625: R[rd] NORCC(R[rs],R[rs2]); / Perform ORNCC on register sources GOTO 247; 626: R[temp] SIMM3(R[ir]); / Get simm3 field 627: R[rd] NORCC(R[rs],R[temp]); / Perform NORCC on register/simm3 GOTO 247; / sources // / srl 688: IF R[IR[3]] THEN GOTO 69; / Is second source operand immediate? 689: R[rd] SRL(R[rs],R[rs2]); / Perform SRL on register sources GOTO 247; 69: R[temp] SIMM3(R[ir]); / Get simm3 field 69: R[rd] SRL(R[rs],R[temp]); / Perform SRL on register/simm3 sources GOTO 247; // / jmpl 76: IF R[IR[3]] THEN GOTO 762; / Is second source operand immediate? 76: R[pc] ADD(R[rs],R[rs2]); / Perform ADD on register sources 999 M. Murdocca and V. Heuring GOTO ;

20 6-2 Partial ARC Microprogram (cont ) 762: R[temp] SEXT3(R[ir]); / Get sign extended simm3 field 763: R[pc] ADD(R[rs],R[temp]); Chapter / Perform 6: ADD Datapath on register/simm3 and Control sources GOTO ; // / ld 792: R[temp] ADD(R[rs],R[rs2]); / Compute source address IF R[IR[3]] THEN GOTO 794; 793: R[rd] AND(R[temp],R[temp]); / Place source address on A bus READ; GOTO 247; 794: R[temp] SEXT3(R[ir]); / Get simm3 field for source address 795: R[temp] ADD(R[rs],R[temp]); / Compute source address GOTO 793; // / st 88: R[temp] ADD(R[rs],R[rs2]); / Compute destination address IF R[IR[3]] THEN GOTO 8; 89: R[ir] RSHIFT5(R[ir]); GOTO 4; / Move rd field into position of rs2 field 4: R[ir] RSHIFT5(R[ir]); / by shifting to the right by 25 bits. 4: R[ir] RSHIFT5(R[ir]); 42: R[ir] RSHIFT5(R[ir]); 43: R[ir] RSHIFT5(R[ir]); 44: R[] AND(R[temp], R[rs2]); / Place destination address on A bus and WRITE; GOTO 247; / place operand on B bus 8: R[temp] SEXT3(R[ir]); / Get simm3 field for destination address 8: R[temp] ADD(R[rs],R[temp]); / Compute destination address GOTO 89; // / Branch instructions: ba, be, bcs, bvs, bneg 88: GOTO 2; / Decoding tree for branches 2: R[temp] LSHIFT(R[ir]); / Sign extend the 22 LSB s of %temp 3: R[temp] RSHIFT5(R[temp]); / by shifting left bits, then right 4: R[temp] RSHIFT5(R[temp]); / bits. RSHIFT5 does sign extension. 5: R[ir] RSHIFT5(R[ir]); / Move COND field to IR[3] by 6: R[ir] RSHIFT5(R[ir]); / applying RSHIFT5 three times. (The 7: R[ir] RSHIFT5(R[ir]); / sign extension is inconsequential.) 8: IF R[IR[3]] THEN GOTO 2; / Is it ba? R[ir] ADD(R[ir],R[ir]); 9: IF R[IR[3]] THEN GOTO 3; / Is it not be? R[ir] ADD(R[ir],R[ir]); : IF Z THEN GOTO 2; / Execute be R[ir] ADD(R[ir],R[ir]); : GOTO 247; / Branch for be not taken 2: R[pc] ADD(R[pc],R[temp]); / Branch is taken GOTO ; 3: IF R[IR[3]] THEN GOTO 6; / Is it bcs? R[ir] ADD(R[ir],R[ir]); 4: IF C THEN GOTO 2; / Execute bcs 5: GOTO 247; / Branch for bcs not taken 6: IF R[IR[3]] THEN GOTO 9; / Is it bvs? 7: IF N THEN GOTO 2; / Execute bneg 8: GOTO 247; / Branch for bneg not taken 9: IF V THEN GOTO 2; / Execute bvs 2: GOTO 247; / Branch for bvs not taken 999 M. Murdocca and V. Heuring 247: R[pc] INCPC(R[pc]); GOTO ; / Increment %pc and start over

21 6-2 Branch Decoding Decoding tree for branch instructions shows corresponding microprogram lines: IR[27] Line 8 IR[28] Line 9 Line 2 ba be Line IR[26] Line 3 28 cond branch Line 4 bcs IR[25] Line 6 be bcs bneg bvs ba Line 7 bneg bvs Line M. Murdocca and V. Heuring

22 6-22 Microstore Address A B C M M M U U U RW A X B X C X D R ALU COND JUMP ADDR Assembled ARC Microprogram M. Murdocca and V. Heuring

23 6-23 A B C M M M U U U RW A X B X C X D R ALU COND JUMP ADDR 793 Assembled ARC Microprogram (cont ) Principles of Computer Architecture by M. Murdocca and 247 V. Heuring 999 M. Murdocca and V. Heuring

24 6-24 Example: Add the subcc Instruction Consider adding instruction subcc (subtract) to the ARC instruction set. subcc uses the Arithmetic format and op3 =. 584: R[temp] SEXT3(R[ir]); / Extract rs2 operand IF IR[3] THEN GOTO 586; / Is second source immediate? 585: R[temp] R[rs2]; / Extract sign extended immediate operand 586: R[temp] NOR(R[temp], R[]); / Form one s complement of subtrahend 587: R[temp] INC(R[temp]); GOTO 63; / Form two s complement of subtrahend A A M U X B B M U X C C M U RW X D R ALU COND JUMP ADDR 999 M. Murdocca and V. Heuring

25 6-25 Branch Table A branch table for trap handlers and interrupt service routines: Address Contents... Trap Handler 6 JUMP TO 2 Illegal instruction 64 JUMP TO 3 Overflow 68 JUMP TO 36 Underflow 72 JUMP TO 5224 Zerodivide 76 JUMP TO 48 Disk 8 JUMP TO 5364 Printer 84 JUMP TO 598 TTY 88 JUMP TO 648 Timer M. Murdocca and V. Heuring

26 n = 248 words n = 248 words 6-26 Microprogramming vs. Nanoprogramming w = 4 bits Original Microprogram k = log 2 (n) = log 2 () = 7 bits (a) Microprogramming vs. (b) nanoprogramming. Microprogram w = 4 bits m = nanowords Total Area = n w = = 83,968 bits Microprogram Area = n k = = 4,336 bits Nanoprogram Area = m w = 4 = 4 bits Total Area = 4, = 8,436 bits (a) (b) 999 M. Murdocca and V. Heuring

27 6-27 Hardware Description Language HDL sequence for a resettable modulo 4 counter. Preamble Statements Epilogue MODULE: MOD_4_COUNTER. INPUTS: x. OUTPUTS: Z[2]. MEMORY: : Z,; GOTO { CONDITIONED ON x, CONDITIONED ON x}. : Z,; GOTO { CONDITIONED ON x, 2 CONDITIONED ON x}. 2: Z,; GOTO { CONDITIONED ON x, 3 CONDITIONED ON x}. 3: Z,; GOTO. END SEQUENCE. END MOD_4_COUNTER. 999 M. Murdocca and V. Heuring

28 6-28 Circuit Derived from HDL Logic design for a modulo 4 counter described in HDL. Z[] DATA SECTION Z[] CONTROL SECTION x CLK M. Murdocca and V. Heuring

29 6-29 HDL for ARC MODULE: ARC_CONTROL_UNIT. INPUTS: OUTPUTS: C, N, V, Z.! These are set by the ALU MEMORY: R[6][32], pc[32], ir[32], temp[32], temp[32], temp2[32], temp3[32]. : ir AND(pc, pc); Read ;! Instruction fetch! Decode op field : GOTO {2 CONDITIONED ON ir[3] ir[3],! Branch/sethi format: op= 4 CONDITIONED ON ir[3] ir[3],! Call format: op= 8 CONDITIONED ON ir[3] ir[3],! Arithmetic format: op= CONDITIONED ON ir[3] ir[3]}.! Memory format: op=! Decode op2 field 2: GOTO 9 CONDITIONED ON ir[24].! Goto 9 if Branch format HDL description of the 3: R[rd] ir[imm22];! sethi GOTO 2. ARC control unit. 4: R[5] AND(pc, pc).! call: save pc in register 5 5: temp ADD(ir, ir).! Shift disp3 field left 6: temp ADD(ir, ir).! Shift again 7: pc ADD(pc, temp); GOTO.! Jump to subroutine! Get second source operand into temp for Arithmetic format 8: temp { SEXT3(ir) CONDITIONED ON ir[3] NOR(ir[9:22]),! addcc R[rs2] CONDITIONED ON ir[3] NOR(ir[9:22]),! addcc SIMM3(ir) CONDITIONED ON ir[3] OR(ir[9:22]),! Remaining R[rs2] CONDITIONED ON ir[3] OR(ir[9:22])}.! Arithmetic instructions! Decode op3 field for Arithmetic format 9: R[rd] { ADDCC(R[rs], temp) CONDITIONED ON XNOR(IR[9:24], ),! addcc ANDCC(R[rs], temp) CONDITIONED ON XNOR(IR[9:24], ),! andcc ORCC(R[rs], temp) CONDITIONED ON XNOR(IR[9:24], ),! orcc NORCC(R[rs], temp) CONDITIONED ON XNOR(IR[9:24], ),! orncc SRL(R[rs], temp) CONDITIONED ON XNOR(IR[9:24], ),! srl ADD(R[rs], temp) CONDITIONED ON XNOR(IR[9:24], )};! jmpl GOTO 2.! Get second source operand into temp for Memory format : temp {SEXT3(ir) CONDITIONED ON ir[3], R[rs2] CONDITIONED ON ir[3]}. : temp ADD(R[rs], temp).! Decode op3 field for Memory format GOTO {2 CONDITIONED ON ir[2],! ld 3 CONDITIONED ON ir[2]}.! st 2: R[rd] AND(temp, temp); Read ; GOTO M. Murdocca and V. Heuring 3: ir RSHIFT5(ir).

30 6-3 HDL for ARC (cont ) 4: ir RSHIFT5(ir). 5: ir RSHIFT5(ir). 6: ir RSHIFT5(ir). 7: ir RSHIFT5(ir). 8: r AND(temp, R[rs2]); Write ; GOTO 2. 9: pc {! Branch instructions ADD(pc, temp) CONDITIONED ON ir[28] + ir[28] ir[27] Z + ir[28] ir[27] ir[26] C + ir[28] ir[27] ir[26] ir[25] N + ir[28] ir[27] ir[26] ir[25] V, INCPC(pc) CONDITIONED ON ir[28] ir[27] Z + ir[28] ir[27] ir[26] C + ir[28] ir[27] ir[26] ir[25] N + ir[28] ir[27] ir[26] ir[25] V}; GOTO. 2: pc INCPC(pc); GOTO. END SEQUENCE. END ARC_CONTROL_UNIT. 999 M. Murdocca and V. Heuring

31 6-3 HDL ARC Circuit CLK IR[3] IR[24] IR[3] CS CS CS 4 CS 6 The hardwired control section of the ARC: generation of the control signals CS 5 CS 9 9 CS 8 6 CS 7 IR[2] CS CS 2 CS 3 CS 4 CS 2 CS CS CS 6 CS 9 7 CS CS M. Murdocca and V. Heuring

32 IR[24] IR[23] IR[22] IR[9] IR[22] IR[9] IR[22] 6-32 HDL ARC Circuit (cont ) Hardwired control section of the ARC: signals from the data section of the control unit to the datapath. IR[28] IR[27] Z IR[28] IR[27] IR[26] C IR[28] IR[27] IR[26] IR[2] IR[2] IR[25] N IR[28] IR[27] IR[26] IR[25] C IR[3] CS 8 IR[9] IR[2] IR[2] IR[22] IR[28] CS 9 CS 9 IR[24] IR[23] IR[22] IR[2] IR[9] IR[3] CS8 IR[9] IR[2] IR[2] IR[22] IR[9] IR[2] IR[2] IR[23] IR[24] CS 9 IR[24] CS 9 IR[23] IR[3] CS 9 CS 8 IR[22] IR[2] IR[9] IR[2] CS 3 CS 2 CS CS 4 CS CS 7 CS 6 CS 2 CS 3 CS 5 CS 4 CS CS 2 CS 2 4 CS CS CS 3 CS 4 CS 3 CS CS 5 8 CS2 CS CS 7 6 CS 5 CS CS 6 CS CS 8 7 CS 3 CS 5 CS 4 CS 6 CS 2 CS 9 CS 7 ALU[] ALU[] ALU[2] ALU[3] IR[2] IR[2] CS 8 CS IR[3] IR[3] CS 8 IR[3] CS CS 8 CS 8 CS 3 CS 9 CS2 CS 9 CS CS CS 2 CS 5 CS 6 CS 2 CS 3 CS 5 CS 4 CS CS 6 8 Write CS7 CS 7 CS CS 4 BMUX CS 9 CS 2 CMUX AMUX Read C[] C[3] C[4] C[5] A[] A[3] A[4] A[] A[2] A[5] C[2] C[] B[] B[] B[2] B[3] B[4] B[5] 999 M. Murdocca and V. Heuring

33 6-33 Case Study: The VHDL Hardware Description Language The majority function. a) truth table, b) AND-OR implementation, c) black box representation. Minterm Index A B C F A B C A B C A B C A B C A B C F A B F C Majority Function a) b) c) 999 M. Murdocca and V. Heuring

34 6-34 VHDL Specification Interface specification for the majority component -- Interface entity MAJORITY is port (A_IN, B_IN, C_IN: in BIT F_OUT: out BIT); end MAJORITY; Behavioral model for the majority component -- Body architecture LOGIC_SPEC of MAJORITY is begin -- compute the output using a Boolean expression F_OUT <= (not A_IN and B_IN and C_IN) or (A_IN and not B_IN and C_IN) or (A_IN and B_IN and not C_IN) or (A_IN and B_IN and C_IN) after 4 ns; end LOGIC_SPEC; 999 M. Murdocca and V. Heuring

35 6-35 VHDL Specification (cont ) -- Package declaration, in library WORK package LOGIC_GATES is component AND3 port (A, B, C : in BIT; X : out BIT); end component; component OR4 port (A, B, C, D : in BIT; X : out BIT); end component; component NOT port (A : in BIT; X : out BIT); end component; -- Interface entity MAJORITY is port (A_IN, B_IN, C_IN: in BIT F_OUT: out BIT); end MAJORITY; 999 M. Murdocca and V. Heuring

36 6-36 VHDL Specification (cont ) -- Body -- Uses components declared in package LOGIC_GATES -- in the WORK library -- import all the components in WORK.LOGIC_GATES use WORK.LOGIC_GATES.all architecture LOGIC_SPEC of MAJORITY is -- declare signals used internally in MAJORITY signal A_BAR, B_BAR, C_BAR, I, I2, I3, I4: BIT; begin -- connect the logic gates NOT_ : NOT port map (A_IN, A_BAR); NOT_2 : NOT port map (B_IN, B_BAR); NOT_3 : NOT port map (C_IN, C_BAR); AND_ : AND3 port map (A_BAR, B_IN, C_IN, I); AND_2 : AND3 port map (A_IN, B_BAR, C_IN, I2); AND_3 : AND3 port map (A_IN, B_IN, C_BAR, I3); AND_4 : AND3 port map (A_IN, B_IN, C_IN, I4); OR_ : OR3 port map (I, I2, I3, I4, F_OUT); end LOGIC_SPEC; 999 M. Murdocca and V. Heuring

1 The ARC processor (data path and control)

1 The ARC processor (data path and control) 1 The ARC processor (data path and control)... 1 1.1 Introduction... 2 1.2 Main part of data path... 2 1.3 Data path... 2 1.4 Controller... 3 1.4.1 Micro instruction