CS/EE 5710/6710 Digital VLSI CAD Assignment #1 Due Tuesday, September 10th, 5:00pm Use handin on a cade machine for submitting the assignment

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1 CS/EE 5710/6710 Digital VLSI CAD Assignment #1 Due Tuesday, September 10th, 5:00pm Use handin on a cade machine for submitting the assignment For this assignment you ll use Digital VLSI Chip Design with Cadence and Synopys Tools.. You ll need to look at Chapters 1-4 for this assignment. The chapters are tutorial in nature so you should be able to follow along as you re learning the tools and completing the assignment. Note that the CAD manual was written with examples from v5.1.4 of the Cadence tools. This year we re using v6.1.5 so things will look a tiny bit different. There is a V5 to V6 conversion guide on the class wed site. Assignment 1. Complete the first part of the Cadence Composer tutorial in Chapter 3 by making a new library and designing a full adder using the standard cells in the NCSU_Digital_Parts library. Note that this is a different parts library than used in the CAD book tutorial! Pay attention to where your gates are coming from! You are welcome to copy the schematic in the CAD book, or make a different gate-level circuit that also implements a Full Adder. The schematic for your full adder is one of the deliverables for this lab. a. Name your new library CAD1 instead of the name used in the CAD manual. You ll be turning in this entire project directory at the end of the assignment. b. Name your full adder schematic FullAdder c. Print a copy of your full adder shcematic into your VLSI directory by printing to a file. Name this file FullAdder.ps. See the information in Section 3.4 of the CAD manual for details. 2. Test your full adder using NC_Verilog. You ll need information from Chapter 4 to simulate your design. Even though we re using NC_Verilog (Section 4.1.2), you should read section on Verilog-XL because there are some general simulation instructions there that pertain to all of our simulators. Deliverables for this section of the lab include the Verilog testbench you wrote for your full adder, the output from that simulation, and the timing waveform that results from the simulation. a. Use the default FullAdder_run1 directory for simulation. (Use the default *_run1 directory for each of the simulations in this assignment) b. Make sure that your testbench uses $display statements, and error checking. We ll look for your simout.tmp file in the FullAdder_run1 simulation directory that you ll turn in to see the $display output. c. We ll find your testfixture.verilog testbench file in your NC_Verilog *_run1 directory. d. Print the timing waveform from simvision using the print to file procedure described on page 63 of the CAD manual. Call this file FullAdderSim.ps. This file will go in your FullAdder_run1 simulation directory by default.

2 3. Create a symbol for your full adder and use it in building a 3-bit adder in a new schematic. The schematic for your 3-bit adder is another deliverable. a. Call your 3-bit adder schdmatic add3 b. Print a copy of your add3 schematic using the print to file procedure. Call that file add3.ps. 4. Simulate the 3-bit Adder using NC_Verilog and a tesetbench that you write for the simulation. You will turn in the Verilog testbench, the output from the simulation, and the timing waveform that results from simulation. a. We ll find your simout.tmp and testfixture.verilog files in your add3_run1 simulation directory that you will turn in. b. Print the timing waveform of the simulation using the print to file procedure. Call this file add3sim.ps. 5. Complete the next part of the tutorial in Chapter 3 by designing a 2-input NAND gate using nmos and pmos transistors from the UofU_Analog_Parts library. Use vdd and gnd symbols for power and ground connections. Again, pay attention to where your gates are coming from! Create a symbol for the NAND that looks something like a NAND symbol. That is, modify the rectangle provided by Cadence to something that looks more like a standard NAND symbol. Simulate your NAND and validate that it is behaving correctly using NC_Verilog and a new testbench. Turn in the schematic for the NAND, the Verilog testbench, the simulation output, and the timing waveform that results from simulation. a. Name this circuit nand2. b. Print your nand2 schematic to a file called nand2.ps. c. We ll find your simout.tmp and testfixture.verilog files in your nand2_run1 simulation directory. d. Print the simulation waveform into a file named nandsim.ps. 6. Using instances of your own 2 input NAND gate, build a circuit that implements the following Boolean function (don t minimize or manipulate the function, and don t use any gates except for your own NAND gate). a. Name this circuit function. b. print the schematic for the circuit to a file named function.ps. 7. Simulate this circuit using NC_Verilog and validate the timing diagrams. Turn in the Verilog testbench, the simulation output, and the timing waveform that results from simulation. a. We ll find your simout.tmp and testfixture.verilog files in your function_run1 simulation directory. b. Print the timing waveform from simulation into a file named functionsim.ps.

3 Additional Details For all of these simulation tasks, make sure that your Verilog test fixture uses "if" and "$display" statements to check for the correct results in the simulation. You should be able to tell from running your test fixture whether the circuit is working correctly before you look at the timing waveforms (that is, if the circuit produces an incorrect output, an error message should be printed!). For these simulations, and for subsequent simulations in this class, you should either test things exhaustively (i.e. test for all possible input combinations), or describe on a separate sheet what tests you did run and justify why that is a good set of tests. It s unlikely that you ll be able to test larger circuits in future labs exhaustivly so you ll have to put some thought into what to test and why that is a good set of tests. However, exhaustive testing will work fine for this assignment. Also, make sure to use an Asheet frame from the UofU_Sheets library on every schematic. Spend the time to make your schematics neat and orderly. Straighten out the wires, space out the components appropriately, don't over crowd, and generally make things look nice. Neatness counts when grading schematics. Note that this assignment is to be done individually. We'll form teams later. CAD Tool Setup Look at Chapters 1 and 2 for information about configuring and starting the tools. Note also that the tool paths in Chapter 2 of the CAD book are close, but not exactly the right paths to use. In particular (these things you only have to do once if you do them correctly): o Make a new directory in which to start up the tools. I recommend making a directory named VLSI in your home directory. o Make a new directory for Cadence under that VLSI directory. I recommend calling it cadence-f13 so that you can keep it isolated from other classes in the future that might use different versions of the tools. Here is the recommended sequence of steps (read the material in Chapter 2 also!). First you will need to log in to a CADE linux machine. Cadence tools are mounted on all the linux machines in the CADE lab. cd mkdir VLSI cd VLSI mkdir cadence-f13 Now set things up so that you ll automatically use the correct version of the tools, and the correct version of the class files. o Use the cad-ncsu script from /uusoc/facility/cad_common/local/bin/f13/cad-ncsu for running the Cadence tools. The easiest thing to do is make sure your search path contains /uusoc/facility/cad_common/local/bin/f13

4 o Set your LOCAL_CADSETUP variable to /uusoc/facility/cad_common/local/class/6710/f13 This is different than what the book says! Make sure you spell LOCAL_CADSETUP correctly! It s NOT CADESETUP The easiest way to do this once and not have to worry about it for the rest of the semester is to edit your.cshrc (or.tcshrc if you use that) to add the following things (if you use bash as your shell, the syntax will be slightly different and you will have to figure that out because I don t use bash ): set path = ($path /uusoc/facility/cad_common/local/bin/f13) setenv LOCAL_CADSETUP /uusoc/facility/cad_common/local/class/6710/f13 Now that these lines are in your.cshrc (or other setup file), the next time you login or start a new shell you will be able to connect to your VLSI/cadence-f13 directory and start up the Cadence tools with cad-ncsu. cd VLSI/cadence-f13 cad-ncsu Things to Turn In Turn in this assignment using the handin program on a CADE linux machine. This is a program that securly transfers data from your account to the class account. The general syntax for the handing process is: handin cs6710 <assignment-name> <file-to-hand-in> One issue with handin is that you can only use it to hand in one file at a time. So, to make things easier, you should use tar to make a file that contains all the files that you want to handin. The simple syntax for tar is: tar [options] [file] Options that are useful include: -c : this creates a new tar archive -r <files> : this appends files to an existing archive -f <filename> : this specifies which archive file you re talking about -v : be verbose and list the files that are being processed -x : extract files from an archive -t : list the files that are in an archive Examples: # create a new archive named archive.tar and put files foo and bar in the archive tar -cf archive.tar foo bar

5 # list all the files that are contained in the archive named archive.tar tar -tvf archive.tar # append a file named trythis.txt to an existing archive tar -rf archive.tar trythis.txt For this assignment, you will begin by creating an archive named cad1.tar and put your CAD1 library directory in it: cd ~/VLSI tar cf cad1.tar CAD1 Now, add the simulation directories for each of your simulation runs to the tar file. For example: tar rf cad1.tar FullAdder_run1 add3_run1 nand2_run1 function_run1 Add the schematic plots tar rf cad1.tar FullAdder.ps add3.ps nand2.ps function.ps If you want to check what s in your.tar file you can check with: tar tvf cad1.tar When you have everything assembled in the tar archive, you can turn it in using handing with: handin cs6710 CAD1 cad1.tar This will transfer the cad1.tar archive file to the cs6710 account, for the CAD1 assignment. To make sure it was submitted properly you can say: handin cs6710 CAD1 That will show you what has been turned in. You can always overwrite a file that has been turned in using handin, so if you made a mistake, or want to update your submission, you can submit again as many times as you need to up to the due date/time for the assignment.