ECE425: Introduction to VLSI System Design Machine Problem 3 Due: 11:59pm Friday, Dec. 15 th 2017

Transcription

1 ECE425: Introduction to VLSI System Design Machine Problem 3 Due: 11:59pm Friday, Dec. 15 th 2017 In this MP, you will use automated tools to synthesize the controller module from your MP2 project into a network of standard cells, place those cells onto a layout, and route the cells together into a complete implementation. You will see the differences between manual and automatic circuit implementation. The datapath you created in MP2 optimizes every transistor for optimum efficiency within the well-defined and detailed constraints of the datapath topology and the TSMC process design rules. As you translated the logic specifications to schematics, you could apply your full knowledge of logic optimization to improve the overall design. However, our automated tools cannot adapt to the specific task of designing an Am2901, as they are designed to solve the most general problem of circuit design. Here is a comparison: Task Human engineer Design automation tools Logic optimization Full knowledge of Boolean Algebra, plus you can go back and change the overall topology. Incremental optimization based on initial specification + Guess and check. Final results based on initial Cell design Integration & routing You know every instance of how every cell will be used, and design for one process. Ability to discover physical realities, learn, and revise. approximation. Our MOSIS-based cell library is generalized for many manufacturers and for ease of use to tools. Designed for speed and generality. Placement is a best guess, routing cannot modify placement. A purely automated approach cannot approach human thoroughness, critical thought, and ingenuity. But it is much less work. Part I. Synthesis We will use Synopsys Design Vision package to perform logic synthesis. Initialize 1. Execute below command in order. module load cadence/aug2016 module load Synopsys_x86-64 This will load the Cadence and Synopsys modules and change into your MP directory (~/ece425.work). 2. Extract the starter kit into your work directory: run

2 tar xvf ~ece425/ece425mp3_fall17.tar. 3. Execute the tool by typing design_vision in your work directory. Do not run it in the background with &. 4. Select File => Read and open your controller.v file. 5. Choose File => Execute Script and double-click tsmc250target.dc. Set constraints Most of the controller should not be critical to the timing of the Am2901, but the decoder generating the select_a and select_b signals must be fast. We will try synthesizing at a couple different speeds to see the effect of changing the desired performance. 1. Select the controller module in the leftmost part of the window under Logical Hierarchy. 2. Select Pins/Ports from the scroll-down menu of the right window. 3. Click and drag over all the select_a and select_b signals, as well as a[3:0] and b[3:0], to highlight all the pins on the controller associated with the decoder. 4. Choose Attributes => Optimization Constraints => Timing Constraints. 5. Enter 275 for Max rise and Max fall. (The units are picoseconds.) Leave the minimum constraints blank. 6. Under Group name, enter decoder. Click OK. 7. Go back and highlight only the select_a/b signals. 8. Select Attributes => Operating Environment => Load. 9. Set Capacitive load to 5. (The units are picofarads.) If you included inverters in your regbit cell and provided only one select_a_hi and one select_b_hi input, use 10 instead. Click OK. Synthesis Choose Design => Compile Ultra and click OK, and your design is synthesized! You can see the resulting schematic by right-clicking controller in the hierarchy section and selecting Schematic View. Identify the register file decoder which generates the select_* inputs. Report the area you got in this setting. If you cannot find the area, select Design => Report Area, and record the Total cell area. Now, we will try loosening the timing budget. Select the select_*, a[3:0], and b[3:0] signals again, and open the timing constraints window. Change the max rise and fall constraints to 325 picoseconds and click OK. Redo the previous paragraph, recording the same values. Report the area you got in this setting. To avoid checking the properties of every cell, you may assume all the cells on a given level with the same symbol are the same. The final number in the cell name specifies drive strength, which is unlikely to vary among cells on the same level. Export the design Choose File => Save as and select Verilog as the format. Name the file as controller_synth.v.

3 Part II. Place & Route Most of the remaining work will be set under two constraints for the layout tool: 1. We want to place the controller above the datapath in the global floorplan. 2. The layout from MP2 exactly defines the bus of wires connecting the datapath and controller. Define the place & route area 1. Launch virtuoso and open your datapath layout. 2. Choose Create => P&R Objects => P&R Boundary, draw a rectangle with similar width and height with your MP2 layout, which entirely covers your MP2 layout. 3. Calculate the necessary height of the P&R area: a. Start with the cell area from the second synthesis run, which you saved. b. Multiply this number by 1.2 to leave a margin. c. Divide by the width of the rectangle to find the desired height. d. Round up to the nearest multiple of 15.12, which is the cell height in our synthesis library. 4. Select the P&R boundary box, press q to pop out its properties window. Enter the four coordinates of the rectangle. For example, if the width of your MP2 layout is 400, and the calculated height of the P&R area is (For most of your designs, the height of the P&R should be 30.24), the four coordinates are (0 0)( ) ( )(400 0) 5. Choose the Move tool and set Snap Mode to Orthogonal. Move the rectangle up so that its bottom touches all the pins in your MP2 layout but doesn t overlap anything else in the datapath. This layout will serve as a floorplan for the whole chip. We will save it in the industry-standard floorplan file format. From the CIW, choose File => Export => DEF. Specify the source library, cell, view names to your datapath layout. Set the file name to am2901.def and click OK. We are finished with virtuoso for now. Load your design into Cadence Encounter We will use Cadence Encounter to manage the place & route design flow. Launch it from a new terminal in your work directory by typing encounter. (Do not use an & sign to launch it in the background, because it requires an interactive command line.) 1. Choose File => Import Design. Click Load, change files of type to All Files (*) and doubleclick mp3.conf. This tells Encounter about your controller_synth.v and the VTVT cell library. Click OK. Note that you need to modify mp3.conf if you used a different name for your verilog. 2. Choose File => Load => DEF and double-click am2901.def. You should only see the P&R Boundary box and internal interface pins. 3. In the current floorplan, Encounter is still unaware that the bottom of the controller is a special interface. (Even though it s full of pins.) 4. In the encounter shell, execute: setdrawview fplan. Alternatively, choose Floorplan view from the GUI toolbar. Most CAD tools provide a shell to execute commands. In fact,

4 the GUI commands will translate to shell commands internally. 5. Choose Floorplan => Edit Floorplan => Create Pin Blockage, draw a narrow rectangle just covering the bottom edge of the controller. This is to prevent the P&R tool from placing pins around this edge. 6. Choose Floorplan => Edit Floorplan => Create Routing Blockage, draw a rectangle inside controller, then use the resize tool to make it cover all your pins in datapath. Ideally, the blockage touches the bottom of controller. However, you might need to leave a small gap between your blockage and controller (e.g., the top part of pins are kept unblocked) such that the router can have enough resource to access/connect to those pins. This is to prevent the router routes into datapath and mess up with your datapath design. A floorplan with pin/routing blockage added looks like the following: 7. To prevent the pins being changed by encounter, choose Edit->Find/Select Object. In the pop-up window, select Object Type as Pin, Mode as And List. Add two items: a. Property: status, operator =, value: PLACED b. Property: name, check NOT, operator: Match, value: U After you added the above two items to the find criteria, click Find. This will select all your control pins. Now, go back to the main window, click q to open the property window. Check Common, change the status from PLACED to FIXED to prevent them being changed. Select Apply all and OK.

5 Add a power grid Now there is a basic floorplan, but we still need to add power rails. If we don t do this now, Encounter will be very hesitant to draw them on top of the already-placed cells! 1. Choose Power => Power Planning => Add Stripe... Browse the Net(s) and add vdd and vss 2. Set the width to 1 (the unit is microns). Leave Spacing at Click OK.

6 3. Choose Route => Special Route. Browse the Net(s) and add vdd and vss. Click OK. 4. Zoom into the intersection of the horizontal and vertical metal and check that there are vias connecting the layers of the grid. Place and route Choose Place => Standard Cells and click OK. Choose Route => NanoRoute=> Route and click OK again. Check the console log and make sure there is no DRC violations. You can switch to Physical View to see result of automatic Place & Route. Wasn t that easy? It s time to record results. Choose File => Report=> Summary. Save and print the report to a file. Don t worry about routing warnings, but your area Effective Utilization should be below 1. Actually, there is one more step. Choose Place => Physical Cells => Add Filler. Click Select, choose filler, Add, then Close, and OK. This connects the nwells empty gaps across between cells. (Incidentally, these filler cells may overlap, resulting in area usage greater than one.) Export back to virtuoso We will integrate the controller with the datapath in Virtuoso. 1. Save the generated layout in the industry-standard GDSII format by choosing File => Save => GDS. Set Output Stream File to controller.gds, and Map File to vtvt/vtvt_tsmc250_lef/vtvt_soce2df2.map. Click OK. 2. In virtuoso CIW, choose File => Import => Stream. Set Stream File to controller.gds, and Library to ece425mp3.

7 3. Click Show Options, and switch to the tab Layers, click load under the Map File, and set the same map file as before: vtvt/vtvt_tsmc250_lef/vtvt_soce2df2.map. 4. Click Apply to import the synthesized layout. Create a new layout cell am2901 and place an ece425mp3/controller and an ece425mp2/datapath inside it. You should click the origin of the canvas to place both instances. Generate a printout showing your overall integration and measure the height and width using the ruler to generate your total layout area. In the LSW, click NV and then center-click the metal3 and metal4 drw and net layers. Make sure the connections between the controller and datapath are visible on the printed page. Normally there would be additional verification at this point to double-check everything, and extra steps to add the structures supporting the 2901 s pins, but you ve earned a break. You re done! Congratulations to be a qualified chip designer!

8 MP3 Report (12.5 points): 1. Synthesis (rise/fall constraints = 275 and 325 respectively): Record the area of the controller for each constraint settings. Print the controller schematic generated by synthesis 2. Place and route: Attach the summary report. 3. Top level layout: Print top-level (complete AM2901 with controller and datapath) layout with Metal 3 only. (Include Metal 3 & 4 if metal 4 was used in MP3) Use ruler to measure the height and width, and calculate the total layout area. You MUST write down clearly your total area on the first page of your MP3 report.