HOMEWORK 9 CMPEN 411 Due: 4/12/ :30pm
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1 HOMEWORK 9 CMPEN 411 Due: 4/12/ :30pm Learning Objective Complete the full 8 bit RISC microprocessor chip design by placing the processor core design into the 40 pin 'tiny' chip pad frame. Do verify the functioning and timing from the 'pad-to-pad' simulation. Instruction This semester, we are building a simple microprocessor shown below. It is an 8-bit RISC processor, its full description and specification is posted at: Now the microprocessor core design needs to be placed into the chip pad frame to complete the chip. Sample pad frame 'p3tinyfr1' for the class chip fabrication, 40 pins total, 1000um X 1000um inside area
2 1. Homework 9 preparation: Create a directory 'hw9yourlastname' under c411 directory (assuming you have c411 directory in your home for this class). Change the current directory to hw9yourlastname. Set up the directory for a new Cadence Virtuoso library. Then start the hw9 design project. For example, my hw9 directory will be 'hw9choi' and I will be running the following unix commands right after I login to my account: % cd c411 % mkdir hw9choi % cd hw9choi % runcds % virtuoso & You can follow the same except that you need to use your last name after 'hw9'. 2. Once the Virtuoso is running, create the new library named 'hw9yourlastname' first. Attach the NCSU_TechLib_ami06 technology to your 'hw9yourlastname' library. Then exit the Virtuoso to add the pad frame library path and your hw8 library path to your hw9 project. One can manually add some library paths to hw9 project and copy all the necessary cells from those library to the new hw9 library. After copying all the cells, one MUST delete the other library paths, leaving only the 'hw9yourlastname' library, containing all the cells for the complete chip. 3. Collect all the components (cells) in the hw9yourlastname library, it will be 'tar' and 'zipped', and turn-in to the instructor for grading. Please use 'Copy Wizard...' from the virtuoso library manager to copy your previous homework cells and the instructor's pad frame cells to the hw9yourlastname library. This way, you can collect all the files into the hw9yourlastname directory and it will allow the grading. Otherwise, your hw9 project folder results in missing files which will cause the design verification for grade to fail. You will lose points if your turned-in hw9 design files cannot be verified by grader due to missing files or cells. 4. To manually add the library path, I will be running the following unix editing command for cmpen 411 class: % xe cds.lib The file cds.lib exists in your hw9yourlastname directory once you created the library hw9yourlastname with Virtuoso. My file contains the following two lines: INCLUDE /home/noncse/kyusunt/cds.lib DEFINE hw9choi /home/noncse/kyusunt/cmpen411/hw9choi/hw9choi Similarly, your cds.lib file will contain your account path and hw9yourlastname in place of mine above. Then I will add the following two lines: DEFINE hw8choi /home/noncse/kyusunt/cmpen411/hw8choi/hw8choi DEFINE p500tiny /home/faculty/kyusun/c411/cd6/ncs/c50/padkc/p500tiny The first line is to add my hw8 library to my hw9 project. You must type your directory path and hw8yourlastname in place of my information. The second line is to add the p500tiny pad library to your hw9 project, you must type it exactly as it is shown. So the overall cds.lib file will contain the following four lines in my case: INCLUDE /home/noncse/kyusunt/cds.lib DEFINE hw9choi /home/noncse/kyusunt/cmpen411/hw9choi/hw9choi DEFINE hw8choi /home/noncse/kyusunt/cmpen411/hw8choi/hw8choi DEFINE p500tiny /home/faculty/kyusun/c411/cd6/ncs/c50/padkc/p500tiny Now be sure to save the file and Quit the cds.lib file editing.
3 5. To copy the cells from your hw8 and the p500tiny library, run Virtuoso. Once the Virtuoso is running, the library manager will show the two libraries: hw8yourlastname and p500tiny in addition to your hw9yourlastname library. First select the hw8yourlastname library in your Library Manager window. Then select the 'Copy Wizard...' option under the 'Edit' pull-down menu in the library manager. The 'Copy Wizard' window will pop. Set the 'Destination Library' to your hw9yourlastname. Then select the cells from your hw8 library to be copied to your hw9 library. You will need to copy Layout, Schematic, and Symbol files of each cell. Click 'OK' to copy them. Then select the p500tiny library in your Library Manager window. Again, select the 'Copy Wizard...' option under the 'Edit' pull-down menu in the library manager. The 'Copy Wizard' window will pop. Set the 'Destination Library' to your hw9yourlastname. Then select the cells (all the cells) from the p500tiny library to be copied to your hw9 library. Again, you will need to copy Layout, Schematic, and Symbol files of each cell. Click 'OK' to copy them. Now quit (Exit) Virtuoso. 6. Once all the cells needed are copied to your hw9 library, you MUST delete the hw8 and p500tiny library paths from the cds.lib file. To do that, again edit cds.lib file and delete the last two lines. This will leave only the hw9 library in your Library Manager the next time you start the Virtuoso. In this way, your hw9 library will contain all the needed cells once you finished the project. 7. Use hierarchical design method to manage design complexity. That is, design simple cells and design top cell which combines simple cells. The Cadence tool Virtuoso assumes all design is done this way, uses cellview to manage cells. Use meaningful names for the cells; for example, use 8bitMicroprocessor rather than hw8 for the microprocessor. For your hw9 project, you MUST name 'aaamicro8top' as the top cell - the complete chip. 8. Now complete the full 8 bit RISC microprocessor chip design by placing the processor core design into the 40 pin 'tiny' chip pad frame. Do verify the functioning and timing from the 'pad-to-pad' simulation. 9. As in any chip design, the design goal is to layout the circuit in a small area, and achieve very fast signal communication. You may want to re-shape and update your design so that it will fit the 40 pin pad frame. Do assign each pin pad for the input, output, program data, vdd, gnd, clock, reset, etc. There are only 40 pins, any left-over pins can be used for testing signals. 10. The pads in the frame can be re-arranged. Any pad can be replaced with another pad. There are input signal pad, output signal pad, in/out bidirectional signal pad, vdd pad, gnd pad, etc. pin The final chip pin signal assignment must be made in the following way:
4 12. Final chip die will be placed in the 40 pin Dual In-line Package (DIP), the bonding wire placement from the chip pads to the package pin leads is shown below (top view): 13. Add two new circuits to the chip: (1) a 21 bit shift register to program the processor chip's SRAM in serial fashion, and (2) a on-chip clock circuit to generate internal clock signal. The schematic diagrams are shown in Appendix A below. 14. Be sure to connect all of the power vdd! and gnd! lines with thicker metal layers (m1 or m2 or m3). Also use as many contacts as possible for the power line connections. 15. Be sure to put the signal labels on the bonding pad with m3 layer. Also be sure to include at least one vdd pad and one gnd pad, and label them. Make only one vdd! label and one gnd! label. 16. The design must be free from the DRC errors and pass the LVS checking. 17. Extract the circuit from the layout including the parasitic capacitances. Then hspice simulate the extracted circuit netlist. Any of the timing measurements required for the questions below must use the simulation of the extracted
5 circuit from the layout including the parasitic capacitances. Place 1pF load capacitor on the output pads, in.hsp file for the pad to pad simulation. 18. To verify the functioning, design the Hspice simulation files:.hsp,.s, and.sp files. Your simulation output must show all signals. Design your.hsp file to show the following eight instruction executions in sequence. However, the program execution must be proceeded by the program storing in the program memory through the pads. So, the simulation must include program storing and then program execution. Explain your simulation: writing and execution sequence with the signals. The timing must include pads and load capacitors on the output pads. MV 0,0 MV #9,5 MV #8,7 MV 7,0 ADD 5,0 SUB 5,7 BC 6 IN 3 OUT You can always add more labels on the layout to see the microprocessor internal signals on the simulation output. This will help debugging the processor, visualizing the signal propagation, and analyzing the circuits. 20. For your microprocessor simulation, explain the instruction execution time. How do you measure the instruction execution time from the simulation result? Please explain. What is the worst case instruction execution time of your microprocessor? Please explain the worst case instruction execution time. 21. How fast can you repeat the clock signal CK while the program properly executing? 22. From the instruction execution simulation, list the delay times of each sub operations, which will be added to make up the one instruction execution cycle. Do for all 7 instructions. Which instruction is the fastest? Which instruction is the slowest? Why? Explain. 23. Which component is the slowest? Why does it take so long? How can we make it faster? Design the.hsp file to demonstrate the worst case instruction execution of the microprocessor while maintaining the correct output result. What limits the maximum speed of operation? Show the simulation plot to substantiate your answer. 24. How many transistors are used in your microprocessor chip design (including the pads)? 25. Did you use static, dynamic, or pass transistor logic? 26. Are there any errors in schematic? 27. Is there an error in layout? Does your layout pass the DRC checking without errors (including the pads)? 28. Is there a miss match on the schematic versus layout? Does your design pass the LVS checking without errors (including the pads)? 29. Extract the circuit from the layout including the parasitic capacitances. Then hspice simulate the extracted circuit netlist. Be sure that your signal label is placed at the pad so that the simulation is 'pad-to-pad' signal simulation. What is the worst case output signal rise time, fall time, and delay time? The worst case delay time is from which input to which output? Explain the signal path for the worst case delay time (this is called critical signal path)? Worst case delay time: T = nsec.
6 30. What is the total layout height and width? What is the total layout area measured in um**2? Area: A = um**2 (including the pads). 31. What is the AT**2 measure of your design? AT**2 = um**2 nsec**2 (including the pads). 32. Create a hw9 report file hw9yourlastname.doc and include captured image of layout and the simulation results. Add your explanations and comments. On the Linux machines in room 218 IST, one can use 'openoffice.org' program for the document creating and editing, and use 'gimp' program for the image capture and processing from the screen. 33. The hw9 report file must also include the answers to the questions. 34. The hw9 report file can be in.doc or.pdf, must include a cover page for student information such as 'CMPEN 411, Homework 9, your name, etc. Please use the sample Homework 9 report format, the sample hw9 report file is posted: Sample hw9 Report 35. Create a tarred zip file of your hw9yourlastname directory in c411 directory. It will contain the schematics, symbols, layouts,.hsp,.sp files, and.doc report file. In your c411 directory, use the following unix commands % tar -czvf hw9yourlastname.tgz hw9yourlatname to create a tarred zip file of hw9yourlastname library. For example, % tar -czvf hw9choi.tgz hw9choi will archive the directory hw9choi and create a zipped file hw9choi.tgz in my c411 project directory. For the grading, the command tar xzvf hw9choi.tgz will be used to restore project. Please delete.tr0 files before zipping, for their sizes are usually large. 36. Turn-in your project zip file through Penn State ANGEL. Deposit your zip file into the Homework 9 DropBox under CLASS tab in CMPEN 411 Course. 37. Make sure that you include all the files necessary into your project folder, in order to verify for grading. Turn-in your project before 11:30pm on the due date. Apendix A (1) The 21 bit shift register diagram: The 21 bit shift register signal connection diagram. Chip pins: SI (Data Shift-In), SO (Data Shift-Out, same as widat<0>), and ck-sh (Data Shifting Clock) are associated with this circuit.
7 The 21 bit shift register schematic diagram. Zoom-in view of the 21 bit shift register schematic diagram, left part. Zoom-in view of the 21 bit shift register schematic diagram, middle part. Zoom-in view of the 21 bit shift register schematic diagram, right part. Please note the output signal names.
8 (2) The on-chip clock circuit: The on-chip clock circuit block diagram. Chip pins: ck-in (Clock-In), ckb-out (Clockb-out), osfstart (Oscillator Frequency Start), osfout (Oscillator Frequency Out), osfs<1>, and osfs<0> (Oscillator Frequency Select) are associated with this circuit. The 31 state ring oscillator schematic diagram. Zoom-in view of the 31 state ring oscillator schematic diagram, left part. Zoom-in view of the 31 state ring oscillator schematic diagram, middle part. Zoom-in view of the 31 state ring oscillator schematic diagram, mid-right part.
9 Zoom-in view of the 31 state ring oscillator schematic diagram, right part. ================================================================================
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