1. Introduction EE108A. Lab 1: Combinational Logic: Extension of the Tic Tac Toe Game

Transcription

1 EE108A Lab 1: Combinational Logic: Extension of the Tic Tac Toe Game 1. Introduction Objective This lab is designed to familiarize you with the process of designing, verifying, and implementing a combinational logic circuit. In particular you will get an overview of the tools we ll be using throughout the quarter and how they interact. For this lab you will be taking the provided Tic Tac Toe game and extending it as in problem 9.8c in the reader. Please make sure you have read and studied chapter 9.4 of the reader before starting this lab. The code provided here is basically just that described in the book with a bit of glue code to take in input from the pushbuttons and output it to the screen. If you don t understand the design of the game from the book you are going to have a very hard time making this lab work. What you ll be doing Logic design consists of three main parts: verifying, verifying, and verifying. Well, technically you design something, then you verify it, then you implement it, and then you verify it again, but most of your time will be spent making sure it works the way you designed it. In this lab we ve provided all of the code for a working Tic Tac Toe game with the Win and Block (two_in_row.v) and Empty (empty.v) strategies as outlined in the book, and a test bench (sim/lab1_testbench.v) for verifying correct functionality in simulation. Your job is to write a PlayAdjacentEdge module (probably called something creative like play_adjacent_edge.v) and a Select4 module and integrate them into the top-level model (tictactoe.v) as described in problem 9.8c. In addition to adding the PlayAdjacentEdge module and hooking it up, you will need to modify the top-level simulation model to test this new functionality, and verify that it works in the simulator. Once you are very sure that it is functioning as required, you will come into lab and demonstrate it running on the FPGA. You will quickly (and quite possibly painfully) learn that unless you have extensively tested a module it will not work, so plan on putting at least as much thought into how you are going to test your design as how you re going to build it. Important things to remember The majority of your time will be spent simulating your design in ModelSim to verify its functionality. (You can do this on your own computer at home if you download and install ModelSim. Please see the webpage for instructions on downloading and licenses.) Debugging your design on the actual FPGA is enormously harder and slower than in ModelSim, so try to make sure everything works before you start downloading to the FPGA. When you simulate a model you will use a testbench module which provides input to the device under test (dut) to see how it responds. In this lab the lab1_testbench.v module instantiates two instances of the TicTacToe module, one for testing (called dut) and one to play against it (called opponent).

2 The testbench is never actually run on the FPGA, so it can do things like print messages to the screen and use for-loops. A separate top-level module lab1_top.v is used for synthesizing the design for the FPGA. That top-level module hooks up the tictactoe.v module to the glue code to take input from the buttons and output to the display. 2. Getting started: Simulation in ModelSim Building the project in ModelSim To work on your project in ModelSim you first need to create a new ModelSim project, import your source files, and tell ModelSim which simulation library to use. 1. To get started download the lab 1 files (lab1.zip) from the website and uncompress them into your local directory. From here on I ll assume all your files are in the lab1_tictactoe directory. 2. Then run ModelSim (we ll be using version SE 5.7a). 3. Create a new project by choosing File->New->Project. 4. Name the project lab1 and navigate to lab1_tictactoe/sim for the Project Location. 5. Click OK. 6. When you click OK the Add items to the Project window will appear. Click on the Add Existing File icon and add empty, rarb, select3, tictactoe, two_in_array, and two_in_row. The other files are the glue code for when you run it on the FPGA, so we don t want them in the simulation. 7. Click Add Existing File again and add the lab1_tictactoe/sim/lab1_testbench.v file as well. This is the testbench file that you will use in simulation to verify functionality. 8. Click Close. You should now see all the files listed in the left side of the window with blue question marks for their status. You can view and edit them by double-clicking on them. At this point you should go through each file and familiarize yourself with what is in it. What you see here should be basically the same as what is in the book in chapter 9.4. Running the provided code Once you are familiar with the contents of the files (which is important given that you re going to be modifying them) you should simulate the whole design to see how it works. To do this you need to first compile all the files, then select the correct simulation library, then open the output windows, and finally run the simulation. 1. To get started choose Compile All from the Compile menu or click the button that looks like someone pouring sand into a box. Green text should appear on the right side as each file is compiled and all the blue question marks should change into green check marks. 2. Now choose Simulate from the Simulate menu. 3. Under the Libraries tab click Add and navigate to C:\Modeltech_5.7a\xilinx_libs\unisims_ver, but make sure you do not select anything in that directory. Then click open. This ads libraries for our FPGAs to your simulation. (For this design you don t actually need any libraries, but when you get more complicated designs you will need them to simulate special FPGA features such as memories.)

3 4. Under the Design tab expand work and select lab1_testbench. This tells ModelSim that the top-level module in your design is lab1_testbench.v. 5. Click OK. 6. Notice that the left-hand side of the ModelSim window has changed from a list of files (Project view in the bottom tab) to a hierarchical list of modules in your design (sim view). You can expand any module here to see what modules are instantiated within it. You are now ready to simulate the design, but first you should open up some windows so you can see the results. Open up the Wave window by choosing Wave from the View menu. To put signals in the Wave window open up the Signals window from the View menu. Note that the signals window shows the signals present in the design at the point selected in the main ModelSim window. For example, if you select the topr module which is one instance of the TwoInRow modules in the winx module inside the opponenet module, the signals window will only show the signals inside that module: Figure 1. Signals inside the submodule lab1_testbench.opponent.winx.topr. If you select the top-level module (lab1_testbench) you will see the signals at the top of the module: Figure 2. Signals inside the top-level module lab1_testbench.

4 This ability to dig-down into modules makes it possible to see what s going on inside a large design easily. For this lab you ll mostly want to see the signals at the top-level of the design, so click on lab1_testbench in the main ModelSim window, then select and drag all the signals from the signals window to the waves window. Now when you run the simulation you ll see the values of those signals over time. Make sure you take a look at the top-level lab1_testbench module and understand what those signals are as you will need them when you write and test your own module! Now that you ve got your wave viewer setup it s time to run the simulation. Remember that when you run a simulation you are using a testbench to control the simulation. In this case the testbench is the top-level file lab1_testbench.v. It is setup to run a bunch of tests on the design and then stop. To run through the whole testbench until the stop choose Simulate->Run-Run All, click the Run All button, or type run all into the main ModelSim window. You can also use the regular Run command to specify how long to run if your testbench does not limit the time itself. As the simulation runs the testbench uses the $display() command to print out messages to the ModelSim window. Remember that since the testbench is only used for simulation it can include commands like $display() or loops. At this point you should make sure you understand the output you re seeing and how it relates to the testbench. If you need more help with ModelSim please take a look at the tutorial on the class webpage. Your job: extending TicTacToe Now that you ve got your simulation environment all set and you understand how the original design works, it s time for you to extend it. What you need to do consists basically of: 1. Add a new PlayAdjacentEdge module that meets the specifications of problem 9.8c. 2. Change the Select3 module to a Select4 module capable of prioritizing amongst 4 inputs. 3. Integrate the new modules into the TicTacToe module. (We ve even specified where you should do this.) 4. Update the testbench to verify the functionality of your module. Please remember that verifying your module s functionality is the most important part of this whole process. For a small design like this it isn t so difficult to do, but as your designs become larger you will find that the more time you spend testing the easier everything goes! 3. Finishing up: Synthesis with Xilinx ISE The final part of the lab is to synthesize your Verilog into the.bit file that you will download to the FPGA to run your design on the actual hardware. The.bit file contains all the configuration information required to setup the FPGA to implement the circuits you designed. Because FPGAs are hard to program, generating a.bit file takes several minutes, so try to spend more time in ModelSim than you do in the Xilinx software!

5 Opening the project in Xilinx ISE The Xilinx projects contain a lot of specific information about the FPGA we are using and how it should be configured, so we ve provided you with a project file for this lab. To generate a.bit file you should first run the Xilinx ISE 7.1i Project Navigator and then choose Open Project from the file menu. Select the lab1_tictactoe/ise/lab1 project. Once the project is open you will see the design hierarchy in the upper left: And the process list in the middle left: Generating your.bit file The process list will change depending on which part of the design you select in the Sources list. To generate a.bit file you need to select the top-level portion of the project lab1_top and double-click on Generate Programming File at the bottom of the Processes list or right-click on it and choose Rerun All. Note that for the actual implementation the top-level file is lab1_top.v and not the testbench lab1_testbench.v as it was in ModelSim! This is a very important distinction that you should try to get clear as soon as possible. The lab1_top.v file instantiates instances of the same TicTacToe module (from the same tictactoe.v file) as the lab1_top.v file, but only one of them can be synthesized to run on hardware. Remember that the lab1_testbench.v file has $display() statements in it and loops. If you were to put those in the top-level file you re using for synthesis

6 the tools would complain that your design was unsynthesizable (if you re lucky) or give you something very strange and hard to debug (if you re not). For this lab there is a lot of glue code in connected to the TicTacToe modules in the synthesizable top-level module. There s also a user constraints file called lab1_top.ucf which defines all the wire connections to the outside world and their timing requirements. You don t need to pay any attention to this code for the prelab, but it s important to realize that we do have to define the external interface in order to make it do anything! (This real-world external interface is what the ModelSim testbench emulates, but it can do so much more carefully than we can ever press a button ourselves.) Creating the.bit file will take 4 or 5 minutes and spit out lots of information to the console tab in ISE. You should make sure that if any warnings are generated that you look at them and know what they are. For this lab if they are in your code you should be concerned, but if they are in one of the glue modules don t worry about it. If you encounter errors read the message and try to fix them. If you really can t understand the error see the TAs for help. Most of the time the errors are due to syntax errors in your glue code (all the others should have been caught in ModelSim) or missing files. If the design just won t compile try choosing Project->Cleanup Project Files to get rid of any old temporary files and try again. 4. Submissions and lab day Submissions Your prelab is due on Monday, October 5PM. You should submit these materials electronically to your Z:\submit folder: 1. Verilog code of the modified TicTacToe module, your new strategy module, the Select4 module, and your modified testbench 2. ModelSim simulation diagrams of your extended game as well as its display outputs. These must be annotated with text to point out where your new module is being tested and how the displayed results match what you expect. 3. A brief descriptions explaining: o How you developed your design and how it is structured. o The strategy you used to verify your design in the testbench and what modifications you made. o Whether you encountered any problems during the design and if you understood them. You can put all this into a PDF file, but if you do please also submit the original Verilog files for the extended game as well. All of your submitted files should be saved electronically to your Z:\submit folder (if one doesn t exist already, create one). You must log into a Packard 128 computer using the username and password we gave you in Lab 0 to access the Z:\ drive.

7 Programming the FPGA To program the FPGA you need to run Xilinx ISE as described above and create a.bit file. Once you have done this double-click on the Analyze Design Using Chipscope Process. Later on in the quarter you will use Chipscope extensively to peer into your design while it is running, but for now we re just going to use it to download your.bit file to the FGPA. You may get a firewall warning when you startup Chipscope. You can ignore this. Turn on the FPGA board using the red switch near the power cable. A bunch of pretty green and red LEDs should turn on and some may even blink if you re really nice. In Chipscope click on the Open Cable/Search JTAG icon in the upper-left corner. After a few seconds Chipscope should find the board and pop up a window listing three devices. The bottom one is our FPGA, but we don t care about this window so just click OK. Now to download your.bit file right-click on the DEV:2 MyDevice2 (XC2VP30) device and choose Configure. (If there isn t a device that matches that name, choose the one that has XC2VP30 in it as that is the part number of the FPGA.) Click on Select New File and choose the lab1_tictactoe/lab1_top.bit file and click OK. You will see a progress bar in the lower right as your design is downloaded to the board. As soon as it finishes the FPGA has been configured for your design and is running. Verifying functionality Now that your design is running on the FPGA you can try it out by flipping the monitor switch over to the B setting. You should see a screen like the following:

8 To test your design you use the 8 switches on the Digilab Digital I/O 4 board attached to the FPGA board to choose which location you want to have an X or an O and then press the LEFT button or the RIGHT button on the FPGA to load that combination in as Xs or Os, respectively. (The combination you have selected on the switches is stored into a memory on the FPGA when you press the button so you can first load positions for X and then for Os to get any board combination.) Unfortunately we only have 8 switches and we need 9 bits of input, so you have to hold down BTN1 (to the left of SW8) to get the 9th bit. If you enter invalid bits or your design is broken you will see a red C in a given square. Now that you ve got your design working you need to verify that your new strategy behaves as expected and show the TA. You must also answer the following questions as part of your lab assignment to be turned in to the TA: 1. What is the maximum delay through your circuit? 2. What fraction of the resources (in terms of LUTs, or look up tables) did your implementation consume? (hint: this and #1 can be found in the place and route report generated when you generate your.bit file.) 3. Look at the floor planner and get an idea of what you actually built. 4. Take a look at the VGA module and figure out how it draws characters at different locations on the screen. 5. Explain the difference between synthesizable and non-synthesizable code. 6. Include any comments about this lab so we can make it better in the future.