FPGA Lecture for LUPO and GTO Vol , 31 August (revised 2013, 19 November) H. Baba
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1 FPGA Lecture for LUPO and GTO Vol , 31 August (revised 2013, 19 November) H. Baba
2 Contents Basic feature of FPGA Basic usage for LUPO New project Read and Write Basic behavioral VHDL simulation Download firmware
3 What is FPGA? Field Programmable Gate Array CLB CLB CLB DCM IOB External IO CLB CLB CLB Clock Manager SRAM Wiring Switch CLB CLB CLB Logic Unit Internal RAM
4 CLB and wiring CLB LUT In Out DFF Clock
5 About LUPO NIM signals are converted to LVTTL NIM->LVTTL->FPGA FPGA->LVTTL->NIM LVDS ports are direct connection Because of this IOB is 2.5V, this port can be accept 2.5V IO signals 8LED 4NIM IN 16 LVDS IO 32 LVTTL IO 4NIM OUT VME Interface (CPLD) User FPGA (Spartan 3E)
6 New Project for LUPO Device and Design flow
7 Design property for GTO
8 The definition of IO (LUPO) LED : LED A : CAMAC/VME address CLOCK : 50MHz clock INIT : CAMAC Z/C, VME Init? IP : NIM Input 0-3 IP0 : IP0 to GCLK OP : NIM Output 0-3 LVDSn/LVDSp : LVDS IO 0-15 LVDS_CLKn/p : LVDS0 to GCLK RD : Data Read WR : Data Write RD_STRB : Read strobe WR_STRB : Write strobe
9 Copy the Constraint file (UCF) vlupo.ucf gto.ucf Write constraints for IO and others Association = should be Implementation
10 Without CAMAC/VME Buses (LUPO) This is enough Edit vlupo.ucf by Edit Constraints(Text) NETs written in UCF are must be written in entity also
11 Simple case (LUPO) Like this If Synthesize -> Implement Design are passed, it will work
12 To make the synchronous circuit When you use if, else, you should put values into all signals explicitly Check Warning In this case, created circuit will be asynchronous circuit Should write values in else explicitly
13 This type works well, usually By using event process, DFF will be used, and values are kept as you had expected Values are changed at the Clock timing
14 Basically, all lines run in parallel IP(0) e d
15 Be careful about the loop circuit As this schematic, you can make the Latch circuit, but... Warnings of Combinational loop It will not work, depending on the pulse width, line delay, jitter and so on
16 Expressly using FF is safe event in the process statement makes DFF, basically As a circuit component, if you use FDCE(=DFF), it will work as you expected
17 Accessing VME/CAMAC buses(read for LUPO) Latch data during RD_STRB = 1
18 Accessing VME/CAMAC buses (for LUPO) Data are read from WD at the transition timing of WE_STRB 1 to 0
19 Example of data readout (LUPO) By using when statement, VME Address (CAMAC AF) is selected During RD_STRB= 1, data must be latched on RD RD <= val; Other cases, RD is unconnected RD <= (others => z ); elsif (WR_STRB = 1 ) then
20 Example of data write (LUPO) 1. Set a flag at WR_STRB= 1 set <= 1 ; 2. At WR_STRB event and WR_STRB= 0 timing, if flag is 1, set values val <= WR; 3. When WR_STRB= 0, value of set shold be kept set <= set; set is connected to CE (clock enable) of DFF WR set WR_STRB elsif (WR_STRB = 1 ) then val
21 Make a scaler (counter) By using event, make a synchronous circuit cnt <= cnt + 1 When data readout, data must be latched at the RD_STRB, otherwise you get invalid values, sometimes If cnt value is changed during readout, it is bad There are skew (- 20ps) between all bits
22 Latching the value of Scaler (Counter) Prepare the vector for readout It is not iq <= cnt; If you this, you get value of cnt - 1
23 Declare usuful libraries library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; cnt <= cnt + 1 requires ARITH If you simulate with built in libraries such as FDCE, you have to uncomment like this
24 Do simulation Create the Test Bench
25 Set initial values Implementation Simulation Switch
26 Write like this clock part are generated automatically wait for 100ns; means 100ns passing ダブルクリックでシミュレーション開始
27 ISim Expand Run 1 step
28 Download firmware to LUPO/GTO Generate Programming File bit file is generated Configure Target Device Launch impact Make file for the flash memory from bit file Load into FPGA First step, PROM = Flash Memory file
29 Setting of PROM file GTO case, it is xcf02s Choose xcf04s and Add Choose Xilinx Flash/PROM and press
![] -> Yes 2.](/docs-images/74/70708316/images/30-1.jpg "Select bit file 3.")
30 Generate PROM file By the wizard 1. [add a device?] -> Yes 2. Select bit file 3. [any other device?] -> No By double click, file (***.mcs) will be generated
31 Download firmware For FPGA, cleared by power cycle (bit file) For Flash ROM, non-volatile (mcs file) Load FPGA option is useful, FPGA will be reconfigured when Flash ROM is updated
32 Ex. mistake case, conv_std_logic_vector Converting to the numerical value of to the 24bits vector conv_std_logic_vector( , 24) Good conv_std_logic_vector(24, ) Converting the numerical value of 24 to the bits vector Synthesize take so long time
33 downto and to signal a : std_logic_vector(3 downto 0) := 3210 Using vector, downto is usual Writing initial value with bit, it is common that the most right position is 0-th bit type ARINT is array(3 downto 0) of integer; constant b : ARINT := (0,1,2,3); It will be b(0)=3, b(1)=2, b(2)=1,b(3)=0 type ARINT is array(0 to 3) of integer; constant b : ARINT := (0,1,2,3); b(0)=0, b(1)=1, b(2)=2,b(3)=3 Depending on custom,,, when array, to is easier to understand
34 If you find a warning of black box attribute box_type : string; attribute box_type of FDCE : component is black_box ; Warning will be solved Or, you don t need to declare COMPONENT that are defined in Xilinx Library, simply uncomment these lines
35 Using LVDS IBUFDS Input OBUFDS Output For input case, write DIFF_TERM = TRUE Terminator is installed
36 GCLK and BUFG Inputs assigned to GCLK can be used as a Clock (having small Skew and Delay) IP0 and LVDSClockp/n By connecting BUFG, other inputs are also can be used as a Clock (it will be the Clock of many other circuit components) Basically, it is automatically connected at the Place & Route Following declaration is necessary in UCF With larger circuit, please check Place & Route Report In case of Local (not BUFGMUX) and Skew is large, the wiring tuning with PlanAhead is necessary
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