Design Problem 3 Solutions

Transcription

1 CSE 260 Digital Computers: Organization and Logical Design Jon Turner Design Problem 3 Solutions In this problem, you are to design, simulate and implement a sequential pattern spotter, using VHDL. This circuit compares an input bit vector against a four bit pattern, where the pattern can specify a 0, 1 or don t care in each of the four positions. Whenever the circuit detects four bits in the input that match the pattern, it raises the output high. Note the pattern may appear at overlapping positions in the input string, in which case, the circuit should detect all occurrences. So for example, if the pattern is 0xx1 and the input bit sequence is , the output bit sequence should be Implement the pattern spotter as a VHDL module called seqpatternspotter, with a clock input, clk, a reset input, a single bit data input, din, a data valid input, valid, and a pattern input, pattern (please use exactly these names). Valid is used by the client circuit to indicate those clock ticks during which there is a new data bit present on din. Your circuit should ignore input bits during clock ticks when valid is low. Equipping the circuit with a valid bit allows it to be used in the S3 board (we ll get to this later). Pattern is an eight bit value, which you are to interpret as four pattern specifications, which are each compared against an input bit. There is a single synchronous output, matchout, which should go high following each rising clock edge when valid is high and the last bit of a matching pattern is detected and matchout should go low following each rising clock edge when valid is high and the input bit does not result in a match of the pattern. Whenever valid is low while matchout should not change. For the first part of the problem, create a project containing just seqpatternspotter and perform a functional simulation to verify its correctness. Your design notes should include a discussion of the state that your circuit keeps track of, a block diagram, and a brief explanation of how the state is maintained and how it is used to generate the output. Your notes should also include a discussion of your test strategy for the circuit. In addition, print out the Device Utilization Summary from the synthesis report produced by the tools, and the timing analysis section. Does the number of LUTs and flip flops reported match what you expect? Justify your answer. How many logic levels are reported in the clock period analysis? What is the resulting maximum clock frequency? Make sure you turn in a copy of your VHDL and the functional simulation output showing that your circuit works correctly (with appropriate notes). For the second part of the problem, you are to embed seqpatternspotter within a larger circuit that can be used on the S3 board. Define an entity-architecture pair called top that has inputs for the switches (swt(7..0)), the push buttons (btn(3..0)), a clock (mclk) and the LEDs (led(7..0)). We won t use the seven segment display on this problem. Use structural VHDL to define an instance of your seqpatternspotter component within the architecture of top and connect mclk to its clk input, the switches to its pattern input and its output signal to led(0). We ll use push buttons for the reset input, the din input and the valid input

2 However, to use the push buttons in this circuit, we first need to debounce the buttons. Mechanical push buttons vibrate when pressed, causing them to make many momentary contacts when we press or release them. If we want to use a button push to be interpreted as a single event, we need to filter out all these transient connections and disconnections. That s what debouncing does. You will find a VHDL module that implements a debouncing circuit on the web site. This module connects to the push buttons and provides debounced versions of the buttons (dbtn(3..0)). Instantiate the debouncing module in your circuit and use the debounced signals it provides for reset, din and valid. In particular, use dbtn(3) for reset, use dbtn(0) for din and use dbtn(1) for valid. When you study the VHDL code for debounce, you will notice that it makes use of a constant called operationmode, which you should define in a package along with other constants that you may want to use in your project. The value of operationmode controls the time period used for debouncing the input switches. Normally, operationmode is set to 1, causing the debouncing period to be one million clock ticks (which equals 20 ms). However, when simulating the circuit, we don t really want to wait for the full debouncing period. Therefore, when synthesizing your circuit in preparation for synthesis, make operationmode equal to 0. There is one additional thing you will need to do in your top circuit. Since it s not possible for us to press the push button controlling valid for just one clock tick at a time, we need to add a small circuit that converts each press of the valid button into a one clock tick pulse. Specifically, when this circuit sees dbtn(1) go from 0 to 1, it should generate a single pulse on the valid signal, allowing us to input a single data bit into seqpatternspotter for each press of valid. The final part of the problem is to implement your design on one of the S3 boards in the Urbauer lab. You may use the same user constraints file you used in design problem 2. Once you have your design on the S3 board, verify that it works as expected by trying a few different patterns and supplying input strings that match them. When you are satisfied, have one of the TAs come into the lab and check it. Be sure to the file containing your VHDL code (please send it as a single file) as an attachment to jon.turner@wustl.edu. Please name your attachment dp3-yourname.vhd, where yourname is your first and last names (e.g. jonturner). Also, a copy of your MCS file, as a second attachment. Note that the last page of this handout is a grading template for the design problem. This should stapled to the front of the assignment when you turn it in, with your name filled in the blank space. When you demonstrate the running design to the TA, make sure he assigns a score and signs in the comment space

3 Design notes for Sequential Pattern Spotter. This circuit implements a sequential pattern matcher. The sequential input stream is compared against a four bit pattern, and the synchronous output matchout is high following each clock tick when a matching pattern is detected. The pattern includes don t cares, so there are eight pattern bits allowing us to encode the three options (01 to match an input 0, 10 to match an input 1 and 11 to match either one). The data input is ignored during all clock ticks when the valid input is low. The first thing to decide is what information the circuit needs to remember. One possible choice is to remember the last few bits we have seen. However, since when the circuit first starts operating, no input bits have been seen yet, we need to be a little careful to avoid false matches in these first few bit times. One way to address this problem is to store the last few bits in encoded form in a history vector. The history vector can have two bits for each actual data bit, using 01 to represent a 0, 10 to represent a 1 and 00 to represent nothing. If we initialize the history vector to 0, we can then keep it up-to-date by shifting it to the left two bit positions and inserting a new bit pair into the low order bits. Representing the history in this way also leads to simple logic for detecting a match against the pattern. This approach leads to the block diagram shown below. Note that the block diagram does not show the valid input. The shifting of the history and the generation of the output are only enabled when valid is high. din history matchout pattern Given the structure of the circuit, a fairly simple testing strategy is sufficient. We need to make sure that each of the history bit pairs can hold any value and that the matching circuitry works correctly. Given the regularity of the circuit, it suffices to use a single pattern that includes all the allowed values 01, 10 and 11. The input bits should include portions that match the don t care bits of the pattern using either a 0 or a

4 VHDL Source Code. Stand-alone version of circuit. Sequential Pattern Spotter Jon Turner - 1/9/2007 This circuit looks for an n bit pattern in an input string. It raises its output high whenever the previous n bits matches the pattern. The pattern to be matched can include zeros, ones or wildcards. - library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; package commondefs is constant patlength: integer := 4; end package commondefs; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.commondefs.all; entity seqpatternspotter is port( clk, reset: in std_logic; din: in std_logic; input data bit valid: in std_logic; high on clock ticks where new data bit on din pattern: in std_logic_vector(2*patlength-1 downto 0); pattern to match against input stream matchout: out std_logic high whenever end of a pattern is seen ); end seqpatternspotter; architecture spsarch of seqpatternspotter is history(2i+1,2i) represent i-th previous input bit 01 stands for input 0, 10 stands for input 1, 00 stands for no valid input bit signal history: std_logic_vector(2*patlength-1 downto 2); pmatch(i)=1 if current input bit plus previous i bits match pattern signal pmatch: std_logic_vector(patlength-1 downto 0); begin process(clk, pattern, history, din, pmatch) begin compare history and din against pattern if din = '0' then pmatch(0) <= pattern(0); else pmatch(0) <= pattern(1); for i in 1 to patlength-1 loop if (history(2*i+1) = '1' and pattern(2*i+1) = '1') or (history(2*i) = '1' and pattern(2*i) = '1') then pmatch(i) <= pmatch(i-1); else pmatch(i) <= '0'; end loop; update history and generate output if rising_edge(clk) then if reset = '1' then matchout <= '0'; - 4 -

5 history <= (history'range => '0'); elsif valid = '1' then history(2*patlength-1 downto 4) <= history(2*patlength-3 downto 2); if din = '0' then history(3 downto 2) <= "01"; else history(3 downto 2) <= "10"; matchout <= pmatch(patlength-1); end process; end spsarch; - 5 -

6 Simulation of Stand-alone Version of Circuit. The simulation result is shown below. Note that the input values are correctly encoded and propagated through the history vector. Also, note that when valid is low, the input is ignored and no output is generated. Finally, note that the matching logic correctly matches the 0 case, the 1 case and the don t care case. pattern 0xx1 no change to history when valid=0 updating history when valid=1 match on 0001 and on 0011 matchout stable when valid=0 match on

7 Synthesis Report. We expect this design to use seven flip flops, since the history information requires six and since the synchronous output matchout requires one more. We also expect six LUTs. Each of the AND-OR groupings requires one LUT, anding these together to produce matchout requires a fifth and we need one more to generate the complement of din. The device utilization section of the simulation report is shown below. It confirms the estimate for flip flops but reports one more LUT. ========================================================================= Device utilization summary: - Selected Device : 3s200ft256-5 Number of Slices: 4 out of % Number of Slice Flip Flops: 7 out of % Number of 4 input LUTs: 7 out of % Number of IOs: 13 Number of bonded IOBs: 13 out of 173 7% Number of GCLKs: 1 out of 8 12% The timing report section of the synthesis report appears below. It reports a maximum clock frequency of 302MHz, based on a worst-case delay between flip flops of 3.3 ns. This delay is based on the fact that the worst-case flip flop to flip flop path has two LUTs. This matches what we would expect based on the block diagram of the circuit. The path from each of the history flip flops to the matchout flip flop will have two LUTs. ========================================================================= Timing constraint: Default period analysis for Clock 'clk' Clock period: 3.304ns (frequency: MHz) Total number of paths / destination ports: 10 / 5 - Delay: 3.304ns (Levels of Logic = 2) Source: history_5 (FF) Destination: matchout (FF) Source Clock: clk rising Destination Clock: clk rising Data Path: history_5 to matchout Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) FDRE:C->Q history_5 (history_5) LUT4:I2->O _mux (_mux0009_map25) LUT4:I2->O _mux (pmatch<3>) FDR:D matchout Total 3.304ns (1.760ns logic, 1.544ns route) (53.3% logic, 46.7% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Total number of paths / destination ports: 25 / 16 - Offset: 3.968ns (Levels of Logic = 2) Source: valid (PAD) Destination: matchout (FF) Destination Clock: clk rising Data Path: valid to matchout Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) IBUF:I->O valid_ibuf (valid_ibuf) - 7 -

8 LUT2:I0->O _or00001 (_or0000) FDR:R matchout Total 3.968ns (2.086ns logic, 1.882ns route) (52.6% logic, 47.4% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Total number of paths / destination ports: 1 / 1 - Offset: 6.216ns (Levels of Logic = 1) Source: matchout (FF) Destination: matchout (PAD) Source Clock: clk rising Data Path: matchout to matchout Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) FDR:C->Q matchout (matchout_obuf) OBUF:I->O matchout_obuf (matchout) Total 6.216ns (5.535ns logic, 0.681ns route) (89.0% logic, 11.0% route) - 8 -

9 Design notes for S3 version. This circuit embeds the sequential pattern spotter in a circuit suitable for use on the S3 board. To use the push buttons on the S3 board, we need to use a debouncing module, so the top module of this circuit instantiates seqpatternspotter and debounce and wires them to each other and to the external pins. The top module also includes circuitry to convert a push of btn(1) into a one clock tick pulse that can be connected to the valid input of seqpatternspotter. The block diagram at right shows how the components are used and connected to the external signals. btn debouncer dbtn(3) dbtn(0) dbtn(1) D >C mclk To test the circuit we need to verify that the various signals reach seqpatternspotter as expected and that the overall behavior is correct. Using the simulator to allow us to examine the internal signals, we ll verify that the external signals reach seqpatternspotter as expected. In particular, we ll check that the switches control the pattern input, that the reset and din signals respond to the button pushes as expected, and that the valid signal is generated correctly. Then, we ll verify that seqpatternspotter can detect an input pattern correctly. swt pattern reset din valid seqpatternspotter matchout clk led(0) - 9 -

10 VHDL for S3 version. Sequential Pattern Spotter Jon Turner - 1/9/2007 This circuit looks for an n bit pattern in an input string. It raises its output high whenever the previous n bits matches the pattern. The pattern to be matched can include zeros, ones or wildcards. On the S3 board, the pattern matches four bits and is specified using the switches. More details below - library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.commondefs.all; entity seqpatternspotter is port( clk, reset: in std_logic; din: in std_logic; input data bit valid: in std_logic; high on clock ticks where new data bit on din pattern: in std_logic_vector(2*patlength-1 downto 0); pattern to match against input stream matchout: out std_logic high whenever end of a pattern is seen ); end seqpatternspotter; architecture spsarch of seqpatternspotter is history(2i+1,2i) represent i-th previous input bit signal history: std_logic_vector(2*patlength-1 downto 2); pmatch(i)=1 if current input bit plus previous i bits match pattern signal pmatch: std_logic_vector(patlength-1 downto 0); begin process(clk, pattern, history, din, pmatch) begin compare history and din against pattern if din = '0' then pmatch(0) <= pattern(0); else pmatch(0) <= pattern(1); for i in 1 to patlength-1 loop if (history(2*i+1) = '1' and pattern(2*i+1) = '1') or (history(2*i) = '1' and pattern(2*i) = '1') then pmatch(i) <= pmatch(i-1); else pmatch(i) <= '0'; end loop; update history and generate output if rising_edge(clk) then if reset = '1' then matchout <= '0'; history <= (history'range => '0'); elsif valid = '1' then history(2*patlength-1 downto 4) <= history(2*patlength-3 downto 2); if din = '0' then history(3 downto 2) <= "01"; else history(3 downto 2) <= "10";

11 matchout <= pmatch(patlength-1); end process; end spsarch; - Debouncer Synchronize and de-bounce the push buttons. dbtn is de-bounced version of btn. To use this module, connect the push buttons on the S3 board to the btn input. For all uses of the buttons by the circuit, use dbtn(i) in place of btn(i). Note that when running on the S3 board, the time period for debouncing is 20 ms or 1 million clock cycles. When simulating the circuit, you need to reduce this to just a few clock ticks, to keep the simulation of reasonable length. The easy way to do this is to change the operationmode constant (defined in commondefs.vhd) to 0. Make sure you change it back to 1 when synthesizing for the S3 board. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use work.commondefs.all; entity debouncer is port( clk: in std_logic; btn: in std_logic_vector(nbtn-1 downto 0); dbtn: out std_logic_vector(nbtn-1 downto 0) ); end debouncer; architecture debarch of debouncer is constant debounceperiod: integer := 3 + operationmode*999997; signal s1btn, s2btn, s3btn: std_logic_vector(nbtn-1 downto 0); signal count: std_logic_vector(31 downto 0); begin process(clk) begin if rising_edge(clk) then first synchronize buttons to reduce likelihood of synchronizer failure s1btn <= btn; s2btn <= s1btn; s3btn <= s2btn; transfer new value to dbtn after it has been stable for duration of the de-bounce period if s3btn /= s2btn then count <= (count'range => '0'); elsif count < debounceperiod then count <= count + 1; elsif count = debounceperiod then dbtn <= s3btn; count <= count + 1; end process; end debarch;

12 Top embeds seqpatternspotter in the S3 board and uses debounced versions of the buttons. The pattern is presented on the switches. The buttons are used for several different purposes. Specifically, btn(3) is the reset button btn(0) is used to specify the next input bit btn(1) is used to indicate the presence of a new input bit in particular, when btn(1) is pressed, the value on btn(0) is input to the pattern spotter circuit btn(2) is not used - library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use work.commondefs.all; entity top is port( mclk: in STD_LOGIC; btn: in std_logic_vector(nbtn-1 downto 0); swt : in std_logic_vector(nswt-1 downto 0); led : out std_logic_vector(nled-1 downto 0); an: out std_logic_vector(ndig-1 downto 0) ); end top; architecture toparch of top is component seqpatternspotter port( clk, reset: in std_logic; din: in std_logic; valid: in std_logic; pattern: in std_logic_vector(2*patlength-1 downto 0); matchout: out std_logic ); end component; component debouncer port( clk: in std_logic; btn: in std_logic_vector(nbtn-1 downto 0); dbtn: out std_logic_vector(nbtn-1 downto 0) ); end component; signal reset: STD_LOGIC; signal dbtn: std_logic_vector(nbtn-1 downto 0); signal prevbtn1: std_logic; signal din, valid, result: std_logic; begin Process for converting 01 transition on btn(1) to a valid signal lasting for one clock tick. Also, associate switches with pat. process (mclk, prevbtn1, dbtn) begin if rising_edge(mclk) then prevbtn1 <= dbtn(1); valid <= (not prevbtn1) and dbtn(1);

13 end process; reset <= dbtn(3); din <= dbtn(0); debc: debouncer port map(mclk, btn, dbtn); spsc: seqpatternspotter port map(mclk, reset, din, valid, swt, result); led(0) <= result; an <= "1111"; end toparch;

14 Simulation Results for S3 Version. The simulation output below shows the results for the version configured for the S3 board. The first section shows that reset is asserted after btn(3) is pressed. Notice that dbtn(3) changes six clock ticks after btn(3). This first section also demonstrates that the external switches control the internal pattern signal. The next section shows that the valid pulse is generated in response to a button push on btn(1), that din follows btn(0) and that the history signal correctly stores the last few input bits. In the final section, we see the specified pattern being detected and the signals controlling the LEDs being properly asserted. btn(3) press makes dbtn(3) go high after 6 ticks, which asserts reset verify that pattern controlled by switches correct generation of valid pulse history correctly tracking valid input bits spotting pattern and turning on led