Declarations. Lexical elements. Type declaration Subtype declaration Constant declaration Signal declaration Variable declaration.
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1 Lexical elements Declarations Reserved words Type declaration Subtype declaration Constant declaration Signal declaration Variable declaration page 1 page 3
2 Type declaration Reserved words architecture a of e is package p is end a; end p; in the STD.STANDARD package: type boolean is (false, true); type bit is ('0', '1'); type character is (NUL, SOH, <...> '}', '~', DEL); type string is array(positive range <>) of character; type bit_vector is array(natural range <>) of bit; in the IEEE.STD_LOGIC_1164 package: type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'); type std_ulogic_vector is array(natural range <>) of std_ulogic; in the IEEE.NUMERIC_STD package: type unsigned is array(natural range <>) of std_logic; type signed is array(natural range <>) of std_logic; abs access after alias all and architecture array assert attribute block body buffer bus case component configuration constant disconnect downto elsif end entity exit file for function generate generic group guarded if impure in inertial inout is label library linkage literal loop map mod nand new next nor not null of on open or others out package port procedure process pure range record register reject rem report return rol ror select severity shared signal sla sll sra srl subtype then to transport type unaffected units until use variable wait when while with xnor xor page 4 page 2
3 Subtype declaration Signal declaration architecture a of e is package p is architecture a of e is end a; end p; end a; in the STD.STANDARD package: subtype natural is integer range 0 to integer'high; subtype positive is integer range 1 to integer'high; signal s1, s2, s3: std_ulogic; signal sig1: std_ulogic; signal sig2: std_ulogic; signal sig3: std_ulogic; in the IEEE.STD_LOGIC_1164 package: subtype std_logic is resolved std_ulogic; subtype X01 is resolved std_ulogic range 'X' to '1'; subtype X01Z is resolved std_ulogic range 'X' to 'Z'; subtype UX01 is resolved std_ulogic range 'U' to '1'; subtype UX01Z is resolved std_ulogic range 'U' to 'Z'; signal logic_out: std_ulogic; signal open_drain_out: std_logic; signal tri_state_out: std_logic; subtype byte is std_ulogic_vector(7 downto 0); subtype word is std_ulogic_vector(15 downto 0); subtype long_word is std_ulogic_vector(31 downto 0); signal counter: unsigned(nb_bits-1 downto 0); signal double: unsigned(2*nb_bits-1 downto 0); signal sine: signed(nb_bits-1 downto 0); subtype BCD_digit is unsigned(3 downto 0); subtype my_counter_type is unsigned(9 downto 0); subtype sine_wave_type is signed(15 downto 0); signal clock_internal: std_ulogic := '1'; page 5 page 7
4 Variable declaration Constant declaration p: process (s_list) architecture a of e is package p is end process p; end a; end p; constant bit_nb: positive := 4; constant min_value: positive := 0; constant max_value: positive := 2**bit_nb - 1; variable v1, v2, v3: std_ulogic; variable var1: std_ulogic; variable var2: std_ulogic; variable var3: std_ulogic; constant bit_nb: positive := 4; constant patt1: unsigned(bit_nb-1 downto 0) := "0101"; constant patt2: unsigned(bit_nb-1 downto 0) := "1010"; variable counter: unsigned(nb_bits-1 downto 0); variable double: unsigned(2*nb_bits-1 downto 0); variable sine: signed(nb_bits-1 downto 0); constant address_nb: positive := 4; constant data_register_address : positive := 0; constant control_register_address : positive := 1; constant interrupt_register_address: positive := 2; constant status_register_address : positive := 3; constant clock_period: time := 5 ns; constant access_time: time := 2 us; constant duty_cycle: time := 33.3 ms; constant reaction_time: time := 4 sec; constant teaching_period: time := 45 min; page 8 page 6
5 Process statement Concurrent statements architecture a of e is end a; Signal assignment Process statement When statement With statement mux: process(sel, x0, x1) if sel = '0' then y <= x0; elsif sel = '1' then y <= x1; y <= 'X'; end process mux; count: process(reset, clock) if reset = '1' then counter <= (others => '0'); elsif rising_edge(clock) then counter <= counter + 1; end process count; page 9 page 11
6 When statement Signal assignment architecture a of e is architecture a of e is end a; end a; y1 <= a; y2 <= a and b; y3 <= to_integer(a); y <= x0 when sel = '0' x1 when sel = '1' 'X'; y <= " "; y <= "0000" & "0011"; y <= ('0', '0','0', '0','0', '0', '1', '1'); y <= (7 downto 2 => '0', 1 0 => '1'); y <= (7 downto 2 => '0', others => '1'); y1 <= a; y2 <= a after 2 ns; y3 <= inertial a after 1 ns; y4 <= transport a after 4 ns; y5 <= reject 1 ns inertial a after 5 ns; y <= x0 after 2 ns when sel = '0' x1 after 3 ns when sel = '1'; y <= a and b after 5 ns; y <= '0', '1' after 2 ns, '0' after 4 ns, 'X' after 10 ns, '1' after 15 ns, '-' after 23 ns; page 12 page 10
7 With statement architecture a of e is end a; Sequential statements mux: with sel select y <= x0 when "00", x1 when "01", x2 when "10", x3 when "11", 'X' when others; Variable assignment If statement Case statement Loop statement decoder: with binary_code select y <= transport "0001" after 2 ns when "00", "0010" after 5 ns when "01", "0100" after 3 ns when "10", "1000" after 4 ns when "11", "XXXX" when others; page 13 page 15
8 Variable assignment p: process (s_list) end process p; y1 := a; y2 := a and b; y3 := to_integer(a); page 16 page 14
9 If statement Loop statement p: process (s_list) p: process (s_list) end process p; end process p; if gate = '1' then q <= d; if sel = '0' then y <= x0; y <= x1; if sel = '0' then y1 <= x0; y2 <= x1; y3 <= '0'; y1 <= x1; y2 <= x0; y3 <= '1'; for xindex in 1 to xsize loop for yindex in 1 to ysize loop if xindex = yindex then y(xindex, yindex) <= '1'; y(xindex, yindex) <= '0'; end loop; end loop; if sel = 0 then y <= x0; elsif sel = 1 then y <= x1; elsif sel = 2 then y <= x2; y <= x3; if (a = '0') and (b = '0') then y <= '1'; y <= '0'; multipl: for indexb in 0 to nbits-1 loop partialprod: for indexa in nbits-1 downto 0 loop partprod(indexa) <= a(indexa) and b(indexb); end loop partialprod; cumsum(indexb+1) <= cumsum(indexb) + partprod; end loop multipl; page 17 page 19
10 Case statement p: process (s_list) end process p; case sel is when "00" => y <= x0; when "01" => y <= x1; when "10" => y <= x2; when "11" => y <= x3; when others => null; end case; case opcode is when add => y1 <= x0; y2 <= x1; when sub => y1 <= x1; y2 <= x0; when others => null; end case; case value is when 1 => nbits <= 1; when 2 3 => nbits <= 2; when 4 to 7 => nbits <= 3; when 8 to 15 => nbits <= 3; when others => nbits <= 0; end case; case to_integer(sel) is when 0 => y <= x0 after 1 ns; when 1 => y <= x1 after 1 ns; when 2 => y <= x2 after 1 ns; when 3 => y <= x3 after 1 ns; when others => y <= 'X'; end case; page 20 page 18
11 Arithmetic operators Operators Logic operators Arithmetic operators Comparisons Concatenation operator description + addition - substraction * multiplication / division ** power abs absolute value mod modulo rem reminder of the division sla arithmetic shift left sra arithmetic shift right maxunsigned <= 2**nBits - 1; maxsigned <= 2**(nBits-1) - 1; page 21 page 23
12 Comparisons Logic operators operator description = equal to /= not equal to < smaller than > greater than <= smaller than or equal to >= greater than or equal to operator not and or xor nand nor xnor sll srl rol ror description inversion logical AND logical OR exclusive-or NAND-function NOR-function exclusive-nor logical shift left logical shift right rotate left rotate right if counter > 0 then counter <= counter -1; y <= a and b; if counter /= 0 then counterrunning <= '1'; counterrunning <= '0'; if (a = '1') and (b = '1') then y <= '1'; y <= '0'; if (a and b) = '1' then y <= '1'; y <= '0'; count <= count sll 3; page 24 page 22
13 Concatenation & operator concatenation description Attributes address <= "1111" & "1100"; constant CLR: std_logic_vector(1 to 4) := "0000"; constant ADD: std_logic_vector(1 to 4) := "0001"; constant CMP: std_logic_vector(1 to 4) := "0010"; constant BRZ: std_logic_vector(1 to 4) := "0011"; Type related attributes Array related attributes constant R0 : std_logic_vector(1 to 2) := "00"; constant DC : std_logic_vector(1 to 2) := "--"; constant reg : std_logic := '0'; constant imm : std_logic := '1'; type ROMArrayType is array(1 to 255) of std_logic_vector(1 to 9); constant ROMArray: ROMArrayType := ( 0 => ( CLR & DC & R0 & reg ), 1 => ( ADD &"01"& R0 & imm ), 2 => ( CMP &"11"& R0 & imm ), 3 => ( BRZ & "0001" & '-' ), 4 to romarray'length-1 => (others => '0') ); page 25 page 27
14 Type related attributes attribute T base T left T right T high T low T pos(x) T val(n) T succ(x) T pred(x) T leftof(x) T rightof(x) result the base type of T the left bound of T the right bound of T the upper bound of T the lower bound of T the position number of X in T the value of position number N in T the successor of X in T the predecessor of X in T the element left of X in T the element right of X in T signal counterint: unsigned; signal count1: unsigned(counter'range); signal count2: unsigned(counter'length-1 downto 0); flip: process(count1) for index in count1'low to count1'high loop count2(index) <= count1(count1'length-index); end loop; end process flip; page 28 page 26
15 Array related attributes Wait statement attribute result A left A right A high A low A range A reverse_range A length the left bound of A the right bound of A the upper bound of A the lower bound of A the range of A the range of A in reverse order the size of the range of A type statetype is (reset, wait, go); signal state: statetype; evalnextstate: process(reset, clock) if reset = '1' then state <= statetype'left; elsif rising_edge(clock) then end process evalnextstate; p: process end process p; test: process testmode <= '0'; databyte <= " "; startsend <= '1'; wait for 4*clockPeriod; startsend <= '0'; wait for 8*clockPeriod; testmode <= '1'; databyte <= " "; startsend <= '1'; wait for 4*clockPeriod; startsend <= '0'; wait; end process test; test: process a <= '0'; b <= '0'; wait for simulstep; error <= y xor '0'; a <= '1'; b <= '1'; wait for simulstep; error <= y xor '1'; end process test; test: process playvectors: for index in stimuli range databyte <= stimuli(index); wait for clockperiod; assert codedword = expected(index); wait for clockperiod; end loop playvectors; wait; end process test; page 29 page 31
16 Assert statement p: process end process p; Simulation elements assert output = '1'; assert output = '1' report "output was '0'!"; Wait statement Assert statement assert output = '1' report "output was '0'!" severity error; in the STD.STANDARD package: type severity_level is (note, warning, error, failure); page 32 page 30
17 Index Lexical elements 1 Declarations 3 Concurrent statements 9 Sequential statements 15 Operators 21 Attributes 27 Simulation elements 29 Arithmetic operators 23 Array related attributes 29 Assert statement 31 Case statement 18 Comparisons 24 Concatenation 25 Constant declaration 6 If statement 17 Logic operators 22 Loop statement 19 Process statement 11 Reserved words 2 Type declaration 4 Type related attributes 28 Signal assignment 10 Signal declaration 7 Subtype declaration 5 Variable assignment 16 Variable declaration 8 Wait statement 30 When statement 12 With statement 13 VHDL syntax shortform Francois Corthay, HEVs, 4/25/02
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