Sintaksa VHDL jezika - podsjetnik -
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1 Sintaksa VHDL jezika - podsjetnik - -- Učitavanje biblioteka library <library_name>; -- Import all the declarations in a package use <library_name>.<package_name>.all; -- Import a specific declaration from a package use <library_name>.<package_name>.<object_name>; -- Import a specific entity from a library use <library_name>.<entity_name>; -- Import from the work library. The work library is an alias -- for the library containing the current design unit. use work.<package_name>.all; -- Često korišteni paketi: -- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions use ieee.std_logic_1164.all; -- SIGNED and UNSIGNED types, and relevant functions use ieee.numeric_std.all; -- Basic sequential functions and concurrent procedures use ieee.vital_primitives.all; -- Library of Parameterized Modules: -- customizable, device-independent logic functions use lpm.lpm_components.all; -- Altera Megafunctions use altera_mf.altera_mf_components.all;
2 -- Deklaracija entiteta entity <entity_name> is generic <name> : <type> := <name> : <type> := <default_value>; <default_value> port -- Input ports <name> : in <type>; <name> : in <type> := <default_value>; -- Inout ports <name> : inout <type>; -- Output ports <name> : out <type>; <name> : out <type> := <default_value> end <entity_name>; -- Deklaracija arhitekture architecture <arch_name> of <entity_name> is begin -- Declarations optional) -- Process Statement optional) -- Concurrent Procedure Call optional) -- Concurrent Signal Assignment optional) -- Conditional Signal Assignment optional) -- Selected Signal Assignment optional) -- Component Instantiation Statement optional) -- Generate Statement optional) end <arch_name>; -- Deklaracija paketa package <package_name> is -- Type Declaration optional) -- Subtype Declaration optional) -- Constant Declaration optional) -- Signal Declaration optional) -- Component Declaration optional) end <package_name>;
3 -- Deklaracija komponente component <component_name> generic <name> : <type>; <name> : <type> := <default_value> -- Opciono port -- Input ports <name> : in <type>; <name> : in <type> := <default_value>; -- Inout ports <name> : inout <type>; -- Output ports <name> : out <type>; <name> : out <type> := <default_value> end component;
4 -- Sintaksa IF uslova if <expression> then elsif <expression> then else ; end if; -- Sintaksa CASE uslova case <expression> is when <constant_expression> => when <constant_expression> => when others => end case; -- Sintaksa FOR petlje for <loop_id> in <range> loop end loop; -- Sintaksa WHILE petlje while <condition> loop end loop; -- Bezuslovna skok naredba next <optional_loop_label>; -- Uslovna skok naredba <optional_loop_label>: next <optional_loop_label> when <condition>; -- Uslovna dodjela vrijednosti <target> <= <value> when <condition> else <value> when <condition> else <value> when <condition> else <value>; -- Dodjela vrijednosti na osnovu jednog izraza stanja posmatranog signala) with <expression> select <target> <= <value> when <choices> <value> when <choices> <value> when <choices> <value> when others;
5 -- Kombinacioni proces process<sensitivity_list>) is -- Declarations) begin end process; -- Sekvencijalni proces processreset, clk) is -- Declarations) begin ifreset = '1') then -- Asynchronous Sequential Statements) elsifrising_edgeclk)) then -- Synchronous Sequential Statements) end if; end process; Unarni operatori: + -- positive - -- negative NOT -- negation ABS -- absolute value Binarni operatori: AND OR NAND NOR XOR XNOR = /= < <= > >= SLL -- Shift Left Logical SRL -- Shift Right Logical SLA -- Shift Left Arithmetic: same as "logical" shift but uses sign extension the leftmost bit is considered the sign bit) SRA -- Shift Right Arithmetic: same as "logical" shift but uses sign extension the rightmost bit is considered the sign bit) ROL -- Rotate Left: Same as a shift, but bits that would "fall off" the left side during a shift will reappear on the right side in a rotation. ROR -- Rotate Right + -- Addition - -- Subtraction & -- Concatenation * -- Multiplication / -- Division MOD -- Modulus: If C <= A MOD B, then A = B*N + C for some integral N), and ABSC) < ABSB). Also, C must be positive if B is positive, and C must be negative if B is negative. REM -- Remainder: If C <= A REM B, then A = A/B)*B + C, and ABSC) < ABSB). Also, C must be positive if A is positive, and C must be negative if A is negative. ** -- Exponent
6 -- Deklaracija signala signal <name> : <type>; signal <name> : <type> := <default_value>; -- Opciono -- Najčešći tipovi signala signal <name> : std_logic; signal <name> : std_logic_vector<msb_index> downto <lsb_index> signal <name> : integer; signal <name> : integer range <low> to <high>; -- Deklaracija varijable variable <name> : <type>; variable <name> : <type> := <default_value>; -- Najčešći tipovi varijabli -- Varijabli se mora dodijeliti -- vrijednost prije korištenja -- u deklaraciji ili u izrazu) variable <name> : std_logic; variable <name> : std_logic_vector<msb_index> downto <lsb_index> variable <name> : integer; variable <name> : integer range <low> to <high>; -- Deklaracija konstante constant <constant_name> : <type> := <constant_value>; -- Deklaracija osnovnog integer tipa type <name> is range <low> to <high>; type index_t is range 0 to 7; type addr_t is range 255 downto 0; -- Deklaracija tipa na osnovu jednodimenzionog niza type <name> is array<range_expr>) of <subtype_indication>; -- Deklaracija tipa na osnovu multidimenzionog niza type <name> is array<range_expr>,..) of <subtype_indication>; -- Ograničena veličina niza type byte_t is array7 downto 0) of std_logic; type mem_t is array7 downto 0) of std_logic_vector7 downto 0 -- Deklaracija nizovnog tipa "neograničene" veličine. Kod deklaracije ovog -- objekta može se definisati opseg. type vector_t is arraynatural range <>) of std_logic;
7 -- Deklaracija enumeracijskog tipa type <name> is <enum_literal>, <enum_literal>, type state_t is IDLE, READING, WRITING, DONE -- Deklaracija strukture type <name> is record <member_ids> : <subtype_indication>; end record; type packet_t is record address : integer range 0 to 256; data : std_logic_vector7 downto 0 end record;
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