wait on until ' for ECE 4514 Martin 2002 ECE 4514 Martin 2002 ECE 4514 Martin 2002 architecture begin : process begin end process;

Size: px

Start display at page:

Download "wait on until ' for ECE 4514 Martin 2002 ECE 4514 Martin 2002 ECE 4514 Martin 2002 architecture begin : process begin end process;"

Geoffrey Osborne
6 years ago
Views:

1 Last time VHDL in Actin Chapter 3 Cncurrent Statements Sequential cnstructs Lps: Fr/while Case If/then/elsif/else Prcess executin Sensitivity lists vs. wait statements Cmpund waits: wait n X,Y until ='0' fr 100 ns; 2 Cncurrent Statements Cncurrent Statements Statements which ccur within the architecture blck "Cncurrent" because all are evaluated fr executin at the same time The rder in which cncurrent statements appear is nt imprtant (t the simulatr) Prcess statements Cnditinal cncurrent signal assignment statements Selective cncurrent signal assignment statements Cncurrent assert statements 3 4 Prcess Statement Review Architecture Basics The PROCESS blck is, as a whle, a cncurrent statement As with all statements in an architecture blck, all PROCESSes within an ARCHITECTURE are cnsidered t execute in parallel. Prcesses cntain nly sequential statements. All cncurrent statements are equivalent t sme prcess statement. 5 architecture MINE f MY_ENTITY is [signal_declaratins] LABEL_1: prcess [(signal_list)] [cnstant_variable_declaratins] [sequential_statements] [ther_cncurrent_statements] end MINE; 6

2 Cncurrent Signal Cncurrent Signal The fllwing are equivalent: prcess (S1, S2) X1 <= S1 r S2; prcess X1 <= S1 r S2; wait n S1, S2; X1 <= S1 r S2; When are these statements executed? 7 [Label :] signal_name <= expressin1 [after sme_time1] [, expressin2 [after smetime2][,...]; Order desn't matter: a <= b + c; c <= d + 1; c <= d + 1; a <= b + c; A cncurrent signal assignment statement is evaluated when a signal n the righthand side changes value 8 Cnc t example: entity prt (, : in std_lgic; Cnc t example: entity prt (, : in std_lgic; architecture gate f signal,,,:std_lgic; <= nt ; end gate; architecture gate f signal,,,:std_lgic; <= nt ; end gate; 9 10 Prcess example: entity prt (, : in std_lgic; Prcess example: entity prt (, : in std_lgic; architecture h_behave f signal,,,:std_lgic; bad_idea: prcess (, ) <= nt ; end behavir; architecture h_behave f signal,,,:std_lgic; bad_idea: prcess (, ) <= nt ; end behavir; 11 12

3 Cncurrent Signal Cncurrent Cnditinal S1 <= '1' after 10 ns, '0' after 20 ns, '' after 30 ns; Time values must be ascending in time. 13 [label:] signal_name <= wave1 when cnd1 else wave2 when cnd2 else Order matters: The first true cnditinal determines the utput s value wave3 when cnd3 else waven-1 when cndn-1 else waven; 14 Cnditinal Cncurrent Assignment Equivalent Prcess Statement Fred: S1 <= A r B after 10 ns, C after 20 ns, '' after 30 ns when MODE='1' else Can A, B, Mde,... be variables? '1' after 10 ns, '0' after 20 ns, '' after 30 ns when CAR=Red else '' after 30 ns; DBUS <= REG1 when REG1SEL else REG2 when REG2SEL else REG3 when REG3SEL else REG4; When are these statements executed? 15 Fred: S1 <= A r B after 10 ns, '' after 30 ns when MODE ='1' else '1' after 10 ns, '' after 30 ns when CAR=Red else '' after 30 ns; Fred: prcess (A, B, MODE, CAR) if MODE='1' then S1 <= A r B after 10 ns, '' after 30 ns; elsif CAR=Red then S1 <= '1' after 10 ns, '' after 30 ns; else S1 <= '' after 30 ns; end if; 16 Selected Cncurrent Selected Cncurrent [Label :] with expressin select signal_name <= wave1 when chice1, wave2 when chice2, waven-1 when chicen-1, waven when thers; Chices must be mutually exclusive and must cver all pssible c values f expressin with SEL select DBUS <= INP0 when "00", INP1 when "01", INP2 when "10", INP3 when thers; 17 18

4 Equivalent Prcess Statement with SEL select DMUX <= INP0 when "00", INP1 when "01", INP2 when "10", INP3 when thers; prcess (SEL,INP0,INP1,INP2,INP3) case SEL is when "00" => DMUX <= INP0; when "01" => DMUX <= INP1; when "10" => DMUX <= INP2; when thers => DMUX <= INP3; end case; 19 Cncurrent behavir ENTITY mux4_1bit IS PORT ( i0, i1, i2, i3, a, b : IN std_lgic; z: OUT std_lgic); END mux4_1bit; ARCHITECTURE cnc OF mux4_1bit IS SIGNAL sel: INTEGER; BEGIN WITH sel SELECT <= i0 AFTER 10 ns WHEN 0, i1 AFTER 10 ns WHEN 1, i2 AFTER 10 ns WHEN 2, i3 AFTER 10 ns WHEN 3, 'X' AFTER 10 ns WHEN OTHERS; sel <= 0 WHEN a = '0' AND b = '0' ELSE 1 WHEN a = '1' AND b = '0' ELSE 2 WHEN a = '0' AND b = '1' ELSE 3 WHEN a = '1' AND b = '1' ELSE 4 ; END cnc; Des this wrk? (Frm Yalamanchili) 20 Statement Statement Methd f prducing interactive feedback during simulatin Diagnstic messages: "Errr: Bus cntentin -- put fire ut" "Warning: reset ccurred when P0 is high" statement is bth a sequential statement and a cncurrent statement. 21 [Label :] assert Blean_expressin [reprt "a message f sme srt"] [severity severity_level]; When Blean_expressin is TRUE, this is cnsidered NORMAL OPERATION and the reprt is NOT printed. When Blean_expressin is FALSE, an assertin vilatin ccurs and the reprt is printed t the cnsle (and lg file). Default message: "in vilatin" printed t cnsle 22 Severity Level Optinal SEVERITY clause: Severity_level can be ne f {NOTE, WARNING, ERROR, r FAILURE} (Default is ERROR). Actin n different severity_level is implementatin dependent. TESTPOINT1 <= RESET and ABORT; assert nt ( TESTPOINT1 ='1' ) reprt "watch ut: reset and abrt active at the same time" severity nte; When is the assert statement executed? When is the reprt printed? 23 24

5 Summary -- build SR flip/flp: U1: NAND2 prt map ( SET_B, QB, Q ); U2: NAND2 prt map ( CLR_B, Q, QB ); assert nt ( SET_B = '0' andclr_b = '0' ) reprt "input vilatin: SET_B=" & value(set_b) & " CLR_B=" & value(clr_b); -- NOTE: functin "value" is a VHDL93 extensin Cncurrent statements Order nt imprtant A prcess blck is a cncurrent statement Selected/cnditinal signal assignments Next time: Data types and attributes, pp

Announcement. VHDL in Action. Review. Statements. Process Execution with no sensitivity list. Sequential Statements

Announcement. VHDL in Action. Review. Statements. Process Execution with no sensitivity list. Sequential Statements Annuncement Prject 2: Assigned tday, due 9/30 ning f class. VHDL in Actin Mdeling a binary/gray cunter. As always, start early Chapter 3 Sequential Statements 1 Review Statements Architecture bdy Cncurrent