Last time. VHDL in Action. Motivation. Covered in This Lesson. Packages. Packages (cont'd)

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1 Last time VHDL in Actin Packages and Libraries Ch 3, pp Versin f wavefrm updating algrithm t handle reject clauses Macr and micr time Delta delays: Ensure crrect rdering f zer time events Martin Cvered in This Lessn Mtivatin Packages Libraries TextIO Why have subprgrams? Readability Design re-use Sharing Packages and libraries are the mechanism fr design re-use and sharing Martin Martin Packages Packages (cnt'd) Observatins: Including functin and prcedure declaratins within ARCHITECTURE / PROCESS blcks is awkward. Can't share between architectures Nt very readable Nt very maintainable Have t cut/paste subprgram int every unit that uses it Better apprach: Grup lgically related sets f functins and prcedures int a mdule that can be easily shared amng distinct designs and peple. Prmte reuse Easier t maintain Package Martin Martin

2 Package Preview Package Preview (cnt'd) A Package cntains tw parts: Package declaratin: PACKAGE pname IS < prttypes f package cmpnents> END pname; Cntains list f available package cmpnents, functins, types, prcedures, etc. Package Bdy PACKAGE BODY pname IS < Cntains package cmpnent definitins> END pname; A listing f the implementatins f package cmpnents Martin Martin Example Package(1 f 2) Example Package(2 f 2) PACKAGE sub_std_lgic_1164 IS TYPE std_ulgic IS ( 'U', --uninitialized 'X', -- frcing unknwn '0', -- frcing 0 '1', -- frcing 1 'Z', -- high impedance 'W', -- weak unknwn 'L', -- weak lw 'H', -- weak high '-' -- dn't care ); Martin TYPE std_ulgic_vectr IS ARRAY (Natural RANGE <>) OF std_ulgic; FUNCTION "AND" ( l, r : std_ulgic) RETURN std_ulgic; FUNCTION "AND" ( l, r : std_ulgic_vectr) RETURN std_ulgic_vectr; FUNCTION "AND" ( l : std_ulgic_vectr, r : std_ulgic) RETURN std_ulgic_vectr; COMPONENT dff PORT ( d, clk : IN std_ulgic; q : OUT std_ulgic); END COMPONENT; END sub_std_lgic_1164; Martin Example Package Bdy Example Package Bdy PACKAGE BODY sub_std_lgic_1164 IS FUNCTION "AND" ( l, r : std_ulgic) RETURN std_ulgic IS VARIABLE tmp : std_ulgic; tmp := 1 WHEN l = 1 AND r= 1 ELSE 0 WHEN l= 0 OR r= 0 ELSE X ; RETURN( tmp); END AND ; FUNCTION "AND" ( l, r : std_ulgic_vectr) RETURN std_ulgic_vectr IS VARIABLE tmp : std_ulgic_vectr; ASSERT l range = r range; REPORT Ranges must be equal fr vectr AND ; SEVERITY ERROR; FOR k in l range LOOP tmp(k) := l(k) AND r(k); END LOOP; RETURN tmp; END AND ; Martin Martin

3 Example Package Bdy Referencing Packages FUNCTION "AND" ( l: std_ulgic_vectr; r: std_ulgic) RETURN std_ulgic_vectr IS VARIABLE tmp : std_ulgic_vectr; FOR k in l range LOOP tmp(k) := l(k) AND r; END LOOP; RETURN tmp; END AND ; USE Clauses Placed befre an entity declaratin, giving the entity and assciated architectures access t the package cntents Syntax: USE library.package_name.cmpnent ; USE wrk.sub_std_1164.dff, wrk.mypack.tff; END sub_std_lgic_1164; Martin Martin Aut Package Libraries The package STANDARD is autmatically made visible t all entities. STANDARD defines: Bit Bit_Vectr Blean Integer Real Character String Time Martin Design units are analyzed (cmpiled) and placed in libraries Lgical library names map t physical directries Libraries STD and WORK are implicitly declared, i.e. dn't have t have "LIBRARY WORK;" in file Martin Libraries Libraries--Dh! Hw abut this: library IEEE; entity test_libs is prt (clk : in bit; data_ut : ut bit); end test_libs; When multiple design units are in the same file, visibility f libraries and packages must be established fr each primary design unit (entity, package header, cnfiguratin) separately! The use clause may selectively establish visibility, e.g., nly the functin rising_ edge() is visible within entity design-2 Martin architecture h_n f test_libs is -- use ieee.std_lgic_1164.all; signal s1 : std_lgic; begin s1 <= '0'; end h_n; Uncmment this line t cmpile crrectly If the entity makes the library visible, the architecture can have the "use" statement in the architecture. Martin

4 Libraries--Dh! USE Clauses Hw abut this: entity test_libs2 is prt (clk : in bit; data_ut : ut bit); end test_libs2; architecture h_n f test_libs2 is library ieee; use ieee.std_lgic_1164.all; signal s1 : std_lgic; begin s1 <= '0'; end h_n; This wn't cmpile--the library clause can't appear in the declarative regin f the architecture. It will cmpile if the library clause is mved just befre the architecture statement... Martin T access all cmpnents f a package: USE wrk.sub_std_lgic_1164.all; Nte: packages can use material defined in ther packages: USE wrk.basics.all; PACKAGE mre_detail IS END mre_details; With this, a hierarchy f packages can be created. Martin Visibility Visibility (1 f 3) Reference t a variable/signal/cnstant depends upn the scpe f the bject and the declaratin regin Reference t bjects declared in a higher scpe can be made with. (dt) ntatin: B.X, WORK.SIG.X, Y.X Martin Example frm text: PACKAGE sig IS SIGNAL x : Integer := 1; END sig; USE wrk.sig; -- Package sig made visible ENTITY y IS SIGNAL x : Integer := 2; END y; ARCHITECTURE z OF y IS SIGNAL z1, z2, z3, z4, z5 : Integer := 0; FUNCTION R RETURN INTEGER IS VARIABLE x : Integer := 3; RETURN x; -- When R called, 3 returned END R; Martin Visibility (2 f 3) Visibility (3 f 3) B: BLOCK SIGNAL x : Integer := 4; SIGNAL z6: Integer := 0; z6 <= x + y.x; -- z6 = END BLOCK B; Martin PROCESS VARIABLE x : Integer := 5; z5 <= x; -- z5 = 5 WAIT; END PROCESS; z1 <= WORK.SIG.x; -- z1 = 1 z2 <= x; -- z2 = 2 z3 <= R; -- z3 = 3 z4 <= B.x; -- z4 = 4 END z; Martin

5 Libraries Libraries Successfully analyzed mdels are stred in a library A library may cnsist f several mdels which may reference ne anther may be arranged in a hierarchical fashin Tw types f libraries: WORK: current analysis entered here RESOURCE: read-nly reference libraries Martin Libraries cntain PRIMARY and SECONDARY units: Primary units: Entities Package Cnfiguratin Secndary units: Architectures Package bdies Primary units must be analyzed befre crrespnding secndary units. Bth must be in the same library. Martin Library Names Library Names Libraries have LOGICAL and PHYSICAL names: Lgical name: Used by the VHDL mdel Prtable, independent f the simulatr Physical name: Used by the hst perating system Dependent upn hst platfrm The VHDL simulatr must ffer sme means f mapping Lgical names t Physical names: In LDV, mapping is in the CDS.lib file: include $CDS_INST_DIR/tls/inca/files/cds.lib define wrk C:/tm/curses/4514f03/ther_cde/wrk Indirectly, the glbal CDS.lib file has: DEFINE std./std DEFINE synpsys./synopsys DEFINE ieee./ieee DEFINE ambit./ambit Martin Martin Making Libraries Visible Creating Libraries T make a library visible, entry must exist in mapping file In yur VHDL cde, visibility cntrlled by LIBRARY cmmand: LIBRARY WORK; -- Autmatic in all VHDL mdels LIBRARY IEEE; Access t library cmpnents is dne with the USE cmmand: USE IEEE.Std_Lgic_1164.ALL; -- In the library IEEE, make the package -- STD_LOGIC_1164 visible t the -- fllwing entity. Martin Implementatin dependent In LDV: Edit->Add->New Library Give a lgical name and a directry File->Set wrk library Set this t the lgical name Analyze cde int the library Add library/use clauses t yur ther mdels Be sure t set wrk library back t yur riginal wrk library Martin

6 Where the libraries ram TextIO In default install f LDV, IEEE packages are in C:\Prgram Files\Cadence Design Systems\LDV\tls\inca\files\IEEE.src std_lgic_1164 package: std_lgic_1164.vhd It s useful t lk thrugh the packages fr functins yu can use We ll g thrugh them in class next week. Files can be distinguished by the type f infrmatin stred Package TEXTIO Declares: type line is access string; type text is file f string ; Use STD.TextIO.all; VHDL 1987: file infile : text is in inputdata. txt ; file utfile : text is ut utputdata. txt ; Martin Martin Using TextIO: Example prcedure read_v1d(variable f:in text; v:ut std_lgic_vectr) is variable buf : line; variable c : character ; begin -- d nt frget apprpriate library declaratins readline (f, buf ); --read a line frm the file. fr i in v range lp read( buf, c ) ; --read a character frm the line. case c is when X => v (i) := X ; when U => v (i) := U ; when Z => v (i) := Z ; when 0 => v (i) := 0 ; when 1 => v (i) := 1 ; when - => v (i) := - ; when W => v (i) := W ; when L => v (i) := L ; when H => v (i) := H ; when thers => v (i) := 0 ; end case; end lp; end; (Frm Yalamanchili) Martin TextIO and testbenches Remember: Testbench instantiates the system t be tested and a stimulus driver Stimulus can be frm: n the fly generatin lcal cnstant arrays file I/O Can als save results t file fr later viewing Martin Summary Packages and libraries Share yur VHDL cde with friends and neighbrs TextIO Next time: Review fr midterm Martin