1.2 Nexys-3 board Between divclk[16] and divclk[20], divclk[ ] is faster than divclk[ ]. It is faster by a factor of.

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1 ee354l_quiz_fall2016.fm 1.2 Nexys-3 board F E A G D B C You are aware of the scanning mechanism for the four SSDs in Nexys-3 and the 12 pins (4 anodes + cathodes =12 pins) involved in controlling the SSDs. Say, we want to build N3_Super with SSDs in the place of the 4 and another N3_Budget with just 2 SSDs in the place of the 4. State increases or decreases in pins because of this. N3_Super: N3_Budget: Mr. (Bruin/Trojan) says that, since all four dot points are tied together, you can either make them all light together or make them all off together. Explain In the place of the four 7-seg (plus dp for dot point) if we use four 16-seg (plus dp for dot point), what is the impact on pins on FPGA (used up for this display purpose)? Between divclk[16] and divclk[20], divclk[ ] is faster than divclk[ ]. It is faster by a factor of You have seen the following code excerpt for generating the anode controls. assign An0 assign An1 assign An2 assign An3 = ~(~(divclk[16] ) && ~(divclk[15])); = ~(~(divclk[16] ) && (divclk[15])); = ~( (divclk[16] ) && ~(divclk[15])); = ~( divclk[16] ) && (divclk[15])); What happens if we rewrite the code as shown below basically ORing with divclk[25]. assign An0 = divclk[25] (~(~(divclk[16] ) && ~(divclk[15]))) ; assign An1 = divclk[25] (~(~(divclk[16] ) && (divclk[15]))); assign An2 = divclk[25] (~( (divclk[16] ) && ~(divclk[15]))); assign An3 = divclk[25] (~( divclk[16] ) && (divclk[15]))); When you press pushbutton BTNL on the Nexys, you convey (logic 1/logic 0) to pin C4. 10/5/16 EE354L Quiz - Fall / 6 C Copyright 2016 Gandhi Puvvada

2 ee354l_quiz_fall2016.fm 1.2 Nexys-3 board F E A G D B C You are aware of the scanning mechanism for the four SSDs in Nexys-3 and the 4anodes + cathodes =12 pins involved in controlling the SSDs. Say we want to build Nexys-3_Super with SSDs in the place of the four and another Nexys-3_budget with just 2 SSDs in the place of 4. State increase or decrease in pins because of this Mr. (Bruin/Trojan) says that, since all four dot points are tied together, you can either make them all lit together or make them all off together. Explain In the place of the four 7-seg (plus dp for dot point) if we use four 16-seg (plus dp for dot point), what is the impact on pins on FPGA (used up for this display purpose)? Between divclk[16] and divclk[25], is faster than. It is faster by a factor of You have seen the following code excerpt for generating the anode controls. assign An0 assign An1 assign An2 assign An3 = ~(~(divclk[16] ) && ~(divclk[15])); = ~(~(divclk[16] ) && (divclk[15])); = ~( (divclk[16] ) && ~(divclk[15])); = ~( divclk[16] ) && (divclk[15])); What happens if we rewrite the code as shown below basically ORing with divclk[25]. assign An0 = divclk[25] (~(~(divclk[16] ) && ~(divclk[15]))) ; assign An1 = divclk[25] (~(~(divclk[16] ) && (divclk[15]))); assign An2 = divclk[25] (~( (divclk[16] ) && ~(divclk[15]))); assign An3 = divclk[25] (~( divclk[16] ) && (divclk[15]))); When you press pushbutton BTNL on the Nexys, you convey (logic 1/logic 0) to pin C4. 10/5/16 EE354L Quiz - Fall / 6 C Copyright 2016 Gandhi Puvvada

3 ee354l_quiz_fall2015.fm 6 ( = 1 points) 15 min. Nexys-3 board F E A G D B C In the I/O design on the side, Pin C4 is an (input/output) pin. Pin U16 is an (input/output) pin. Pin N16 is an (input/output) pin. Pin T17 is an (input/output) pin. 6.2 Extract from our test_nexys3_verilog.v : 6 Student XYZ used divclk[1:17] for the sev_seg_clk where as student ABC used divclk[14:13]. Hence student XYZ is scanning at a (higher/same/lower) frequency. His SSDs will glow with intensity (brighter/same/dimmer ) than our SSDs. Hence student ABC is scanning at a (higher/same/lower) frequency. Her SSDs will glow with intensity (brighter/same/dimmer ) than our SSDs. 6.3 In a design, if we wanted to display 7777 (each digit with 7 only without any dot point), you (need / do not need) scanning control. Explain briefly how you would get this 7777 displayed with least amount of hardware. The remaining 7 weeks are very crucial for EE354L. Please use our office hours. The grader, the TAs, and I are eager to help you. Best wishes, Gandhi 10/12/15 EE354L Quiz - Fall / 6 C Copyright 2015 Gandhi Puvvada

4 ee354l_quiz_fall2015.fm 6 ( points) min. Nexys-3 board F E A G D B C 6.1 In the I/O design on the side, Pin C4 is an (input/output) pin. Pin U16 is an (input/output) pin. Pin N16 is an (input/output) pin. Pin T17 is an (input/output) pin. 6.2 Extract from our test_nexys3_verilog.v : Student XYZ used divclk[1:17] for the sev_seg_clk where as student ABC used divclk[14:13]. Hence student XYZ is scanning at a (higher/same/lower) frequency. His SSDs will glow with intensity (brighter/same/dimmer ) than our SSDs. Hence student ABC is scanning at a (higher/same/lower) frequency. Her SSDs will glow with intensity (brighter/same/dimmer ) than our SSDs. 6.3 In a design, if we wanted to display 7777 (each digit with 7 only without any dot point), you (need / do not need) scanning control. Explain briefly how you would get this 7777 displayed with least amount of hardware. The remaining 7 weeks are very crucial for EE354L. Please use our office hours. The grader, the TAs, and I are eager to help you. Best wishes, Gandhi 10/12/15 EE201L Quiz - Fall / 6 C Copyright 2015 Gandhi Puvvada

5 4 ( 10 points) 10 min. Reproduced below is a question and its solution from the Quiz of Spring Scanning control alteration to adjust the intensity. // The clock divider is just for your information reg [26:0] divclk; board_clk, posedge reset) begin if (reset) divclk <= 0; else divclk <= divclk + 1'b1; end assign sev_seg_clk = divclk[16:15]; // In the following four lines from the original design, I have replaced An0 with An0_I (standing for Anode 0 Intermediate) and similarly the other three. assign An0_I= ~(~(sev_seg_clk[1]) && ~(sev_seg_clk[0])); // when sev_seg_clk = 00 assign An1_I= ~(~(sev_seg_clk[1]) && (sev_seg_clk[0])); // when sev_seg_clk = 01 assign An2_I= ~( (sev_seg_clk[1]) && ~(sev_seg_clk[0])); // when sev_seg_clk = 10 assign An3_I= ~( (sev_seg_clk[1]) && (sev_seg_clk[0])); // when sev_seg_clk = 11 // In the following four lines, I have used divclk[17] and divclk[1] to keep a signal such as An0 // active or inactive (you figure it out) for extended length of time. assign An0 = (An0_I) (divclk[1]); // ORed with the (divclk[1]) assign An1 = (An1_I) (divclk[1]); // ORed with the (divclk[1]) assign An2 = (An2_I) (divclk[17]); // ORed with the (divclk[17]) assign An3 = (An3_I) (divclk[17]); // ORed with the (divclk[17]) Since An0 and An1 were altered in one way and An2 and An3 were altered in a different way, we expect SSD0 and SSD1 to glow with different intensity compared to SSD2 and SSD3. February 24, :00 am EE354L Quiz - Spring / 7 C Copyright 2016 Gandhi Puvvada

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7 ee354_quiz_fall201.fm 2.3 You had gone through a past exam question where SSDs were controlled in intensity. Given below is the waveform of divclk [15:19] so that you can perform ORing or ANDing or any combination of these or any logic operation on the GL_I, G1_I, G2_I, GR_I Based on the way the LEDs are connected to the Spartan-6 FPGA on Nexys-3 board, you would produce a (zero / one) on GR_I to light up LD1 LD0. Seven students tried to control GR_I s intensity, by ORing and/or ANDing as shown below. Comment on each student (or groups of students) using words like, wrong design, right design with intensity increased say by a factor of 1.25 or to 125% or decreased say by a factor of 2 or to 50%, etc. assign GR = GR_I divclk[1]; // Student #1 assign GR = GR_I & divclk[1]; // Student #2 assign GR = GR_I (divclk[1] divclk[19]); // Student #3 assign GR = GR_I (divclk[1] & divclk[19]); // Student #4 assign GR = GR_I & (divclk[1] divclk[19]); // Student #5 assign GR = GR_I & (divclk[1] & divclk[19]); // Student #6 assign GR = GR_I ~(divclk[1] divclk[19]); // Student #7 assign GR = GR_I & ~(divclk[1] divclk[19]); // Student # Now make the four groups of LEDs glow in 4 different intensities such that the GL glows with the highest intensity and GR glows with the lowest intensity. Write the assign statements below. 7+3 October 1, 201 6:13 am EE354L Quiz - Fall / 9 C Copyright 201 Gandhi Puvvada

8 ee354_quiz_fall201.fm 2.3 You had gone through a past exam question where SSDs were controlled in intensity. Given below is the waveform of divclk [15:19] so that you can perform ORing or ANDing or any combination of these or any logic operation on the GL_I, G1_I, G2_I, GR_I Based on the way the LEDs are connected to the Spartan-6 FPGA on Nexys-3 board, you would produce a (zero / one) on GR_I to light up LD1 LD0. Seven students tried to control GR_I s intensity, by ORing and/or ANDing as shown below. Comment on each student (or groups of students) using words like, wrong design, right design with intensity increased say by a factor of 1.25 or to 125% or decreased say by a factor of 2 or to 50%, etc. assign GR = GR_I divclk[1]; // Student #1 assign GR = GR_I & divclk[1]; // Student #2 assign GR = GR_I (divclk[1] divclk[19]); // Student #3 assign GR = GR_I (divclk[1] & divclk[19]); // Student #4 assign GR = GR_I & (divclk[1] divclk[19]); // Student #5 assign GR = GR_I & (divclk[1] & divclk[19]); // Student #6 assign GR = GR_I ~(divclk[1] divclk[19]); // Student #7 assign GR = GR_I & ~(divclk[1] divclk[19]); // Student # Now make the four groups of LEDs glow in 4 different intensities such that the GL glows with the highest intensity and GR glows with the lowest intensity. Write the assign statements below. 7+3 October 1, 201 6:13 am EE354L Quiz - Fall / 9 C Copyright 201 Gandhi Puvvada