Fall 2016 Instructor: Gandhi Puvvada. Thursday, 9/22/2016 (A 2H 50M exam) 05:30 PM - 08:20 PM (170 min) in THH101. Student s Last Name:

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1 EE457 Quiz (~0%) Closed-book Closed-notes Exam; No cheat sheets; No cell phones or computers Calculators and Verilog Guides are not needed and hence not allowed. Fall 206 Instructor: Gandhi Puvvada Thursday, 9/22/206 (A 2H 50M exam) 05:30 PM - 08:20 PM (70 min) in THH0 Student s Last Name: Student s First Name: Student s DEN D2L Ques# Topic Page# Time Points Score State Diagram, RTL Design min CPU Performance 5 20 min Unsigned and Signed numbers 6 20 min MIPS ISA, Byte-addressable processors min Single-Cycle CPU 0-25 min. 45 Total 60 min. 238 Perfect Score 230 Viterbi School of Engineering University of Southern California September 22, 206 0:09 am EE457 Quiz - Fall 206 / 2 C Copyright 206 Gandhi Puvvada

2 ( = 68 points) 50 min. State Diagram and RTL design (Iteration counter advancement and terminal count checking): 7. A rectangular array of bits, A[I,J], are to be cleared starting from A[,5] to A[5,]. It is a total of 25 bits as shown in the diagram. Row index I goes from to 5 and Column index J goes from 5 to. RESET The clearing is done row by row from the top row (I == ) to the bottom row (I == 5). And with in a row, we start from the right end (J == 5) to the left end (J == ). It is a row-major order as shown in the pseudo code. Complete the state diagram below. START INI I<= ; J<= 5; START C I CLR A[I,J] <= 0; if (J!= ) J <= J - ; else { J <= ; I <= I + ; } J for (I = ; I <= 5; I++) { for (J = 5; J >= ; J--) A[I][J] = 0; } When you reach the DONE state what are the values of I,J? I = ; J = ; C C = (I == ) (J == ) Number of clocks spent in CLR state = ACK DONE ACK 8.. You know that a later assignment over-rides an earlier assignment in a procedural block of Verilog HDL. Complete the two RTL snippets for the CLR case branch. You can use a statement such as I <= I; or J <= J; if needed in your if statement. In the left-side RTL, J is by default decremented and this decrementation is over-ridden as needed. In the right-side RTL, I is by default incremented and this incrementation is over-ridden as needed. CLR: begin A[I,J] <= 0; J <= J - ; // by default if ( CLR: begin A[I,J] <= 0; I <= I + ; // by default if ( end end September 22, 206 0:09 am EE457 Quiz - Fall / 2 C Copyright 206 Gandhi Puvvada

3 3.2 How many B[K] locations are cleared in the completed state diagram below? RESET START K = ACK INI CLR DONE K<= 2; START B[K] <= 0; K = K <= K - ; ACK 8.3 Complete the state diagram below to clear 50 bits of A[I,J,K] (25 bits of A [I,J,2] and 25 bits of A [I,J,] ). Like in Q#., for each of the two values of K, the I and the J can be made to go from [I,J]=[5,] to [I,J]= [,5]. The array A is maintained in a flash memory. You for (K = 2; K >= ; K--) { for (I = ; I <= 5; I++) { for (J = 5; J >= ; J--) A[I,J,K] = 0; } } perhaps know that flash memory takes several clocks to write to it. For the sake of this problem, let us say that we need a minimum of two clocks to write to it and we need to wait until we get a positive indication from the flash memory status output FWD (FWD = Flash memory Writing Done) in the form of (FWD == ). The Flash memory is not expected to update FWD properly in the first clock when you start writing. So we should not assume that it finished writing even if we see FWD = during the first clock. A Flag F, initially cleared to zero, can be used to make sure that we keep I, J, and K unchanged at least for one clock. At the end of the first clock, the flag F is set indicating that the FWD can be relied upon. From the 2nd clock onwards we wait for (FWD == ) to update the location coordinates, I, J, and K, and clear the Flag F. START C ACK RESET INI I<= ; J<= 5; K<= 2; F<= 0; START CLR A[I,J,K] <= 0; if (J!= ) J <= J - ; else if ( { J <= ; else { I <= I + ; } C = C When you reach the DONE state what are the values of I,J,K,F? I = ; J = ; K = ; F = ; DONE } ACK September 22, 206 0:09 am EE457 Quiz - Fall / 2 C Copyright 206 Gandhi Puvvada

4 .4 You have done the Min/Max lab Part (with two comparators) and Part 2 (with one comparator). Part takes a constant number of clocks (+5 = 6) where as Part 2 takes a variable number of clocks (+5 = 6 at minimum for an ascending data and + 5*2 = 3 at maximum for a descending data). Here you are given a dual port memory M and two comparators, and are asked to improve the best case. The Comparator #0 looks at all even numbered locations M[I] and arrives at one set of results, Max0 and Min0. The Comparator # looks at all odd numbered locations M[J] and arrives at another set of results, Max and Min. Finally we have a Merge state, where we compare the two sets of results (Comp#0 compares Max0 and Max while Comp# compares Min0 and Min) and arrive at the final results, Max and Min. So the best case is +7+=9 clocks for an ascending data. The worst case is +4+=6 for a descending data. So, while in the CMxMn state, if one of the two, Com#0 or Comp#, has finished its job before the other, he should just wait. Only either when both are about to be done together or when one is done and the other is about to be done, you should prepare to move to the Merge state. An inferior designer waits until both are done (rather than about to be done) and wastes one clock. We will send him back to EE354L. Here I and J counters are 5 bit counters. I starts with and J starts with Each is incremented by 2 whenever it needs to be incremented (I<=I+2; J<=J+2;). So I remains even always and J remains odd always. When I is done, it becomes 6 (0000) and when J is done, it becomes 7 (000). You may be able to use some or all of the following conditions in your design. (I==4), (I!=4), (I==6), (I!=6), (J==5), (J!=5), (J==7), (J!=7), M[I] >= Max0, M[I] <= Min0, M[J] >= Max, M[J] <= Min, Max >= Max0, Min <= Min0, 6 Reset Start State Diagram for Part 2 for Dual-Port Memory 2 flags, 2 comparators, 2 counters. INI LOAD Flag0<=0; Start Min0 <= M[I]; I <= 0; Max0 <= M[I]; Flag<=0; I <= I + 2; J <= ; Min <= M[J]; Max <= M[J]; J <= J + 2; DONE C CMxMn Merge if (Max >= Max0) Max <= Max; else Max <= Max0; if (Min <= Min0) Min <= Min; else Min <= Min0; C September 22, 206 0:09 am EE457 Quiz - Fall / 2 C Copyright 206 Gandhi Puvvada

5 6 You need to complete the design on the previous page by (a) filling up "0" or "" in the six boxes (b) writing I <= I + 2; or J <= J + 2; at appropriate places in the code (c) and finally figuring out the condition "C" governing state transition from CMxCMn state to the Merge state. Write the long boolean expression below for the condition C. C = 2 ( = 28 points) 20 min. Performance Let us say, we are a hardware IP (Intellectual Property) vendor. We designed a Multiply instruction execution IP which takes 20 clocks at 2 GHz and sold the IP to two processor manufacturers, XYZ and ABC, who implemented our USC CISC ISA. The frequency of usage of the multiply instruction (in the dynamic execution trace of the binary produced by compiling the benchmark by a third party compiler) is 0%. Both processors ran at 2 GHz. But percentage of execution time spent on our Mult instruction is 20% in XYZ and 25% in ABC.. If you have adequate data, compare the performance of the two processors. If the data is inadequate, explain how it is inadequate. Also, if there is excessive data, state what is excessive. 2. If you have adequate data, compare the native MIPs ratings of the two processors. If the data is inadequate, explain how it is inadequate. 3. If you have adequate data, compare the relative MIPs ratings of the two processors. If the data is inadequate, explain how it is inadequate % improvement in Instruction A is better than 0% improvement in Instruction B, if (select) (a) frequency of occurrence of A in the dynamic execution trace is more than that of B (b) percentage of execution time spent on A is higher than that of B (c) CPI of A is higher than CPI of B (d) none of the above Reducing clocks taken by Instruction A by clock is better than reducing clocks taken by Instruction B by clock, if (select) (a) frequency of occurrence of A in the dynamic execution trace is more than that of B (b) percentage of execution time spent on A is higher than that of B (c) CPI of A is higher than CPI of B (d) none of the above September 22, 206 0:09 am EE457 Quiz - Fall / 2 C Copyright 206 Gandhi Puvvada

6 3 ( = 35 points) 20 min. unsigned and signed numbers 0 3. If you are allowed to use numbers from the SW (South-West) quadrant only (as shown in the figure below) you can only arrive at some of the 8 combinations in the table on the side. Cross off the rows, which are not possible to fill with these limited choices. Complete the last two columns for the remaining rows. UNSIGNED SW LARGER mag. SMALLER mag. Error point: C bit is set bit Circles Just FYI SIGNED SW SMALLER mag. LARGER mag. +3 Error Point: V bit is set Operation Addition Addition Addition Addition Subtraction Subtraction Subtraction Subtraction Result / if numbers are treated as signed numbers Result / if numbers are treated as unsigned numbers V Raw OVERFLOW Carry C4 (COUT) Given two 4-bit numbers A (a 3 a 2 a a 0 ) and B (b 3 b 2 b b 0 ), produce 2AleB_BW. 2AleB_BW stands for 2A (double of A) le (less than or equal) to B BW both ways (BW = both ways = whether we treat A and B as signed numbers in 2 s complement notation or unsigned numbers). Let us analyze to see which cases need an actual comparator to compare and which can be concluded easily. To double A (a 3 a 2 a a 0 ), we can append a zero at the right-end whether A is signed (2 s comp) or unsigned, so basically we are comparing a 3 a 2 a a 0 0 with b 3 b 2 b b 0. T / F If a 3 is a, we can conclude 2AleB_BW as (true/false) without any comparator because when A and B are considered to be (signed/unsigned), the 2A is too (big/ small) for any B to match up. For the remaining part, i.e for (a 3 =0), we need to consider the two cases, (b 3 =0) and (b 3 =). For the case [(a 3 =0) and (b 3 =)], we can conclude 2AleB as false, without any comparator, if both A and B are treated as (signed/unsigned) numbers. For the case [(a 3 =0) and (b 3 =0)], since both are positive, we can use an unsigned 4-bit comparator to find if 2AleB is true or not by comparing a 2 a a 0 0 with b 3 b 2 b b 0 T / F. If a 2 a a 0 is lower than b 3 b 2 b then a 2 a a 0 0 is lower than b 3 b 2 b b 0 even if b 0 is a. T/F However, for a 2 a a 0 0 to be equal to b 3 b 2 b b 0, the b 0 needs to be a (0 / ) Complete the 3-bit unsigned comparison below to compare a 2 a a 0 with b 3 b 2 b. Combine it with b 0 to produce an IntR ( = intermediate result) standing for a 2 a a 0 0 is lower than or equal to b 3 b 2 b b 0. Combine this with requirements on a 3 and b 3 to produce the final inference 2AleB_BW. b b b Y2 Y Y0 a2 a a0 X2 X X0 ADD/SUB VDD 2AleB_BW Carry RawCarry a b cout cin s a b cout cin s a b cout cin s S2 S S0 d2 d d0 C0 d2 d d0 Zero IntR_Lower IntR_Equal IntR V September 22, 206 0:09 am EE457 Quiz - Fall / 2 C Copyright 206 Gandhi Puvvada

7 4 ( = 62 points) 45 min. MIPS ISA, Byte-addressable processors 2 4. It is possible to replace the unconditional branch, beq $0,$0, L2 with a jump j L2 or with a jr $8 provided $8 is loaded as shown below. The worst choice of the three is (select one) (i) beq $0,$0, L2; (ii) j L2; (iii) lui $8, 0000h; ori $8, $8, 006Ch; jr $8; // upstream code 40 beq $, $2, L; 44 addu $4, $0, $0; 48 beq $0, $0, L2; L(=4C) L2(=6C)... Explain: Arrive at the 6-bit offset field in the translation of beq $0,$0, L2 on the side Reproduced below is an extract from your class-notes September 22, 206 0:09 am EE457 Quiz - Fall / 2 C Copyright 206 Gandhi Puvvada

8 I have corrected the textbook code incorrectly because I assumed that The "add" in the five-instruction rectangle can be replaced by "addi $29, $29, 4" to add a 4 to move the stack pointer $29. Similarly the "sub" can be replaced by " " to subtract a 4 to move the stack pointer $ A student wrote the above code initially and later while debugging he decided that the call to subroutine C was not required. But he just deleted the jal C instruction instead of deleting all the 5 instructions in the rectangles! Is it that it is just wasteful that he is executing 4 instructions or is it harmful? Answer the above question again, this time assuming that it is a conditional call instruction beqal $, $2, C in the place of jal C. Recall the made-up instruction beqal (branch if equal and link) we used in an earlier exam question, where we write to the link register $3 conditionally Based on the above analysis, Mr. (Bruin / Trojan) recommends removal of the AND gate and OR gate in the rectangle by redefining the beqal as conditional call which unconditionally deposits the return address into the link register $3. And he further requires that every use of beqal should be preceded by two lines to (save/ retrieve) the contents of $3 on the compiler designated stack and followed by two lines to (save/retrieve) the return address saved on the stack into the link register $ The textbook and the class-notes show a (SRAM / SSRAM) for the Level Data Cache (shown as Data Memory in chapter 5) (though/because) in real design we use (SRAM / SSRAM) for the Level Data Cache. September 22, 206 0:09 am EE457 Quiz - Fall / 2 C Copyright 206 Gandhi Puvvada

9 Intel follows (Little Endian / Big Endian) system. In the Intel processor system address space, byte 0000_747C H is the (most / least) significant byte of the 32-bit word with system address (state in hexadecimal). State the next three 32-bit word addresses, next to the 32-bit word 40 Hex :. State the next three 64-bit long word addresses, next to the 64-bit long word 40 Hex, in the context of i860 (64-bit data 32-bit logical address byte addressable processor):. 4.5 Shown on the side is the memory interface to a byte-wide memory chip in a memory system based on minimum number of byte-wide banks for an USC28 processor (28-bit data, 32- bit logical address, byte-addressable processor). USC processors are similar to Intel processors so far as byte-enable pins are concerned. The address pins on the processor are (select) (i) A[3:0] (ii) A[3:3],/BE[7:0] (iii) A[3:4],/BE[5:0] Fill-in the 3-blanks (marked by the 3 arrows) in the figure on the side. Also find the system addresses corresponding to the lowest-addressed two bytes of this memory chip. The lowest-addressed two bytes of this chip map to the system byte addresses (in hex). The system addresses mapping to any location in this memory chip will have the same upper (state a number) bits namely (state their labels in the form X[3:2]). A[9:4] A3 A30 A29 A28 A27 A26 A25 A24 A23 A22 A2 A20 KB A[ ] D[7:0] WE RD CS If this chip goes bad, until you replace, you should avoid using memory in system address range (state the range in hex): BE4 Note D[ ] Blank area (for rough work) September 22, 206 0:09 am EE457 Quiz - Fall / 2 C Copyright 206 Gandhi Puvvada

10 5 ( = 45 points) 25 min. Single-cycle CPU: You are familiar with the ordinary jump instruction J (Jump with the 26-bit jump address field), Jal (Jump and Link), Jr rs, (Jump register rs), and the Beq (Branch if Equal). In class we discussed a made-up instruction, Beqal (Branch if equal and link, a conditional call instruction). For this question, assume that the Beqal writes unconditionally to the link register $3 the return address (PC+4). Hence the control signal "beqal" is crossed off in the control signal table below The data path on the next page is nearly complete. Complete the connections to the 7 loose ends which were marked with numbered arrows. 5.2 Control Signal Table: Complete the three rows and three columns. Whenever possible, use don t cares. Instruction ALUSrc ALUOp ALUop0 RegWrite RegDst Memtoreg MemRead MemWrite Branch beqal (not needed) JUMP Jal JR 2+9 R-format lw sw X X 0 0 beq X X 0 0 beqal J X X X 0 X X 0 0 X Jal JR rs X X X X X X X X Blank area It is not difficult to get an A in EE457. You need to work for it and seek help from the 457 teaching team on whatever you do not understand. We are eager to help you. The next three topics, pipelined CPU, cache and virtual memory are interesting and challenging too. They are the focus of the midterm exam. Then we cover advanced topics. Best! Gandhi, TAs: Sanmukh, Pezhman, Fangzhou, Mentors: Bo, Monisha, Nishant HW Graders: Hongtai, Aashish, Yashah Lab graders: Neil, Dong, Congyi September 22, 206 0:09 am EE457 Quiz - Fall / 2 C Copyright 206 Gandhi Puvvada

11 Instruction [3:0] Jump Address [3:0] PC+4 [3:28] 0 0 Jump JR Jal Control RegDst Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite PCSrc Jump JR Zero 0 0 ALU control Jal 6 7

12 Blank page: Please write your name and . Tear it off and use for rough work. Do not submit. Student s Last Name: September 22, 206 0:09 am EE457 Quiz - Fall / 2 C Copyright 206 Gandhi Puvvada