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1 ee457_quiz_fl2010.fm 10/1/10 2 ( = 46 points) 30 min. State diagram coding in Verilog (you may refer to the Cadence (Esperan) Verilog guide): Consider the following partial flowchart and the corresponding partial state diagram along with the Verilog code segments written by four students.?? C? : if () state <= ; if () state <= ; if (C) state <= ; state <= ; #1 : if (! &&! &&!C) state <= ; if (! &&! && C) state <= ; if (! && ) state <= ; #2 // there is no if state <= ; : if () state <= ; if (! && ) state <= ; if (! &&! && C) state <= ; if (! &&! &&!C) state <= ; #3 : #4 if () state <= ; if (! && ) state <= ; if (! &&! && C) state <= ; if (! &&! &&!C) state <= ; Notice that code #3 is similar to code #1, except that code #3 is perhaps unnecessarily (but harmlessly) more verbose (like my wife! don t tell her). Code #4 is formed by removing the three occurrences of "" in code #3. Code #2 is essentially the reverse ordering of code #3. Write "ight" or "Wrong" below for each. Code #1 ; Code #2 ; Code #3 ; Code #4 ; : #5 if ( ) // write or or C state <= ; if ( ) // write or or C state <= ; if ( )// write or or C state <= ; 2.2 Now consider the incomplete Code #5 on the side along with the Karnaugh map representation of the desired state transitions. If all the three,,, C, are true, state gets assigned with, gets C reassigned with and further reassigned with. Since the last 0 assignment prevails over the prior assignments, in this case, state finally goes to. Note that there is no if clause leading back to 1. Complete the "if" conditions in code #5. Else state reasons C why it can not be completed. EE457 Quiz all / 9 C Copyright 2010 Gandhi Puvvada
2 ee457_quiz_fl2010.fm 10/1/ Combinational logic coding: he result is either the sum SUM of and () or the difference DI X minus Y (XY), deping on which ever is greater. ssuming that all needed declarations are already made appropriately (as reg or wire), complete the always block below. X Y SUM DI P Q Q>P I1S Y G internal signal DI_G ) SUM DI X Y Out of the three SUM, DI,, we need to assign using (blocking / nonblocking) assignment operator only, where as we can assign using any one of the two operators. DI_G if () Sequential logic coding: he above design is modified to have registered outputs. hese registers shall be updated only in COMP state. Complete the L (datapath operations) in the COMP state (COMP case branch). he case statement is in an always block( (posedge CLK) ). X Y SUM DI I1S Y I1S Y D Q [7:0] [7:0] CLK P Q Q>P I1S Y D Q QCOMP CLK (SE == COMP) onehot CU notation SCLK DI_G Out of the three SUM, DI,,we need to assign using (blocking / nonblocking) assignment operator only, where as we SCLK COMP:// COMP state case branch SUM DI X Y DI_G if () 3 ( 10 points) 10 min. eproduced below is a all 2008 Quiz question together with its answer. all 2008 Question Number system, adder design: You are looking for a 3bit adder/subtractor, which can perform addition or subtraction of signed or unsigned 3bit numbers and produce appropriate sum/difference together with overflow information. You are given the following 4bit adder/subtractor chip. Your lab partner connected it to [2:0], [2:0], and SUM[2:0] as shown below. He is not sure whether this is so far correct and also he does not know how to proceed with X0 and Y0 (i.e. whether to connect 0,0 or 0,1, or 1,0, or 1,1). EE457 Quiz all / 9 C Copyright 2010 Gandhi Puvvada
3 ee457_quiz_all2011.fm 9/30/11 2 ( = 83 points) 60 min. State diagram design and Verilog coding 2.1 In #2 or #3, if the state machine gets stuck in state, then just say so and do not fill the values. 57 ~ESE #1 S (IL) S (EMEN) () Number of clocks spent in state Values of I, J, and K in the state: J = (EMEN) J = K = (EMEN) K = #1 Complete the state transition conditions above for the state so that the behavior is identical to the state machine on the left. 77 ~ESE #2 S (IL) S (EMEN) J <= I if (I!= 4) () ~ESE #3 S (IL) S (I = J) and (J!=K) (EMEN) J <= I if (I!= 4) (I = J) and (J!=K) () Number of clocks spent in state Values of I, J, and K in the state: Number of clocks spent in state Values of I, J, and K in the state: wo students wrote Verilog code for the #1 state machine above. Each of them claims that his design effectively behaves like the #1 state machine. he clocks spent in and the values of I, J, and K in each clock will be exactly the same. If you think that a design works, complete its conditions/thresholds in the rectangular box. Otherwise state why it does not work. 68 : // state transitions in the control unit if (I == ) state <= ; // L operations in the Data Path temp = I; J <= temp; temp = temp 1; I <= temp; K <= I 1; : // L operations in the Data Path temp = I; temp = temp 1; I <= temp; // state transitions in the control unit if (temp == ) state <= ; September 30, :22 pm EE457 Quiz all / 10 C Copyright 2011 Gandhi Puvvada
4 ee457_quiz_all2013.fm 9/28/13 3 ( 42 points) 25 min yte addressable processors: Shown on the side is the memory interface to a 64K chip in a system based on 32bit data, 32 bit logical address byteaddressable processor. Notice that the Data lines are not labeled. mong the 4 choices below, pick as many potential right choices for labeling the data lines and explain your choices. (i) D[7:0] (ii) D[15:8] (iii) D[23:16] (iv) D[31:24] Let us say, this 64K chip got burnt out. Until we replace the chip, we should avoid using a 64K range of memory locations or more or less? Specify the size of the memory space and its range in hexadecimal that we need to avoid. [17:2] K [15:0] D[7:0] WE D CS E3 D[ ] SWP operation of $4 and $5 is shown on the side for initial contents of 3 and 4. ssume that the registers and the LU are 4 bits wide (instead of 32 bits wide). Show what happens if the initial contents are 1110 and 1111 in binary. Would you use DD and SU instructions to perform the swap operation or DDU and SUU? Explain. $4 $ $4 $ State diagram coding in Verilog: he following is an extract from our all2010 quiz exam. nd we know that both code snippets (#1 and #1) (which are parts of their respective clocked always procedural blocks) correctly represent the partial state diagram on the left. : if () state <= ; if (! && ) SL_ state <= ; DL_ if (! &&! && C) state <= ; if (! &&! &&!C) state <= ; #1 : #1 if () state <= ; if (! && ) state <= ; if (! &&! && C) state <= ; if (! &&! &&!C) state <= ; SL_ DL_ EE457 Quiz all / 9 C Copyright 2013 Gandhi Puvvada
5 ee457_quiz_all2013.fm 9/28/ later (concurrent assign statement / procedural assignment) overrides an earlier such assignment in a (clocked procedural block / combinational procedural block / either / neither) What happens if we remove the lines in the two doubleline rectangles, DL_ and DL_? possible answer (removing the loop around ) is shown on the right. Do you agree with the possible answer? Yes / No If you disagree, show the correct answer by modifying one or two of the leftside diagrams. Did we violate the.i or M.E. requirements? (.I. / M.E. / oth / Neither). possible answer What happens if we remove the lines in the two singleline rectangles SL_ and SL_. possible answer is shown on the right. Do you agree with the possible answer? Yes / No If you disagree, show the correct answer by modifying one or two of the leftside diagrams. Did we violate the.i or M.E. requirements? (.I. / M.E. / oth / Neither). possible answer Synchronous counter coding: s shown on the side, many technicians code combinational logic separately and use a clocked always block just to update the registers, whereas engineers code the register together with the upstream combinational logic in one clocked always block. Engineer s way echnician s way he 2 lines in Engox: OK to leave them commented? Y/N OK to uncomment them? Y/N Engox he 2 lines in echox: OK to leave them as is? Y/N OK to comment them out? Y/N echox EE457 Quiz all / 9 C Copyright 2013 Gandhi Puvvada
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EE201L and EE560 Verilog Lecture by Gandhi Puvvada, USC always statements, t t Coding a Flip-Flop Counters, Basics of Data Path, blocking and non-blocking assignments Copyright 2008 Gandhi Puvvada 1 always
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